static struct gl_context *
nv10_context_create(struct nouveau_screen *screen, const struct gl_config *visual,
struct gl_context *share_ctx)
{
struct nouveau_context *nctx;
struct gl_context *ctx;
unsigned celsius_class;
int ret;
nctx = CALLOC_STRUCT(nouveau_context);
if (!nctx)
return NULL;
ctx = &nctx->base;
if (!nouveau_context_init(ctx, screen, visual, share_ctx))
goto fail;
ctx->Extensions.ARB_texture_env_crossbar = true;
ctx->Extensions.ARB_texture_env_combine = true;
ctx->Extensions.ARB_texture_env_dot3 = true;
ctx->Extensions.NV_fog_distance = true;
ctx->Extensions.NV_texture_rectangle = true;
if (ctx->Mesa_DXTn) {
ctx->Extensions.EXT_texture_compression_s3tc = true;
ctx->Extensions.ANGLE_texture_compression_dxt = true;
}
/* GL constants. */
ctx->Const.MaxTextureLevels = 12;
ctx->Const.MaxTextureCoordUnits = NV10_TEXTURE_UNITS;
ctx->Const.MaxTextureImageUnits = NV10_TEXTURE_UNITS;
ctx->Const.MaxTextureUnits = NV10_TEXTURE_UNITS;
ctx->Const.MaxTextureMaxAnisotropy = 2;
ctx->Const.MaxTextureLodBias = 15;
ctx->Driver.Clear = nv10_clear;
/* 2D engine. */
ret = nv04_surface_init(ctx);
if (!ret)
goto fail;
/* 3D engine. */
if (context_chipset(ctx) >= 0x17 && context_chipset(ctx) != 0x1a)
celsius_class = NV17_3D_CLASS;
else if (context_chipset(ctx) >= 0x11)
celsius_class = NV15_3D_CLASS;
else
celsius_class = NV10_3D_CLASS;
ret = nouveau_object_new(context_chan(ctx), 0xbeef0001, celsius_class,
NULL, 0, &nctx->hw.eng3d);
if (ret)
goto fail;
nv10_hwctx_init(ctx);
nv10_vbo_init(ctx);
nv10_swtnl_init(ctx);
return ctx;
fail:
nv10_context_destroy(ctx);
return NULL;
}
struct pipe_screen *
nv30_screen_create(struct nouveau_device *dev)
{
struct nv30_screen *screen = CALLOC_STRUCT(nv30_screen);
struct pipe_screen *pscreen;
struct nouveau_pushbuf *push;
struct nv04_fifo *fifo;
unsigned oclass = 0;
int ret, i;
if (!screen)
return NULL;
switch (dev->chipset & 0xf0) {
case 0x30:
if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
oclass = NV30_3D_CLASS;
else
if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
oclass = NV34_3D_CLASS;
else
if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
oclass = NV35_3D_CLASS;
break;
case 0x40:
if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
oclass = NV40_3D_CLASS;
else
if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
oclass = NV44_3D_CLASS;
break;
case 0x60:
if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
oclass = NV44_3D_CLASS;
break;
default:
break;
}
if (!oclass) {
NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
FREE(screen);
return NULL;
}
pscreen = &screen->base.base;
pscreen->destroy = nv30_screen_destroy;
pscreen->get_param = nv30_screen_get_param;
pscreen->get_paramf = nv30_screen_get_paramf;
pscreen->get_shader_param = nv30_screen_get_shader_param;
pscreen->context_create = nv30_context_create;
pscreen->is_format_supported = nv30_screen_is_format_supported;
nv30_resource_screen_init(pscreen);
nouveau_screen_init_vdec(&screen->base);
screen->base.fence.emit = nv30_screen_fence_emit;
screen->base.fence.update = nv30_screen_fence_update;
ret = nouveau_screen_init(&screen->base, dev);
if (ret)
FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
if (oclass == NV40_3D_CLASS) {
screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
}
fifo = screen->base.channel->data;
push = screen->base.pushbuf;
push->rsvd_kick = 16;
ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
NULL, 0, &screen->null);
if (ret)
FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
/* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
* this means that the address pointed at by the DMA object must
* be 4KiB aligned, which means this object needs to be the first
* one allocated on the channel.
*/
ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
.length = 32 }, sizeof(struct nv04_notify),
int
nouveau_screen_init(struct nouveau_screen *screen, struct nouveau_device *dev)
{
struct pipe_screen *pscreen = &screen->base;
struct nv04_fifo nv04_data = { .vram = 0xbeef0201, .gart = 0xbeef0202 };
struct nvc0_fifo nvc0_data = { };
uint64_t time;
int size, ret;
void *data;
union nouveau_bo_config mm_config;
char *nv_dbg = getenv("NOUVEAU_MESA_DEBUG");
if (nv_dbg)
nouveau_mesa_debug = atoi(nv_dbg);
/*
* this is initialized to 1 in nouveau_drm_screen_create after screen
* is fully constructed and added to the global screen list.
*/
screen->refcount = -1;
if (dev->chipset < 0xc0) {
data = &nv04_data;
size = sizeof(nv04_data);
} else {
data = &nvc0_data;
size = sizeof(nvc0_data);
}
ret = nouveau_object_new(&dev->object, 0, NOUVEAU_FIFO_CHANNEL_CLASS,
data, size, &screen->channel);
if (ret)
return ret;
screen->device = dev;
ret = nouveau_client_new(screen->device, &screen->client);
if (ret)
return ret;
ret = nouveau_pushbuf_new(screen->client, screen->channel,
4, 512 * 1024, 1,
&screen->pushbuf);
if (ret)
return ret;
/* getting CPU time first appears to be more accurate */
screen->cpu_gpu_time_delta = os_time_get();
ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_PTIMER_TIME, &time);
if (!ret)
screen->cpu_gpu_time_delta = time - screen->cpu_gpu_time_delta * 1000;
pscreen->get_name = nouveau_screen_get_name;
pscreen->get_vendor = nouveau_screen_get_vendor;
pscreen->get_device_vendor = nouveau_screen_get_device_vendor;
pscreen->get_timestamp = nouveau_screen_get_timestamp;
pscreen->fence_reference = nouveau_screen_fence_ref;
pscreen->fence_signalled = nouveau_screen_fence_signalled;
pscreen->fence_finish = nouveau_screen_fence_finish;
util_format_s3tc_init();
screen->lowmem_bindings = PIPE_BIND_GLOBAL; /* gallium limit */
screen->vidmem_bindings =
PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL |
PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT |
PIPE_BIND_CURSOR |
PIPE_BIND_SAMPLER_VIEW |
PIPE_BIND_SHADER_RESOURCE | PIPE_BIND_COMPUTE_RESOURCE |
PIPE_BIND_GLOBAL;
screen->sysmem_bindings =
PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_STREAM_OUTPUT |
PIPE_BIND_COMMAND_ARGS_BUFFER;
memset(&mm_config, 0, sizeof(mm_config));
screen->mm_GART = nouveau_mm_create(dev,
NOUVEAU_BO_GART | NOUVEAU_BO_MAP,
&mm_config);
screen->mm_VRAM = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
return 0;
}
void
nouveau_screen_fini(struct nouveau_screen *screen)
{
nouveau_mm_destroy(screen->mm_GART);
nouveau_mm_destroy(screen->mm_VRAM);
nouveau_pushbuf_del(&screen->pushbuf);
nouveau_client_del(&screen->client);
nouveau_object_del(&screen->channel);
nouveau_device_del(&screen->device);
}
int
nvc0_screen_compute_setup(struct nvc0_screen *screen,
struct nouveau_pushbuf *push)
{
struct nouveau_object *chan = screen->base.channel;
struct nouveau_device *dev = screen->base.device;
uint32_t obj_class;
int ret;
int i;
switch (dev->chipset & ~0xf) {
case 0xc0:
if (dev->chipset == 0xc8)
obj_class = NVC8_COMPUTE_CLASS;
else
obj_class = NVC0_COMPUTE_CLASS;
break;
case 0xd0:
obj_class = NVC0_COMPUTE_CLASS;
break;
default:
NOUVEAU_ERR("unsupported chipset: NV%02x\n", dev->chipset);
return -1;
}
ret = nouveau_object_new(chan, 0xbeef90c0, obj_class, NULL, 0,
&screen->compute);
if (ret) {
NOUVEAU_ERR("Failed to allocate compute object: %d\n", ret);
return ret;
}
ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 1 << 12, NULL,
&screen->parm);
if (ret)
return ret;
BEGIN_NVC0(push, SUBC_COMPUTE(NV01_SUBCHAN_OBJECT), 1);
PUSH_DATA (push, screen->compute->oclass);
/* hardware limit */
BEGIN_NVC0(push, NVC0_COMPUTE(MP_LIMIT), 1);
PUSH_DATA (push, screen->mp_count);
BEGIN_NVC0(push, NVC0_COMPUTE(CALL_LIMIT_LOG), 1);
PUSH_DATA (push, 0xf);
BEGIN_NVC0(push, SUBC_COMPUTE(0x02a0), 1);
PUSH_DATA (push, 0x8000);
/* global memory setup */
BEGIN_NVC0(push, SUBC_COMPUTE(0x02c4), 1);
PUSH_DATA (push, 0);
BEGIN_NIC0(push, NVC0_COMPUTE(GLOBAL_BASE), 0x100);
for (i = 0; i <= 0xff; i++)
PUSH_DATA (push, (0xc << 28) | (i << 16) | i);
BEGIN_NVC0(push, SUBC_COMPUTE(0x02c4), 1);
PUSH_DATA (push, 1);
/* local memory and cstack setup */
BEGIN_NVC0(push, NVC0_COMPUTE(TEMP_ADDRESS_HIGH), 2);
PUSH_DATAh(push, screen->tls->offset);
PUSH_DATA (push, screen->tls->offset);
BEGIN_NVC0(push, NVC0_COMPUTE(TEMP_SIZE_HIGH), 2);
PUSH_DATAh(push, screen->tls->size);
PUSH_DATA (push, screen->tls->size);
BEGIN_NVC0(push, NVC0_COMPUTE(WARP_TEMP_ALLOC), 1);
PUSH_DATA (push, 0);
BEGIN_NVC0(push, NVC0_COMPUTE(LOCAL_BASE), 1);
PUSH_DATA (push, 1 << 24);
/* shared memory setup */
BEGIN_NVC0(push, NVC0_COMPUTE(CACHE_SPLIT), 1);
PUSH_DATA (push, NVC0_COMPUTE_CACHE_SPLIT_48K_SHARED_16K_L1);
BEGIN_NVC0(push, NVC0_COMPUTE(SHARED_BASE), 1);
PUSH_DATA (push, 2 << 24);
BEGIN_NVC0(push, NVC0_COMPUTE(SHARED_SIZE), 1);
PUSH_DATA (push, 0);
/* code segment setup */
BEGIN_NVC0(push, NVC0_COMPUTE(CODE_ADDRESS_HIGH), 2);
PUSH_DATAh(push, screen->text->offset);
PUSH_DATA (push, screen->text->offset);
/* bind parameters buffer */
BEGIN_NVC0(push, NVC0_COMPUTE(CB_SIZE), 3);
PUSH_DATA (push, screen->parm->size);
PUSH_DATAh(push, screen->parm->offset);
PUSH_DATA (push, screen->parm->offset);
BEGIN_NVC0(push, NVC0_COMPUTE(CB_BIND), 1);
PUSH_DATA (push, (0 << 8) | 1);
/* TODO: textures & samplers */
return 0;
}
int
nouveau_screen_init(struct nouveau_screen *screen, struct nouveau_device *dev)
{
struct pipe_screen *pscreen = &screen->base;
struct nv04_fifo nv04_data = { .vram = 0xbeef0201, .gart = 0xbeef0202 };
struct nvc0_fifo nvc0_data = { };
uint64_t time;
int size, ret;
void *data;
union nouveau_bo_config mm_config;
char *nv_dbg = getenv("NOUVEAU_MESA_DEBUG");
if (nv_dbg)
nouveau_mesa_debug = atoi(nv_dbg);
screen->prefer_nir = debug_get_bool_option("NV50_PROG_USE_NIR", false);
/* These must be set before any failure is possible, as the cleanup
* paths assume they're responsible for deleting them.
*/
screen->drm = nouveau_drm(&dev->object);
screen->device = dev;
/*
* this is initialized to 1 in nouveau_drm_screen_create after screen
* is fully constructed and added to the global screen list.
*/
screen->refcount = -1;
if (dev->chipset < 0xc0) {
data = &nv04_data;
size = sizeof(nv04_data);
} else {
data = &nvc0_data;
size = sizeof(nvc0_data);
}
/*
* Set default VRAM domain if not overridden
*/
if (!screen->vram_domain) {
if (dev->vram_size > 0)
screen->vram_domain = NOUVEAU_BO_VRAM;
else
screen->vram_domain = NOUVEAU_BO_GART;
}
ret = nouveau_object_new(&dev->object, 0, NOUVEAU_FIFO_CHANNEL_CLASS,
data, size, &screen->channel);
if (ret)
return ret;
ret = nouveau_client_new(screen->device, &screen->client);
if (ret)
return ret;
ret = nouveau_pushbuf_new(screen->client, screen->channel,
4, 512 * 1024, 1,
&screen->pushbuf);
if (ret)
return ret;
/* getting CPU time first appears to be more accurate */
screen->cpu_gpu_time_delta = os_time_get();
ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_PTIMER_TIME, &time);
if (!ret)
screen->cpu_gpu_time_delta = time - screen->cpu_gpu_time_delta * 1000;
pscreen->get_name = nouveau_screen_get_name;
pscreen->get_vendor = nouveau_screen_get_vendor;
pscreen->get_device_vendor = nouveau_screen_get_device_vendor;
pscreen->get_disk_shader_cache = nouveau_screen_get_disk_shader_cache;
pscreen->get_timestamp = nouveau_screen_get_timestamp;
pscreen->fence_reference = nouveau_screen_fence_ref;
pscreen->fence_finish = nouveau_screen_fence_finish;
nouveau_disk_cache_create(screen);
screen->transfer_pushbuf_threshold = 192;
screen->lowmem_bindings = PIPE_BIND_GLOBAL; /* gallium limit */
screen->vidmem_bindings =
PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL |
PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT |
PIPE_BIND_CURSOR |
PIPE_BIND_SAMPLER_VIEW |
PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE |
PIPE_BIND_COMPUTE_RESOURCE |
PIPE_BIND_GLOBAL;
screen->sysmem_bindings =
PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_STREAM_OUTPUT |
PIPE_BIND_COMMAND_ARGS_BUFFER;
memset(&mm_config, 0, sizeof(mm_config));
screen->mm_GART = nouveau_mm_create(dev,
NOUVEAU_BO_GART | NOUVEAU_BO_MAP,
&mm_config);
screen->mm_VRAM = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
return 0;
}
void
nouveau_screen_fini(struct nouveau_screen *screen)
{
int fd = screen->drm->fd;
nouveau_mm_destroy(screen->mm_GART);
nouveau_mm_destroy(screen->mm_VRAM);
nouveau_pushbuf_del(&screen->pushbuf);
nouveau_client_del(&screen->client);
nouveau_object_del(&screen->channel);
nouveau_device_del(&screen->device);
nouveau_drm_del(&screen->drm);
close(fd);
disk_cache_destroy(screen->disk_shader_cache);
}
int
nv50_screen_compute_setup(struct nv50_screen *screen,
struct nouveau_pushbuf *push)
{
struct nouveau_device *dev = screen->base.device;
struct nouveau_object *chan = screen->base.channel;
struct nv04_fifo *fifo = (struct nv04_fifo *)chan->data;
unsigned obj_class;
int i, ret;
switch (dev->chipset & 0xf0) {
case 0x50:
case 0x80:
case 0x90:
obj_class = NV50_COMPUTE_CLASS;
break;
case 0xa0:
switch (dev->chipset) {
case 0xa3:
case 0xa5:
case 0xa8:
obj_class = NVA3_COMPUTE_CLASS;
break;
default:
obj_class = NV50_COMPUTE_CLASS;
break;
}
break;
default:
NOUVEAU_ERR("unsupported chipset: NV%02x\n", dev->chipset);
return -1;
}
ret = nouveau_object_new(chan, 0xbeef50c0, obj_class, NULL, 0,
&screen->compute);
if (ret)
return ret;
BEGIN_NV04(push, SUBC_COMPUTE(NV01_SUBCHAN_OBJECT), 1);
PUSH_DATA (push, screen->compute->handle);
BEGIN_NV04(push, NV50_COMPUTE(UNK02A0), 1);
PUSH_DATA (push, 1);
BEGIN_NV04(push, NV50_COMPUTE(DMA_STACK), 1);
PUSH_DATA (push, fifo->vram);
BEGIN_NV04(push, NV50_COMPUTE(STACK_ADDRESS_HIGH), 2);
PUSH_DATAh(push, screen->stack_bo->offset);
PUSH_DATA (push, screen->stack_bo->offset);
BEGIN_NV04(push, NV50_COMPUTE(STACK_SIZE_LOG), 1);
PUSH_DATA (push, 4);
BEGIN_NV04(push, NV50_COMPUTE(UNK0290), 1);
PUSH_DATA (push, 1);
BEGIN_NV04(push, NV50_COMPUTE(LANES32_ENABLE), 1);
PUSH_DATA (push, 1);
BEGIN_NV04(push, NV50_COMPUTE(REG_MODE), 1);
PUSH_DATA (push, NV50_COMPUTE_REG_MODE_STRIPED);
BEGIN_NV04(push, NV50_COMPUTE(UNK0384), 1);
PUSH_DATA (push, 0x100);
BEGIN_NV04(push, NV50_COMPUTE(DMA_GLOBAL), 1);
PUSH_DATA (push, fifo->vram);
for (i = 0; i < 15; i++) {
BEGIN_NV04(push, NV50_COMPUTE(GLOBAL_ADDRESS_HIGH(i)), 2);
PUSH_DATA (push, 0);
PUSH_DATA (push, 0);
BEGIN_NV04(push, NV50_COMPUTE(GLOBAL_LIMIT(i)), 1);
PUSH_DATA (push, 0);
BEGIN_NV04(push, NV50_COMPUTE(GLOBAL_MODE(i)), 1);
PUSH_DATA (push, NV50_COMPUTE_GLOBAL_MODE_LINEAR);
}
BEGIN_NV04(push, NV50_COMPUTE(GLOBAL_ADDRESS_HIGH(15)), 2);
PUSH_DATA (push, 0);
PUSH_DATA (push, 0);
BEGIN_NV04(push, NV50_COMPUTE(GLOBAL_LIMIT(15)), 1);
PUSH_DATA (push, ~0);
BEGIN_NV04(push, NV50_COMPUTE(GLOBAL_MODE(15)), 1);
PUSH_DATA (push, NV50_COMPUTE_GLOBAL_MODE_LINEAR);
BEGIN_NV04(push, NV50_COMPUTE(LOCAL_WARPS_LOG_ALLOC), 1);
PUSH_DATA (push, 7);
BEGIN_NV04(push, NV50_COMPUTE(LOCAL_WARPS_NO_CLAMP), 1);
PUSH_DATA (push, 1);
BEGIN_NV04(push, NV50_COMPUTE(STACK_WARPS_LOG_ALLOC), 1);
PUSH_DATA (push, 7);
BEGIN_NV04(push, NV50_COMPUTE(STACK_WARPS_NO_CLAMP), 1);
PUSH_DATA (push, 1);
BEGIN_NV04(push, NV50_COMPUTE(USER_PARAM_COUNT), 1);
PUSH_DATA (push, 0);
BEGIN_NV04(push, NV50_COMPUTE(DMA_TEXTURE), 1);
PUSH_DATA (push, fifo->vram);
BEGIN_NV04(push, NV50_COMPUTE(TEX_LIMITS), 1);
PUSH_DATA (push, 0x54);
BEGIN_NV04(push, NV50_COMPUTE(LINKED_TSC), 1);
PUSH_DATA (push, 0);
BEGIN_NV04(push, NV50_COMPUTE(DMA_TIC), 1);
PUSH_DATA (push, fifo->vram);
BEGIN_NV04(push, NV50_COMPUTE(TIC_ADDRESS_HIGH), 3);
PUSH_DATAh(push, screen->txc->offset);
PUSH_DATA (push, screen->txc->offset);
PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
BEGIN_NV04(push, NV50_COMPUTE(DMA_TSC), 1);
PUSH_DATA (push, fifo->vram);
BEGIN_NV04(push, NV50_COMPUTE(TSC_ADDRESS_HIGH), 3);
PUSH_DATAh(push, screen->txc->offset + 65536);
PUSH_DATA (push, screen->txc->offset + 65536);
PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
BEGIN_NV04(push, NV50_COMPUTE(DMA_CODE_CB), 1);
PUSH_DATA (push, fifo->vram);
BEGIN_NV04(push, NV50_COMPUTE(DMA_LOCAL), 1);
PUSH_DATA (push, fifo->vram);
BEGIN_NV04(push, NV50_COMPUTE(LOCAL_ADDRESS_HIGH), 2);
PUSH_DATAh(push, screen->tls_bo->offset + 65536);
PUSH_DATA (push, screen->tls_bo->offset + 65536);
BEGIN_NV04(push, NV50_COMPUTE(LOCAL_SIZE_LOG), 1);
PUSH_DATA (push, util_logbase2((screen->max_tls_space / ONE_TEMP_SIZE) * 2));
return 0;
}
int
nvc0_screen_compute_setup(struct nvc0_screen *screen,
struct nouveau_pushbuf *push)
{
struct nouveau_object *chan = screen->base.channel;
struct nouveau_device *dev = screen->base.device;
uint32_t obj_class;
int ret;
int i;
switch (dev->chipset & ~0xf) {
case 0xc0:
case 0xd0:
/* In theory, GF110+ should also support NVC8_COMPUTE_CLASS but,
* in practice, a ILLEGAL_CLASS dmesg fail appears when using it. */
obj_class = NVC0_COMPUTE_CLASS;
break;
default:
NOUVEAU_ERR("unsupported chipset: NV%02x\n", dev->chipset);
return -1;
}
ret = nouveau_object_new(chan, 0xbeef90c0, obj_class, NULL, 0,
&screen->compute);
if (ret) {
NOUVEAU_ERR("Failed to allocate compute object: %d\n", ret);
return ret;
}
BEGIN_NVC0(push, SUBC_CP(NV01_SUBCHAN_OBJECT), 1);
PUSH_DATA (push, screen->compute->oclass);
/* hardware limit */
BEGIN_NVC0(push, NVC0_CP(MP_LIMIT), 1);
PUSH_DATA (push, screen->mp_count);
BEGIN_NVC0(push, NVC0_CP(CALL_LIMIT_LOG), 1);
PUSH_DATA (push, 0xf);
BEGIN_NVC0(push, SUBC_CP(0x02a0), 1);
PUSH_DATA (push, 0x8000);
/* global memory setup */
BEGIN_NVC0(push, SUBC_CP(0x02c4), 1);
PUSH_DATA (push, 0);
BEGIN_NIC0(push, NVC0_CP(GLOBAL_BASE), 0x100);
for (i = 0; i <= 0xff; i++)
PUSH_DATA (push, (0xc << 28) | (i << 16) | i);
BEGIN_NVC0(push, SUBC_CP(0x02c4), 1);
PUSH_DATA (push, 1);
/* local memory and cstack setup */
BEGIN_NVC0(push, NVC0_CP(TEMP_ADDRESS_HIGH), 2);
PUSH_DATAh(push, screen->tls->offset);
PUSH_DATA (push, screen->tls->offset);
BEGIN_NVC0(push, NVC0_CP(TEMP_SIZE_HIGH), 2);
PUSH_DATAh(push, screen->tls->size);
PUSH_DATA (push, screen->tls->size);
BEGIN_NVC0(push, NVC0_CP(WARP_TEMP_ALLOC), 1);
PUSH_DATA (push, 0);
BEGIN_NVC0(push, NVC0_CP(LOCAL_BASE), 1);
PUSH_DATA (push, 0xff << 24);
/* shared memory setup */
BEGIN_NVC0(push, NVC0_CP(CACHE_SPLIT), 1);
PUSH_DATA (push, NVC0_COMPUTE_CACHE_SPLIT_48K_SHARED_16K_L1);
BEGIN_NVC0(push, NVC0_CP(SHARED_BASE), 1);
PUSH_DATA (push, 0xfe << 24);
BEGIN_NVC0(push, NVC0_CP(SHARED_SIZE), 1);
PUSH_DATA (push, 0);
/* code segment setup */
BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
PUSH_DATAh(push, screen->text->offset);
PUSH_DATA (push, screen->text->offset);
/* textures */
BEGIN_NVC0(push, NVC0_CP(TIC_ADDRESS_HIGH), 3);
PUSH_DATAh(push, screen->txc->offset);
PUSH_DATA (push, screen->txc->offset);
PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
/* samplers */
BEGIN_NVC0(push, NVC0_CP(TSC_ADDRESS_HIGH), 3);
PUSH_DATAh(push, screen->txc->offset + 65536);
PUSH_DATA (push, screen->txc->offset + 65536);
PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
/* MS sample coordinate offsets */
BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3);
PUSH_DATA (push, NVC0_CB_AUX_SIZE);
PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5));
PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5));
BEGIN_1IC0(push, NVC0_CP(CB_POS), 1 + 2 * 8);
PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
PUSH_DATA (push, 0); /* 0 */
PUSH_DATA (push, 0);
PUSH_DATA (push, 1); /* 1 */
PUSH_DATA (push, 0);
PUSH_DATA (push, 0); /* 2 */
PUSH_DATA (push, 1);
PUSH_DATA (push, 1); /* 3 */
PUSH_DATA (push, 1);
PUSH_DATA (push, 2); /* 4 */
PUSH_DATA (push, 0);
PUSH_DATA (push, 3); /* 5 */
PUSH_DATA (push, 0);
PUSH_DATA (push, 2); /* 6 */
PUSH_DATA (push, 1);
PUSH_DATA (push, 3); /* 7 */
PUSH_DATA (push, 1);
return 0;
}
static void
nouveau_accel_init(struct nouveau_drm *drm)
{
struct nouveau_device *device = nv_device(drm->device);
struct nouveau_object *object;
u32 arg0, arg1;
int ret;
if (nouveau_noaccel || !nouveau_fifo(device) /*XXX*/)
return;
/* initialise synchronisation routines */
if (device->card_type < NV_10) ret = nv04_fence_create(drm);
else if (device->card_type < NV_11 ||
device->chipset < 0x17) ret = nv10_fence_create(drm);
else if (device->card_type < NV_50) ret = nv17_fence_create(drm);
else if (device->chipset < 0x84) ret = nv50_fence_create(drm);
else if (device->card_type < NV_C0) ret = nv84_fence_create(drm);
else ret = nvc0_fence_create(drm);
if (ret) {
NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
nouveau_accel_fini(drm);
return;
}
if (device->card_type >= NV_E0) {
ret = nouveau_channel_new(drm, &drm->client, NVDRM_DEVICE,
NVDRM_CHAN + 1,
NVE0_CHANNEL_IND_ENGINE_CE0 |
NVE0_CHANNEL_IND_ENGINE_CE1, 0,
&drm->cechan);
if (ret)
NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
arg0 = NVE0_CHANNEL_IND_ENGINE_GR;
arg1 = 1;
} else
if (device->chipset >= 0xa3 &&
device->chipset != 0xaa &&
device->chipset != 0xac) {
ret = nouveau_channel_new(drm, &drm->client, NVDRM_DEVICE,
NVDRM_CHAN + 1, NvDmaFB, NvDmaTT,
&drm->cechan);
if (ret)
NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
arg0 = NvDmaFB;
arg1 = NvDmaTT;
} else {
arg0 = NvDmaFB;
arg1 = NvDmaTT;
}
ret = nouveau_channel_new(drm, &drm->client, NVDRM_DEVICE, NVDRM_CHAN,
arg0, arg1, &drm->channel);
if (ret) {
NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
nouveau_accel_fini(drm);
return;
}
ret = nouveau_object_new(nv_object(drm), NVDRM_CHAN, NVDRM_NVSW,
nouveau_abi16_swclass(drm), NULL, 0, &object);
if (ret == 0) {
struct nouveau_software_chan *swch = (void *)object->parent;
ret = RING_SPACE(drm->channel, 2);
if (ret == 0) {
if (device->card_type < NV_C0) {
BEGIN_NV04(drm->channel, NvSubSw, 0, 1);
OUT_RING (drm->channel, NVDRM_NVSW);
} else
if (device->card_type < NV_E0) {
BEGIN_NVC0(drm->channel, FermiSw, 0, 1);
OUT_RING (drm->channel, 0x001f0000);
}
}
swch = (void *)object->parent;
swch->flip = nouveau_flip_complete;
swch->flip_data = drm->channel;
}
if (ret) {
NV_ERROR(drm, "failed to allocate software object, %d\n", ret);
nouveau_accel_fini(drm);
return;
}
if (device->card_type < NV_C0) {
ret = nouveau_gpuobj_new(drm->device, NULL, 32, 0, 0,
&drm->notify);
if (ret) {
NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
nouveau_accel_fini(drm);
return;
}
ret = nouveau_object_new(nv_object(drm),
drm->channel->handle, NvNotify0,
0x003d, &(struct nv_dma_class) {
.flags = NV_DMA_TARGET_VRAM |
NV_DMA_ACCESS_RDWR,
.start = drm->notify->addr,
.limit = drm->notify->addr + 31
}, sizeof(struct nv_dma_class),
static int
firmware_present(struct pipe_screen *pscreen, enum pipe_video_profile profile)
{
struct nouveau_screen *screen = nouveau_screen(pscreen);
int chipset = screen->device->chipset;
int vp3 = chipset < 0xa3 || chipset == 0xaa || chipset == 0xac;
int vp5 = chipset >= 0xd0;
int ret;
/* For all chipsets, try to create a BSP objects. Assume that if firmware
* is present for it, firmware is also present for VP/PPP */
if (!(screen->firmware_info.profiles_checked & 1)) {
struct nouveau_object *channel = NULL, *bsp = NULL;
struct nv04_fifo nv04_data = {.vram = 0xbeef0201, .gart = 0xbeef0202};
struct nvc0_fifo nvc0_args = {};
struct nve0_fifo nve0_args = {.engine = NVE0_FIFO_ENGINE_BSP};
void *data = NULL;
int size, oclass;
if (chipset < 0xc0)
oclass = 0x85b1;
else if (vp5)
oclass = 0x95b1;
else
oclass = 0x90b1;
if (chipset < 0xc0) {
data = &nv04_data;
size = sizeof(nv04_data);
} else if (chipset < 0xe0) {
data = &nvc0_args;
size = sizeof(nvc0_args);
} else {
data = &nve0_args;
size = sizeof(nve0_args);
}
/* kepler must have its own channel, so just do this for everyone */
nouveau_object_new(&screen->device->object, 0,
NOUVEAU_FIFO_CHANNEL_CLASS,
data, size, &channel);
if (channel) {
nouveau_object_new(channel, 0, oclass, NULL, 0, &bsp);
if (bsp)
screen->firmware_info.profiles_present |= 1;
nouveau_object_del(&bsp);
nouveau_object_del(&channel);
}
screen->firmware_info.profiles_checked |= 1;
}
if (!(screen->firmware_info.profiles_present & 1))
return 0;
/* For vp3/vp4 chipsets, make sure that the relevant firmware is present */
if (!vp5 && !(screen->firmware_info.profiles_checked & (1 << profile))) {
char path[PATH_MAX];
struct stat s;
if (vp3)
vp3_getpath(profile, path);
else
vp4_getpath(profile, path);
ret = stat(path, &s);
if (!ret && s.st_size > 1000)
screen->firmware_info.profiles_present |= (1 << profile);
screen->firmware_info.profiles_checked |= (1 << profile);
}
return vp5 || (screen->firmware_info.profiles_present & (1 << profile));
}
int
nouveau_vp3_screen_get_video_param(struct pipe_screen *pscreen,
enum pipe_video_profile profile,
enum pipe_video_entrypoint entrypoint,
enum pipe_video_cap param)
{
int chipset = nouveau_screen(pscreen)->device->chipset;
int vp3 = chipset < 0xa3 || chipset == 0xaa || chipset == 0xac;
int vp5 = chipset >= 0xd0;
enum pipe_video_format codec = u_reduce_video_profile(profile);
switch (param) {
case PIPE_VIDEO_CAP_SUPPORTED:
/* VP3 does not support MPEG4, VP4+ do. */
return entrypoint == PIPE_VIDEO_ENTRYPOINT_BITSTREAM &&
profile >= PIPE_VIDEO_PROFILE_MPEG1 &&
(!vp3 || codec != PIPE_VIDEO_FORMAT_MPEG4) &&
firmware_present(pscreen, profile);
case PIPE_VIDEO_CAP_NPOT_TEXTURES:
return 1;
case PIPE_VIDEO_CAP_MAX_WIDTH:
case PIPE_VIDEO_CAP_MAX_HEIGHT:
return vp5 ? 4096 : 2048;
case PIPE_VIDEO_CAP_PREFERED_FORMAT:
return PIPE_FORMAT_NV12;
case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
return true;
case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
return false;
case PIPE_VIDEO_CAP_MAX_LEVEL:
switch (profile) {
case PIPE_VIDEO_PROFILE_MPEG1:
return 0;
case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
return 3;
case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
return 3;
case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
return 5;
case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
return 1;
case PIPE_VIDEO_PROFILE_VC1_MAIN:
return 2;
case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
return 4;
case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
return 41;
default:
debug_printf("unknown video profile: %d\n", profile);
return 0;
}
default:
debug_printf("unknown video param: %d\n", param);
return 0;
}
}
struct pipe_video_decoder *
nvc0_create_decoder(struct pipe_context *context,
enum pipe_video_profile profile,
enum pipe_video_entrypoint entrypoint,
enum pipe_video_chroma_format chroma_format,
unsigned width, unsigned height, unsigned max_references,
bool chunked_decode)
{
struct nouveau_screen *screen = &((struct nvc0_context *)context)->screen->base;
struct nvc0_decoder *dec;
struct nouveau_pushbuf **push;
union nouveau_bo_config cfg;
bool kepler = screen->device->chipset >= 0xe0;
cfg.nvc0.tile_mode = 0x10;
cfg.nvc0.memtype = 0xfe;
int ret, i;
uint32_t codec = 1, ppp_codec = 3;
uint32_t timeout;
u32 tmp_size = 0;
if (getenv("XVMC_VL"))
return vl_create_decoder(context, profile, entrypoint,
chroma_format, width, height,
max_references, chunked_decode);
if (entrypoint != PIPE_VIDEO_ENTRYPOINT_BITSTREAM) {
debug_printf("%x\n", entrypoint);
return NULL;
}
dec = CALLOC_STRUCT(nvc0_decoder);
if (!dec)
return NULL;
dec->client = screen->client;
if (!kepler) {
dec->bsp_idx = 5;
dec->vp_idx = 6;
dec->ppp_idx = 7;
} else {
dec->bsp_idx = 2;
dec->vp_idx = 2;
dec->ppp_idx = 2;
}
for (i = 0; i < 3; ++i)
if (i && !kepler) {
dec->channel[i] = dec->channel[0];
dec->pushbuf[i] = dec->pushbuf[0];
} else {
void *data;
u32 size;
struct nvc0_fifo nvc0_args = {};
struct nve0_fifo nve0_args = {};
if (!kepler) {
size = sizeof(nvc0_args);
data = &nvc0_args;
} else {
unsigned engine[] = {
NVE0_FIFO_ENGINE_BSP,
NVE0_FIFO_ENGINE_VP,
NVE0_FIFO_ENGINE_PPP
};
nve0_args.engine = engine[i];
size = sizeof(nve0_args);
data = &nve0_args;
}
ret = nouveau_object_new(&screen->device->object, 0,
NOUVEAU_FIFO_CHANNEL_CLASS,
data, size, &dec->channel[i]);
if (!ret)
ret = nouveau_pushbuf_new(screen->client, dec->channel[i], 4,
32 * 1024, true, &dec->pushbuf[i]);
if (ret)
break;
}
push = dec->pushbuf;
if (!kepler) {
if (!ret)
ret = nouveau_object_new(dec->channel[0], 0x390b1, 0x90b1, NULL, 0, &dec->bsp);
if (!ret)
ret = nouveau_object_new(dec->channel[1], 0x190b2, 0x90b2, NULL, 0, &dec->vp);
if (!ret)
ret = nouveau_object_new(dec->channel[2], 0x290b3, 0x90b3, NULL, 0, &dec->ppp);
} else {
if (!ret)
ret = nouveau_object_new(dec->channel[0], 0x95b1, 0x95b1, NULL, 0, &dec->bsp);
if (!ret)
ret = nouveau_object_new(dec->channel[1], 0x95b2, 0x95b2, NULL, 0, &dec->vp);
if (!ret)
ret = nouveau_object_new(dec->channel[2], 0x90b3, 0x90b3, NULL, 0, &dec->ppp);
}
if (ret)
goto fail;
BEGIN_NVC0(push[0], SUBC_BSP(NV01_SUBCHAN_OBJECT), 1);
PUSH_DATA (push[0], dec->bsp->handle);
BEGIN_NVC0(push[1], SUBC_VP(NV01_SUBCHAN_OBJECT), 1);
PUSH_DATA (push[1], dec->vp->handle);
BEGIN_NVC0(push[2], SUBC_PPP(NV01_SUBCHAN_OBJECT), 1);
PUSH_DATA (push[2], dec->ppp->handle);
dec->base.context = context;
dec->base.profile = profile;
dec->base.entrypoint = entrypoint;
dec->base.chroma_format = chroma_format;
dec->base.width = width;
dec->base.height = height;
dec->base.max_references = max_references;
dec->base.destroy = nvc0_decoder_destroy;
dec->base.flush = nvc0_decoder_flush;
dec->base.decode_bitstream = nvc0_decoder_decode_bitstream;
dec->base.begin_frame = nvc0_decoder_begin_frame;
dec->base.end_frame = nvc0_decoder_end_frame;
for (i = 0; i < NVC0_VIDEO_QDEPTH && !ret; ++i)
ret = nouveau_bo_new(screen->device, NOUVEAU_BO_VRAM,
0, 1 << 20, &cfg, &dec->bsp_bo[i]);
if (!ret)
ret = nouveau_bo_new(screen->device, NOUVEAU_BO_VRAM,
0x100, 4 << 20, &cfg, &dec->inter_bo[0]);
if (!ret) {
if (!kepler)
nouveau_bo_ref(dec->inter_bo[0], &dec->inter_bo[1]);
else
ret = nouveau_bo_new(screen->device, NOUVEAU_BO_VRAM,
0x100, dec->inter_bo[0]->size, &cfg,
&dec->inter_bo[1]);
}
if (ret)
goto fail;
switch (u_reduce_video_profile(profile)) {
case PIPE_VIDEO_CODEC_MPEG12: {
codec = 1;
assert(max_references <= 2);
break;
}
case PIPE_VIDEO_CODEC_MPEG4: {
codec = 4;
tmp_size = mb(height)*16 * mb(width)*16;
assert(max_references <= 2);
break;
}
case PIPE_VIDEO_CODEC_VC1: {
ppp_codec = codec = 2;
tmp_size = mb(height)*16 * mb(width)*16;
assert(max_references <= 2);
break;
}
case PIPE_VIDEO_CODEC_MPEG4_AVC: {
codec = 3;
dec->tmp_stride = 16 * mb_half(width) * nvc0_video_align(height) * 3 / 2;
tmp_size = dec->tmp_stride * (max_references + 1);
assert(max_references <= 16);
break;
}
default:
fprintf(stderr, "invalid codec\n");
goto fail;
}
if (screen->device->chipset < 0xd0) {
int fd;
char path[PATH_MAX];
ssize_t r;
uint32_t *end, endval;
ret = nouveau_bo_new(screen->device, NOUVEAU_BO_VRAM, 0,
0x4000, &cfg, &dec->fw_bo);
if (!ret)
ret = nouveau_bo_map(dec->fw_bo, NOUVEAU_BO_WR, dec->client);
if (ret)
goto fail;
nvc0_video_getpath(profile, path);
fd = open(path, O_RDONLY | O_CLOEXEC);
if (fd < 0) {
fprintf(stderr, "opening firmware file %s failed: %m\n", path);
goto fw_fail;
}
r = read(fd, dec->fw_bo->map, 0x4000);
close(fd);
if (r < 0) {
fprintf(stderr, "reading firmware file %s failed: %m\n", path);
goto fw_fail;
}
if (r == 0x4000) {
fprintf(stderr, "firmware file %s too large!\n", path);
goto fw_fail;
}
if (r & 0xff) {
fprintf(stderr, "firmware file %s wrong size!\n", path);
goto fw_fail;
}
end = dec->fw_bo->map + r - 4;
endval = *end;
while (endval == *end)
end--;
r = (intptr_t)end - (intptr_t)dec->fw_bo->map + 4;
switch (u_reduce_video_profile(profile)) {
case PIPE_VIDEO_CODEC_MPEG12: {
assert((r & 0xff) == 0xe0);
dec->fw_sizes = (0x2e0<<16) | (r - 0x2e0);
break;
}
case PIPE_VIDEO_CODEC_MPEG4: {
assert((r & 0xff) == 0xe0);
dec->fw_sizes = (0x2e0<<16) | (r - 0x2e0);
break;
}
case PIPE_VIDEO_CODEC_VC1: {
assert((r & 0xff) == 0xac);
dec->fw_sizes = (0x3ac<<16) | (r - 0x3ac);
break;
}
case PIPE_VIDEO_CODEC_MPEG4_AVC: {
assert((r & 0xff) == 0x70);
dec->fw_sizes = (0x370<<16) | (r - 0x370);
break;
}
default:
goto fw_fail;
}
munmap(dec->fw_bo->map, dec->fw_bo->size);
dec->fw_bo->map = NULL;
}
if (codec != 3) {
ret = nouveau_bo_new(screen->device, NOUVEAU_BO_VRAM, 0,
0x400, &cfg, &dec->bitplane_bo);
if (ret)
goto fail;
}
dec->ref_stride = mb(width)*16 * (mb_half(height)*32 + nvc0_video_align(height)/2);
ret = nouveau_bo_new(screen->device, NOUVEAU_BO_VRAM, 0,
dec->ref_stride * (max_references+2) + tmp_size,
&cfg, &dec->ref_bo);
if (ret)
goto fail;
timeout = 0;
BEGIN_NVC0(push[0], SUBC_BSP(0x200), 2);
PUSH_DATA (push[0], codec);
PUSH_DATA (push[0], timeout);
BEGIN_NVC0(push[1], SUBC_VP(0x200), 2);
PUSH_DATA (push[1], codec);
PUSH_DATA (push[1], timeout);
BEGIN_NVC0(push[2], SUBC_PPP(0x200), 2);
PUSH_DATA (push[2], ppp_codec);
PUSH_DATA (push[2], timeout);
++dec->fence_seq;
#if NVC0_DEBUG_FENCE
ret = nouveau_bo_new(screen->device, NOUVEAU_BO_GART|NOUVEAU_BO_MAP,
0, 0x1000, NULL, &dec->fence_bo);
if (ret)
goto fail;
nouveau_bo_map(dec->fence_bo, NOUVEAU_BO_RDWR, screen->client);
dec->fence_map = dec->fence_bo->map;
dec->fence_map[0] = dec->fence_map[4] = dec->fence_map[8] = 0;
dec->comm = (struct comm *)(dec->fence_map + (COMM_OFFSET/sizeof(*dec->fence_map)));
/* So lets test if the fence is working? */
nouveau_pushbuf_space(push[0], 6, 1, 0);
PUSH_REFN (push[0], dec->fence_bo, NOUVEAU_BO_GART|NOUVEAU_BO_RDWR);
BEGIN_NVC0(push[0], SUBC_BSP(0x240), 3);
PUSH_DATAh(push[0], dec->fence_bo->offset);
PUSH_DATA (push[0], dec->fence_bo->offset);
PUSH_DATA (push[0], dec->fence_seq);
BEGIN_NVC0(push[0], SUBC_BSP(0x304), 1);
PUSH_DATA (push[0], 0);
PUSH_KICK (push[0]);
nouveau_pushbuf_space(push[1], 6, 1, 0);
PUSH_REFN (push[1], dec->fence_bo, NOUVEAU_BO_GART|NOUVEAU_BO_RDWR);
BEGIN_NVC0(push[1], SUBC_VP(0x240), 3);
PUSH_DATAh(push[1], (dec->fence_bo->offset + 0x10));
PUSH_DATA (push[1], (dec->fence_bo->offset + 0x10));
PUSH_DATA (push[1], dec->fence_seq);
BEGIN_NVC0(push[1], SUBC_VP(0x304), 1);
PUSH_DATA (push[1], 0);
PUSH_KICK (push[1]);
nouveau_pushbuf_space(push[2], 6, 1, 0);
PUSH_REFN (push[2], dec->fence_bo, NOUVEAU_BO_GART|NOUVEAU_BO_RDWR);
BEGIN_NVC0(push[2], SUBC_PPP(0x240), 3);
PUSH_DATAh(push[2], (dec->fence_bo->offset + 0x20));
PUSH_DATA (push[2], (dec->fence_bo->offset + 0x20));
PUSH_DATA (push[2], dec->fence_seq);
BEGIN_NVC0(push[2], SUBC_PPP(0x304), 1);
PUSH_DATA (push[2], 0);
PUSH_KICK (push[2]);
usleep(100);
while (dec->fence_seq > dec->fence_map[0] ||
dec->fence_seq > dec->fence_map[4] ||
dec->fence_seq > dec->fence_map[8]) {
debug_printf("%u: %u %u %u\n", dec->fence_seq, dec->fence_map[0], dec->fence_map[4], dec->fence_map[8]);
usleep(100);
}
debug_printf("%u: %u %u %u\n", dec->fence_seq, dec->fence_map[0], dec->fence_map[4], dec->fence_map[8]);
#endif
return &dec->base;
fw_fail:
debug_printf("Cannot create decoder without firmware..\n");
nvc0_decoder_destroy(&dec->base);
return NULL;
fail:
debug_printf("Creation failed: %s (%i)\n", strerror(-ret), ret);
nvc0_decoder_destroy(&dec->base);
return NULL;
}
static struct gl_context *
nv20_context_create(struct nouveau_screen *screen, gl_api api,
const struct gl_config *visual,
struct gl_context *share_ctx)
{
struct nouveau_context *nctx;
struct gl_context *ctx;
unsigned kelvin_class;
int ret;
nctx = CALLOC_STRUCT(nouveau_context);
if (!nctx)
return NULL;
ctx = &nctx->base;
if (!nouveau_context_init(ctx, api, screen, visual, share_ctx))
goto fail;
ctx->Extensions.ARB_texture_env_crossbar = true;
ctx->Extensions.ARB_texture_env_combine = true;
ctx->Extensions.ARB_texture_env_dot3 = true;
ctx->Extensions.EXT_texture_env_dot3 = true;
ctx->Extensions.NV_fog_distance = true;
ctx->Extensions.NV_texture_rectangle = true;
ctx->Extensions.EXT_texture_compression_s3tc = true;
ctx->Extensions.ANGLE_texture_compression_dxt = true;
/* GL constants. */
ctx->Const.MaxTextureCoordUnits = NV20_TEXTURE_UNITS;
ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits = NV20_TEXTURE_UNITS;
ctx->Const.MaxTextureUnits = NV20_TEXTURE_UNITS;
ctx->Const.MaxTextureMaxAnisotropy = 8;
ctx->Const.MaxTextureLodBias = 15;
ctx->Driver.Clear = nv20_clear;
/* 2D engine. */
ret = nv04_surface_init(ctx);
if (!ret)
goto fail;
/* 3D engine. */
if (context_chipset(ctx) >= 0x25)
kelvin_class = NV25_3D_CLASS;
else
kelvin_class = NV20_3D_CLASS;
ret = nouveau_object_new(context_chan(ctx), 0xbeef0001, kelvin_class,
NULL, 0, &nctx->hw.eng3d);
if (ret)
goto fail;
nv20_hwctx_init(ctx);
nv20_vbo_init(ctx);
nv20_swtnl_init(ctx);
return ctx;
fail:
nv20_context_destroy(ctx);
return NULL;
}
static struct gl_context *
nv04_context_create(struct nouveau_screen *screen, const struct gl_config *visual,
struct gl_context *share_ctx)
{
struct nv04_context *nctx;
struct nouveau_hw_state *hw;
struct gl_context *ctx;
int ret;
nctx = CALLOC_STRUCT(nv04_context);
if (!nctx)
return NULL;
ctx = &nctx->base.base;
hw = &nctx->base.hw;
if (!nouveau_context_init(ctx, screen, visual, share_ctx))
goto fail;
/* GL constants. */
ctx->Const.MaxTextureLevels = 11;
ctx->Const.MaxTextureCoordUnits = NV04_TEXTURE_UNITS;
ctx->Const.MaxTextureImageUnits = NV04_TEXTURE_UNITS;
ctx->Const.MaxTextureUnits = NV04_TEXTURE_UNITS;
ctx->Const.MaxTextureMaxAnisotropy = 2;
ctx->Const.MaxTextureLodBias = 15;
/* 2D engine. */
ret = nv04_surface_init(ctx);
if (!ret)
goto fail;
/* 3D engine. */
ret = nouveau_object_new(context_chan(ctx), 0xbeef0001,
NV04_TEXTURED_TRIANGLE_CLASS, NULL, 0,
&hw->eng3d);
if (ret)
goto fail;
ret = nouveau_object_new(context_chan(ctx), 0xbeef0002,
NV04_MULTITEX_TRIANGLE_CLASS, NULL, 0,
&hw->eng3dm);
if (ret)
goto fail;
ret = nouveau_object_new(context_chan(ctx), 0xbeef0003,
NV04_SURFACE_3D_CLASS, NULL, 0,
&hw->surf3d);
if (ret)
goto fail;
init_dummy_texture(ctx);
nv04_hwctx_init(ctx);
nv04_render_init(ctx);
return ctx;
fail:
nv04_context_destroy(ctx);
return NULL;
}
struct pipe_screen *
nv30_screen_create(struct nouveau_device *dev)
{
struct nv30_screen *screen = CALLOC_STRUCT(nv30_screen);
struct pipe_screen *pscreen;
struct nouveau_pushbuf *push;
struct nv04_fifo *fifo;
unsigned oclass = 0;
int ret, i;
if (!screen)
return NULL;
switch (dev->chipset & 0xf0) {
case 0x30:
if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
oclass = NV30_3D_CLASS;
else
if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
oclass = NV34_3D_CLASS;
else
if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
oclass = NV35_3D_CLASS;
break;
case 0x40:
if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
oclass = NV40_3D_CLASS;
else
if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
oclass = NV44_3D_CLASS;
break;
case 0x60:
if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
oclass = NV44_3D_CLASS;
break;
default:
break;
}
if (!oclass) {
NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
FREE(screen);
return NULL;
}
/*
* Some modern apps try to use msaa without keeping in mind the
* restrictions on videomem of older cards. Resulting in dmesg saying:
* [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
* [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
* [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
*
* Because we are running out of video memory, after which the program
* using the msaa visual freezes, and eventually the entire system freezes.
*
* To work around this we do not allow msaa visauls by default and allow
* the user to override this via NV30_MAX_MSAA.
*/
screen->max_sample_count = debug_get_num_option("NV30_MAX_MSAA", 0);
if (screen->max_sample_count > 4)
screen->max_sample_count = 4;
pscreen = &screen->base.base;
pscreen->destroy = nv30_screen_destroy;
pscreen->get_param = nv30_screen_get_param;
pscreen->get_paramf = nv30_screen_get_paramf;
pscreen->get_shader_param = nv30_screen_get_shader_param;
pscreen->context_create = nv30_context_create;
pscreen->is_format_supported = nv30_screen_is_format_supported;
nv30_resource_screen_init(pscreen);
nouveau_screen_init_vdec(&screen->base);
screen->base.fence.emit = nv30_screen_fence_emit;
screen->base.fence.update = nv30_screen_fence_update;
ret = nouveau_screen_init(&screen->base, dev);
if (ret)
FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
if (oclass == NV40_3D_CLASS) {
screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
}
fifo = screen->base.channel->data;
push = screen->base.pushbuf;
push->rsvd_kick = 16;
ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
NULL, 0, &screen->null);
if (ret)
FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
/* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
* this means that the address pointed at by the DMA object must
* be 4KiB aligned, which means this object needs to be the first
* one allocated on the channel.
*/
ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
.length = 32 }, sizeof(struct nv04_notify),
struct pipe_video_codec *
nvc0_create_decoder(struct pipe_context *context,
const struct pipe_video_codec *templ)
{
struct nouveau_screen *screen = &((struct nvc0_context *)context)->screen->base;
struct nouveau_vp3_decoder *dec;
struct nouveau_pushbuf **push;
union nouveau_bo_config cfg;
bool kepler = screen->device->chipset >= 0xe0;
cfg.nvc0.tile_mode = 0x10;
cfg.nvc0.memtype = 0xfe;
int ret, i;
uint32_t codec = 1, ppp_codec = 3;
uint32_t timeout;
u32 tmp_size = 0;
if (getenv("XVMC_VL"))
return vl_create_decoder(context, templ);
if (templ->entrypoint != PIPE_VIDEO_ENTRYPOINT_BITSTREAM) {
debug_printf("%x\n", templ->entrypoint);
return NULL;
}
dec = CALLOC_STRUCT(nouveau_vp3_decoder);
if (!dec)
return NULL;
dec->client = screen->client;
dec->base = *templ;
nouveau_vp3_decoder_init_common(&dec->base);
if (!kepler) {
dec->bsp_idx = 5;
dec->vp_idx = 6;
dec->ppp_idx = 7;
} else {
dec->bsp_idx = 2;
dec->vp_idx = 2;
dec->ppp_idx = 2;
}
for (i = 0; i < 3; ++i)
if (i && !kepler) {
dec->channel[i] = dec->channel[0];
dec->pushbuf[i] = dec->pushbuf[0];
} else {
void *data;
u32 size;
struct nvc0_fifo nvc0_args = {};
struct nve0_fifo nve0_args = {};
if (!kepler) {
size = sizeof(nvc0_args);
data = &nvc0_args;
} else {
unsigned engine[] = {
NVE0_FIFO_ENGINE_BSP,
NVE0_FIFO_ENGINE_VP,
NVE0_FIFO_ENGINE_PPP
};
nve0_args.engine = engine[i];
size = sizeof(nve0_args);
data = &nve0_args;
}
ret = nouveau_object_new(&screen->device->object, 0,
NOUVEAU_FIFO_CHANNEL_CLASS,
data, size, &dec->channel[i]);
if (!ret)
ret = nouveau_pushbuf_new(screen->client, dec->channel[i], 4,
32 * 1024, true, &dec->pushbuf[i]);
if (ret)
break;
}
push = dec->pushbuf;
if (!kepler) {
if (!ret)
ret = nouveau_object_new(dec->channel[0], 0x390b1, 0x90b1, NULL, 0, &dec->bsp);
if (!ret)
ret = nouveau_object_new(dec->channel[1], 0x190b2, 0x90b2, NULL, 0, &dec->vp);
if (!ret)
ret = nouveau_object_new(dec->channel[2], 0x290b3, 0x90b3, NULL, 0, &dec->ppp);
} else {
if (!ret)
ret = nouveau_object_new(dec->channel[0], 0x95b1, 0x95b1, NULL, 0, &dec->bsp);
if (!ret)
ret = nouveau_object_new(dec->channel[1], 0x95b2, 0x95b2, NULL, 0, &dec->vp);
if (!ret)
ret = nouveau_object_new(dec->channel[2], 0x90b3, 0x90b3, NULL, 0, &dec->ppp);
}
if (ret)
goto fail;
BEGIN_NVC0(push[0], SUBC_BSP(NV01_SUBCHAN_OBJECT), 1);
PUSH_DATA (push[0], dec->bsp->handle);
BEGIN_NVC0(push[1], SUBC_VP(NV01_SUBCHAN_OBJECT), 1);
PUSH_DATA (push[1], dec->vp->handle);
BEGIN_NVC0(push[2], SUBC_PPP(NV01_SUBCHAN_OBJECT), 1);
PUSH_DATA (push[2], dec->ppp->handle);
dec->base.context = context;
dec->base.decode_bitstream = nvc0_decoder_decode_bitstream;
for (i = 0; i < NOUVEAU_VP3_VIDEO_QDEPTH && !ret; ++i)
ret = nouveau_bo_new(screen->device, NOUVEAU_BO_VRAM,
0, 1 << 20, &cfg, &dec->bsp_bo[i]);
if (!ret)
ret = nouveau_bo_new(screen->device, NOUVEAU_BO_VRAM,
0x100, 4 << 20, &cfg, &dec->inter_bo[0]);
if (!ret) {
ret = nouveau_bo_new(screen->device, NOUVEAU_BO_VRAM,
0x100, dec->inter_bo[0]->size, &cfg,
&dec->inter_bo[1]);
}
if (ret)
goto fail;
switch (u_reduce_video_profile(templ->profile)) {
case PIPE_VIDEO_FORMAT_MPEG12: {
codec = 1;
assert(templ->max_references <= 2);
break;
}
case PIPE_VIDEO_FORMAT_MPEG4: {
codec = 4;
tmp_size = mb(templ->height)*16 * mb(templ->width)*16;
assert(templ->max_references <= 2);
break;
}
case PIPE_VIDEO_FORMAT_VC1: {
ppp_codec = codec = 2;
tmp_size = mb(templ->height)*16 * mb(templ->width)*16;
assert(templ->max_references <= 2);
break;
}
case PIPE_VIDEO_FORMAT_MPEG4_AVC: {
codec = 3;
dec->tmp_stride = 16 * mb_half(templ->width) * nouveau_vp3_video_align(templ->height) * 3 / 2;
tmp_size = dec->tmp_stride * (templ->max_references + 1);
assert(templ->max_references <= 16);
break;
}
default:
fprintf(stderr, "invalid codec\n");
goto fail;
}
if (screen->device->chipset < 0xd0) {
ret = nouveau_bo_new(screen->device, NOUVEAU_BO_VRAM, 0,
0x4000, &cfg, &dec->fw_bo);
if (ret)
goto fail;
ret = nouveau_vp3_load_firmware(dec, templ->profile, screen->device->chipset);
if (ret)
goto fw_fail;
}
if (codec != 3) {
ret = nouveau_bo_new(screen->device, NOUVEAU_BO_VRAM, 0,
0x400, &cfg, &dec->bitplane_bo);
if (ret)
goto fail;
}
dec->ref_stride = mb(templ->width)*16 * (mb_half(templ->height)*32 + nouveau_vp3_video_align(templ->height)/2);
ret = nouveau_bo_new(screen->device, NOUVEAU_BO_VRAM, 0,
dec->ref_stride * (templ->max_references+2) + tmp_size,
&cfg, &dec->ref_bo);
if (ret)
goto fail;
timeout = 0;
BEGIN_NVC0(push[0], SUBC_BSP(0x200), 2);
PUSH_DATA (push[0], codec);
PUSH_DATA (push[0], timeout);
BEGIN_NVC0(push[1], SUBC_VP(0x200), 2);
PUSH_DATA (push[1], codec);
PUSH_DATA (push[1], timeout);
BEGIN_NVC0(push[2], SUBC_PPP(0x200), 2);
PUSH_DATA (push[2], ppp_codec);
PUSH_DATA (push[2], timeout);
++dec->fence_seq;
#if NOUVEAU_VP3_DEBUG_FENCE
ret = nouveau_bo_new(screen->device, NOUVEAU_BO_GART|NOUVEAU_BO_MAP,
0, 0x1000, NULL, &dec->fence_bo);
if (ret)
goto fail;
nouveau_bo_map(dec->fence_bo, NOUVEAU_BO_RDWR, screen->client);
dec->fence_map = dec->fence_bo->map;
dec->fence_map[0] = dec->fence_map[4] = dec->fence_map[8] = 0;
dec->comm = (struct comm *)(dec->fence_map + (COMM_OFFSET/sizeof(*dec->fence_map)));
/* So lets test if the fence is working? */
nouveau_pushbuf_space(push[0], 6, 1, 0);
PUSH_REFN (push[0], dec->fence_bo, NOUVEAU_BO_GART|NOUVEAU_BO_RDWR);
BEGIN_NVC0(push[0], SUBC_BSP(0x240), 3);
PUSH_DATAh(push[0], dec->fence_bo->offset);
PUSH_DATA (push[0], dec->fence_bo->offset);
PUSH_DATA (push[0], dec->fence_seq);
BEGIN_NVC0(push[0], SUBC_BSP(0x304), 1);
PUSH_DATA (push[0], 0);
PUSH_KICK (push[0]);
nouveau_pushbuf_space(push[1], 6, 1, 0);
PUSH_REFN (push[1], dec->fence_bo, NOUVEAU_BO_GART|NOUVEAU_BO_RDWR);
BEGIN_NVC0(push[1], SUBC_VP(0x240), 3);
PUSH_DATAh(push[1], (dec->fence_bo->offset + 0x10));
PUSH_DATA (push[1], (dec->fence_bo->offset + 0x10));
PUSH_DATA (push[1], dec->fence_seq);
BEGIN_NVC0(push[1], SUBC_VP(0x304), 1);
PUSH_DATA (push[1], 0);
PUSH_KICK (push[1]);
nouveau_pushbuf_space(push[2], 6, 1, 0);
PUSH_REFN (push[2], dec->fence_bo, NOUVEAU_BO_GART|NOUVEAU_BO_RDWR);
BEGIN_NVC0(push[2], SUBC_PPP(0x240), 3);
PUSH_DATAh(push[2], (dec->fence_bo->offset + 0x20));
PUSH_DATA (push[2], (dec->fence_bo->offset + 0x20));
PUSH_DATA (push[2], dec->fence_seq);
BEGIN_NVC0(push[2], SUBC_PPP(0x304), 1);
PUSH_DATA (push[2], 0);
PUSH_KICK (push[2]);
usleep(100);
while (dec->fence_seq > dec->fence_map[0] ||
dec->fence_seq > dec->fence_map[4] ||
dec->fence_seq > dec->fence_map[8]) {
debug_printf("%u: %u %u %u\n", dec->fence_seq, dec->fence_map[0], dec->fence_map[4], dec->fence_map[8]);
usleep(100);
}
debug_printf("%u: %u %u %u\n", dec->fence_seq, dec->fence_map[0], dec->fence_map[4], dec->fence_map[8]);
#endif
return &dec->base;
fw_fail:
debug_printf("Cannot create decoder without firmware..\n");
dec->base.destroy(&dec->base);
return NULL;
fail:
debug_printf("Creation failed: %s (%i)\n", strerror(-ret), ret);
dec->base.destroy(&dec->base);
return NULL;
}
