u16
nvbios_timingEp(struct nouveau_bios *bios, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_ramcfg *p)
{
u16 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp;
p->timing_ver = *ver;
p->timing_hdr = *hdr;
switch (!!data * *ver) {
case 0x10:
p->timing_10_WR = nv_ro08(bios, data + 0x00);
p->timing_10_CL = nv_ro08(bios, data + 0x02);
p->timing_10_ODT = nv_ro08(bios, data + 0x0e) & 0x07;
p->timing_10_CWL = nv_ro08(bios, data + 0x13);
break;
case 0x20:
p->timing[0] = nv_ro32(bios, data + 0x00);
p->timing[1] = nv_ro32(bios, data + 0x04);
p->timing[2] = nv_ro32(bios, data + 0x08);
p->timing[3] = nv_ro32(bios, data + 0x0c);
p->timing[4] = nv_ro32(bios, data + 0x10);
p->timing[5] = nv_ro32(bios, data + 0x14);
p->timing[6] = nv_ro32(bios, data + 0x18);
p->timing[7] = nv_ro32(bios, data + 0x1c);
p->timing[8] = nv_ro32(bios, data + 0x20);
p->timing[9] = nv_ro32(bios, data + 0x24);
p->timing[10] = nv_ro32(bios, data + 0x28);
p->timing_20_2e_03 = (nv_ro08(bios, data + 0x2e) & 0x03) >> 0;
p->timing_20_2e_30 = (nv_ro08(bios, data + 0x2e) & 0x30) >> 4;
p->timing_20_2e_c0 = (nv_ro08(bios, data + 0x2e) & 0xc0) >> 6;
p->timing_20_2f_03 = (nv_ro08(bios, data + 0x2f) & 0x03) >> 0;
temp = nv_ro16(bios, data + 0x2c);
p->timing_20_2c_003f = (temp & 0x003f) >> 0;
p->timing_20_2c_1fc0 = (temp & 0x1fc0) >> 6;
p->timing_20_30_07 = (nv_ro08(bios, data + 0x30) & 0x07) >> 0;
p->timing_20_30_f8 = (nv_ro08(bios, data + 0x30) & 0xf8) >> 3;
temp = nv_ro16(bios, data + 0x31);
p->timing_20_31_0007 = (temp & 0x0007) >> 0;
p->timing_20_31_0078 = (temp & 0x0078) >> 3;
p->timing_20_31_0780 = (temp & 0x0780) >> 7;
p->timing_20_31_0800 = (temp & 0x0800) >> 11;
p->timing_20_31_7000 = (temp & 0x7000) >> 12;
p->timing_20_31_8000 = (temp & 0x8000) >> 15;
break;
default:
data = 0;
break;
}
return data;
}
static int
nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq)
{
struct nouveau_clock *clk = nouveau_clock(pfb);
struct nouveau_bios *bios = nouveau_bios(pfb);
struct nvc0_ram *ram = (void *)pfb->ram;
struct nvc0_ramfuc *fuc = &ram->fuc;
u8 ver, cnt, len, strap;
struct {
u32 data;
u8 size;
} rammap, ramcfg, timing;
int ref, div, out;
int from, mode;
int N1, M1, P;
int ret;
/* lookup memory config data relevant to the target frequency */
rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size,
&cnt, &ramcfg.size);
if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) {
nv_error(pfb, "invalid/missing rammap entry\n");
return -EINVAL;
}
/* locate specific data set for the attached memory */
strap = nvbios_ramcfg_index(nv_subdev(pfb));
if (strap >= cnt) {
nv_error(pfb, "invalid ramcfg strap\n");
return -EINVAL;
}
ramcfg.data = rammap.data + rammap.size + (strap * ramcfg.size);
if (!ramcfg.data || ver != 0x10 || ramcfg.size < 0x0e) {
nv_error(pfb, "invalid/missing ramcfg entry\n");
return -EINVAL;
}
/* lookup memory timings, if bios says they're present */
strap = nv_ro08(bios, ramcfg.data + 0x01);
if (strap != 0xff) {
timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size,
&cnt, &len);
if (!timing.data || ver != 0x10 || timing.size < 0x19) {
nv_error(pfb, "invalid/missing timing entry\n");
return -EINVAL;
}
} else {
timing.data = 0;
}
ret = ram_init(fuc, pfb);
if (ret)
return ret;
/* determine current mclk configuration */
from = !!(ram_rd32(fuc, 0x1373f0) & 0x00000002); /*XXX: ok? */
/* determine target mclk configuration */
if (!(ram_rd32(fuc, 0x137300) & 0x00000100))
ref = clk->read(clk, nv_clk_src_sppll0);
else
ref = clk->read(clk, nv_clk_src_sppll1);
div = max(min((ref * 2) / freq, (u32)65), (u32)2) - 2;
out = (ref * 2) / (div + 2);
mode = freq != out;
ram_mask(fuc, 0x137360, 0x00000002, 0x00000000);
if ((ram_rd32(fuc, 0x132000) & 0x00000002) || 0 /*XXX*/) {
ram_nuke(fuc, 0x132000);
ram_mask(fuc, 0x132000, 0x00000002, 0x00000002);
ram_mask(fuc, 0x132000, 0x00000002, 0x00000000);
}
if (mode == 1) {
ram_nuke(fuc, 0x10fe20);
ram_mask(fuc, 0x10fe20, 0x00000002, 0x00000002);
ram_mask(fuc, 0x10fe20, 0x00000002, 0x00000000);
}
// 0x00020034 // 0x0000000a
ram_wr32(fuc, 0x132100, 0x00000001);
if (mode == 1 && from == 0) {
/* calculate refpll */
ret = nva3_pll_calc(nv_subdev(pfb), &ram->refpll,
ram->mempll.refclk, &N1, NULL, &M1, &P);
if (ret <= 0) {
nv_error(pfb, "unable to calc refpll\n");
return ret ? ret : -ERANGE;
}
ram_wr32(fuc, 0x10fe20, 0x20010000);
ram_wr32(fuc, 0x137320, 0x00000003);
ram_wr32(fuc, 0x137330, 0x81200006);
ram_wr32(fuc, 0x10fe24, (P << 16) | (N1 << 8) | M1);
ram_wr32(fuc, 0x10fe20, 0x20010001);
ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
/* calculate mempll */
ret = nva3_pll_calc(nv_subdev(pfb), &ram->mempll, freq,
&N1, NULL, &M1, &P);
if (ret <= 0) {
nv_error(pfb, "unable to calc refpll\n");
return ret ? ret : -ERANGE;
}
ram_wr32(fuc, 0x10fe20, 0x20010005);
ram_wr32(fuc, 0x132004, (P << 16) | (N1 << 8) | M1);
ram_wr32(fuc, 0x132000, 0x18010101);
ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000);
} else
if (mode == 0) {
ram_wr32(fuc, 0x137300, 0x00000003);
}
if (from == 0) {
ram_nuke(fuc, 0x10fb04);
ram_mask(fuc, 0x10fb04, 0x0000ffff, 0x00000000);
ram_nuke(fuc, 0x10fb08);
ram_mask(fuc, 0x10fb08, 0x0000ffff, 0x00000000);
ram_wr32(fuc, 0x10f988, 0x2004ff00);
ram_wr32(fuc, 0x10f98c, 0x003fc040);
ram_wr32(fuc, 0x10f990, 0x20012001);
ram_wr32(fuc, 0x10f998, 0x00011a00);
ram_wr32(fuc, 0x13d8f4, 0x00000000);
} else {
ram_wr32(fuc, 0x10f988, 0x20010000);
ram_wr32(fuc, 0x10f98c, 0x00000000);
ram_wr32(fuc, 0x10f990, 0x20012001);
ram_wr32(fuc, 0x10f998, 0x00010a00);
}
if (from == 0) {
// 0x00020039 // 0x000000ba
}
// 0x0002003a // 0x00000002
ram_wr32(fuc, 0x100b0c, 0x00080012);
// 0x00030014 // 0x00000000 // 0x02b5f070
// 0x00030014 // 0x00010000 // 0x02b5f070
ram_wr32(fuc, 0x611200, 0x00003300);
// 0x00020034 // 0x0000000a
// 0x00030020 // 0x00000001 // 0x00000000
ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
ram_wr32(fuc, 0x10f210, 0x00000000);
ram_nsec(fuc, 1000);
if (mode == 0)
nvc0_ram_train(fuc, 0x000c1001);
ram_wr32(fuc, 0x10f310, 0x00000001);
ram_nsec(fuc, 1000);
ram_wr32(fuc, 0x10f090, 0x00000061);
ram_wr32(fuc, 0x10f090, 0xc000007f);
ram_nsec(fuc, 1000);
if (from == 0) {
ram_wr32(fuc, 0x10f824, 0x00007fd4);
} else {
ram_wr32(fuc, 0x1373ec, 0x00020404);
}
if (mode == 0) {
ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000);
ram_mask(fuc, 0x10f200, 0x00008000, 0x00008000);
ram_wr32(fuc, 0x10f830, 0x41500010);
ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
ram_mask(fuc, 0x132100, 0x00000100, 0x00000100);
ram_wr32(fuc, 0x10f050, 0xff000090);
ram_wr32(fuc, 0x1373ec, 0x00020f0f);
ram_wr32(fuc, 0x1373f0, 0x00000003);
ram_wr32(fuc, 0x137310, 0x81201616);
ram_wr32(fuc, 0x132100, 0x00000001);
// 0x00020039 // 0x000000ba
ram_wr32(fuc, 0x10f830, 0x00300017);
ram_wr32(fuc, 0x1373f0, 0x00000001);
ram_wr32(fuc, 0x10f824, 0x00007e77);
ram_wr32(fuc, 0x132000, 0x18030001);
ram_wr32(fuc, 0x10f090, 0x4000007e);
ram_nsec(fuc, 2000);
ram_wr32(fuc, 0x10f314, 0x00000001);
ram_wr32(fuc, 0x10f210, 0x80000000);
ram_wr32(fuc, 0x10f338, 0x00300220);
ram_wr32(fuc, 0x10f300, 0x0000011d);
ram_nsec(fuc, 1000);
ram_wr32(fuc, 0x10f290, 0x02060505);
ram_wr32(fuc, 0x10f294, 0x34208288);
ram_wr32(fuc, 0x10f298, 0x44050411);
ram_wr32(fuc, 0x10f29c, 0x0000114c);
ram_wr32(fuc, 0x10f2a0, 0x42e10069);
ram_wr32(fuc, 0x10f614, 0x40044f77);
ram_wr32(fuc, 0x10f610, 0x40044f77);
ram_wr32(fuc, 0x10f344, 0x00600009);
ram_nsec(fuc, 1000);
ram_wr32(fuc, 0x10f348, 0x00700008);
ram_wr32(fuc, 0x61c140, 0x19240000);
ram_wr32(fuc, 0x10f830, 0x00300017);
nvc0_ram_train(fuc, 0x80021001);
nvc0_ram_train(fuc, 0x80081001);
ram_wr32(fuc, 0x10f340, 0x00500004);
ram_nsec(fuc, 1000);
ram_wr32(fuc, 0x10f830, 0x01300017);
ram_wr32(fuc, 0x10f830, 0x00300017);
// 0x00030020 // 0x00000000 // 0x00000000
// 0x00020034 // 0x0000000b
ram_wr32(fuc, 0x100b0c, 0x00080028);
ram_wr32(fuc, 0x611200, 0x00003330);
} else {
ram_wr32(fuc, 0x10f800, 0x00001800);
ram_wr32(fuc, 0x13d8f4, 0x00000000);
ram_wr32(fuc, 0x1373ec, 0x00020404);
ram_wr32(fuc, 0x1373f0, 0x00000003);
ram_wr32(fuc, 0x10f830, 0x40700010);
ram_wr32(fuc, 0x10f830, 0x40500010);
ram_wr32(fuc, 0x13d8f4, 0x00000000);
ram_wr32(fuc, 0x1373f8, 0x00000000);
ram_wr32(fuc, 0x132100, 0x00000101);
ram_wr32(fuc, 0x137310, 0x89201616);
ram_wr32(fuc, 0x10f050, 0xff000090);
ram_wr32(fuc, 0x1373ec, 0x00030404);
ram_wr32(fuc, 0x1373f0, 0x00000002);
// 0x00020039 // 0x00000011
ram_wr32(fuc, 0x132100, 0x00000001);
ram_wr32(fuc, 0x1373f8, 0x00002000);
ram_nsec(fuc, 2000);
ram_wr32(fuc, 0x10f808, 0x7aaa0050);
ram_wr32(fuc, 0x10f830, 0x00500010);
ram_wr32(fuc, 0x10f200, 0x00ce1000);
ram_wr32(fuc, 0x10f090, 0x4000007e);
ram_nsec(fuc, 2000);
ram_wr32(fuc, 0x10f314, 0x00000001);
ram_wr32(fuc, 0x10f210, 0x80000000);
ram_wr32(fuc, 0x10f338, 0x00300200);
ram_wr32(fuc, 0x10f300, 0x0000084d);
ram_nsec(fuc, 1000);
ram_wr32(fuc, 0x10f290, 0x0b343825);
ram_wr32(fuc, 0x10f294, 0x3483028e);
ram_wr32(fuc, 0x10f298, 0x440c0600);
ram_wr32(fuc, 0x10f29c, 0x0000214c);
ram_wr32(fuc, 0x10f2a0, 0x42e20069);
ram_wr32(fuc, 0x10f200, 0x00ce0000);
ram_wr32(fuc, 0x10f614, 0x60044e77);
ram_wr32(fuc, 0x10f610, 0x60044e77);
ram_wr32(fuc, 0x10f340, 0x00500000);
ram_nsec(fuc, 1000);
ram_wr32(fuc, 0x10f344, 0x00600228);
ram_nsec(fuc, 1000);
ram_wr32(fuc, 0x10f348, 0x00700000);
ram_wr32(fuc, 0x13d8f4, 0x00000000);
ram_wr32(fuc, 0x61c140, 0x09a40000);
nvc0_ram_train(fuc, 0x800e1008);
ram_nsec(fuc, 1000);
ram_wr32(fuc, 0x10f800, 0x00001804);
// 0x00030020 // 0x00000000 // 0x00000000
// 0x00020034 // 0x0000000b
ram_wr32(fuc, 0x13d8f4, 0x00000000);
ram_wr32(fuc, 0x100b0c, 0x00080028);
ram_wr32(fuc, 0x611200, 0x00003330);
ram_nsec(fuc, 100000);
ram_wr32(fuc, 0x10f9b0, 0x05313f41);
ram_wr32(fuc, 0x10f9b4, 0x00002f50);
nvc0_ram_train(fuc, 0x010c1001);
}
ram_mask(fuc, 0x10f200, 0x00000800, 0x00000800);
// 0x00020016 // 0x00000000
if (mode == 0)
ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
return 0;
}
u16
nvbios_timingEp(struct nvkm_bios *bios, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *p)
{
u16 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp;
p->timing_ver = *ver;
p->timing_hdr = *hdr;
switch (!!data * *ver) {
case 0x10:
p->timing_10_WR = nv_ro08(bios, data + 0x00);
p->timing_10_WTR = nv_ro08(bios, data + 0x01);
p->timing_10_CL = nv_ro08(bios, data + 0x02);
p->timing_10_RC = nv_ro08(bios, data + 0x03);
p->timing_10_RFC = nv_ro08(bios, data + 0x05);
p->timing_10_RAS = nv_ro08(bios, data + 0x07);
p->timing_10_RP = nv_ro08(bios, data + 0x09);
p->timing_10_RCDRD = nv_ro08(bios, data + 0x0a);
p->timing_10_RCDWR = nv_ro08(bios, data + 0x0b);
p->timing_10_RRD = nv_ro08(bios, data + 0x0c);
p->timing_10_13 = nv_ro08(bios, data + 0x0d);
p->timing_10_ODT = nv_ro08(bios, data + 0x0e) & 0x07;
p->timing_10_24 = 0xff;
p->timing_10_21 = 0;
p->timing_10_20 = 0;
p->timing_10_CWL = 0;
p->timing_10_18 = 0;
p->timing_10_16 = 0;
switch (min_t(u8, *hdr, 25)) {
case 25:
p->timing_10_24 = nv_ro08(bios, data + 0x18);
case 24:
case 23:
case 22:
p->timing_10_21 = nv_ro08(bios, data + 0x15);
case 21:
p->timing_10_20 = nv_ro08(bios, data + 0x14);
case 20:
p->timing_10_CWL = nv_ro08(bios, data + 0x13);
case 19:
p->timing_10_18 = nv_ro08(bios, data + 0x12);
case 18:
case 17:
p->timing_10_16 = nv_ro08(bios, data + 0x10);
}
break;
case 0x20:
p->timing[0] = nv_ro32(bios, data + 0x00);
p->timing[1] = nv_ro32(bios, data + 0x04);
p->timing[2] = nv_ro32(bios, data + 0x08);
p->timing[3] = nv_ro32(bios, data + 0x0c);
p->timing[4] = nv_ro32(bios, data + 0x10);
p->timing[5] = nv_ro32(bios, data + 0x14);
p->timing[6] = nv_ro32(bios, data + 0x18);
p->timing[7] = nv_ro32(bios, data + 0x1c);
p->timing[8] = nv_ro32(bios, data + 0x20);
p->timing[9] = nv_ro32(bios, data + 0x24);
p->timing[10] = nv_ro32(bios, data + 0x28);
p->timing_20_2e_03 = (nv_ro08(bios, data + 0x2e) & 0x03) >> 0;
p->timing_20_2e_30 = (nv_ro08(bios, data + 0x2e) & 0x30) >> 4;
p->timing_20_2e_c0 = (nv_ro08(bios, data + 0x2e) & 0xc0) >> 6;
p->timing_20_2f_03 = (nv_ro08(bios, data + 0x2f) & 0x03) >> 0;
temp = nv_ro16(bios, data + 0x2c);
p->timing_20_2c_003f = (temp & 0x003f) >> 0;
p->timing_20_2c_1fc0 = (temp & 0x1fc0) >> 6;
p->timing_20_30_07 = (nv_ro08(bios, data + 0x30) & 0x07) >> 0;
p->timing_20_30_f8 = (nv_ro08(bios, data + 0x30) & 0xf8) >> 3;
temp = nv_ro16(bios, data + 0x31);
p->timing_20_31_0007 = (temp & 0x0007) >> 0;
p->timing_20_31_0078 = (temp & 0x0078) >> 3;
p->timing_20_31_0780 = (temp & 0x0780) >> 7;
p->timing_20_31_0800 = (temp & 0x0800) >> 11;
p->timing_20_31_7000 = (temp & 0x7000) >> 12;
p->timing_20_31_8000 = (temp & 0x8000) >> 15;
break;
default:
data = 0;
break;
}
return data;
}