static int nvc0_graph_construct_context(struct nouveau_channel *chan) { struct drm_nouveau_private *dev_priv = chan->dev->dev_private; struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR); struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR]; struct drm_device *dev = chan->dev; int ret, i; u32 *ctx; ctx = kmalloc(priv->grctx_size, GFP_KERNEL); if (!ctx) return -ENOMEM; if (!nouveau_ctxfw) { nv_wr32(dev, 0x409840, 0x80000000); nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12); nv_wr32(dev, 0x409504, 0x00000001); if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) { NV_ERROR(dev, "PGRAPH: HUB_SET_CHAN timeout\n"); nvc0_graph_ctxctl_debug(dev); ret = -EBUSY; goto err; } } else {
static void nve0_graph_ctxctl_isr(struct nvc0_graph_priv *priv) { u32 ustat = nv_rd32(priv, 0x409c18); if (ustat & 0x00000001) nv_error(priv, "CTXCTRL ucode error\n"); if (ustat & 0x00080000) nv_error(priv, "CTXCTRL watchdog timeout\n"); if (ustat & ~0x00080001) nv_error(priv, "CTXCTRL 0x%08x\n", ustat); nvc0_graph_ctxctl_debug(priv); nv_wr32(priv, 0x409c20, ustat); }