void usbuart_init(void)
{
#if defined(BLACKMAGIC)
/* On mini hardware, UART and SWD share connector pins.
* Don't enable UART if we're being debugged. */
if ((platform_hwversion() == 1) && (SCS_DEMCR & SCS_DEMCR_TRCENA))
return;
#endif
rcc_periph_clock_enable(USBUSART_CLK);
UART_PIN_SETUP();
/* Setup UART parameters. */
usart_set_baudrate(USBUSART, 38400);
usart_set_databits(USBUSART, 8);
usart_set_stopbits(USBUSART, USART_STOPBITS_1);
usart_set_mode(USBUSART, USART_MODE_TX_RX);
usart_set_parity(USBUSART, USART_PARITY_NONE);
usart_set_flow_control(USBUSART, USART_FLOWCONTROL_NONE);
/* Finally enable the USART. */
usart_enable(USBUSART);
/* Enable interrupts */
USBUSART_CR1 |= USART_CR1_RXNEIE;
nvic_set_priority(USBUSART_IRQ, IRQ_PRI_USBUSART);
nvic_enable_irq(USBUSART_IRQ);
/* Setup timer for running deferred FIFO processing */
USBUSART_TIM_CLK_EN();
timer_reset(USBUSART_TIM);
timer_set_mode(USBUSART_TIM, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_prescaler(USBUSART_TIM,
rcc_ppre2_frequency / USBUART_TIMER_FREQ_HZ * 2 - 1);
timer_set_period(USBUSART_TIM,
USBUART_TIMER_FREQ_HZ / USBUART_RUN_FREQ_HZ - 1);
/* Setup update interrupt in NVIC */
nvic_set_priority(USBUSART_TIM_IRQ, IRQ_PRI_USBUSART_TIM);
nvic_enable_irq(USBUSART_TIM_IRQ);
/* turn the timer on */
timer_enable_counter(USBUSART_TIM);
}
static inline void usart_enable_irq(u8 IRQn) {
/* Note:
* In libstm32 times the priority of this interrupt was set to
* preemption priority 2 and sub priority 1
*/
/* Enable USART interrupts */
nvic_enable_irq(IRQn);
}
void platform_mrf_interrupt_enable(void) {
// Enable EXTI0 interrupt.
nvic_enable_irq(MRF_INTERRUPT_NVIC);
/* Configure the EXTI subsystem. */
exti_select_source(MRF_INTERRUPT_EXTI, MRF_INTERRUPT_PORT);
exti_set_trigger(MRF_INTERRUPT_EXTI, EXTI_TRIGGER_FALLING);
exti_enable_request(MRF_INTERRUPT_EXTI);
}
void imu_aspirin_arch_int_enable(void) {
#ifdef ASPIRIN_USE_GYRO_INT
nvic_set_priority(NVIC_EXTI15_10_IRQ, 0x0F);
nvic_enable_irq(NVIC_EXTI15_10_IRQ);
#endif
nvic_set_priority(NVIC_EXTI2_IRQ, 0x0F);
nvic_enable_irq(NVIC_EXTI2_IRQ);
// should not be needed anymore, handled by the spi driver
#if 0
/* Enable DMA1 channel4 IRQ Channel ( SPI RX) */
nvic_set_priority(NVIC_DMA1_CHANNEL4_IRQ, 0);
nvic_enable_irq(NVIC_DMA1_CHANNEL4_IRQ);
#endif
}
/* Function to init a timer */
void timer_setup(void)
{
/* Enable TIM2 clock. */
rcc_periph_clock_enable(RCC_TIM2);
/* Enable TIM2 interrupt. */
nvic_enable_irq(NVIC_TIM2_IRQ);
/* Reset TIM2 peripheral. */
timer_reset(TIM2);
/* Timer global mode:
* - No divider
* - Alignment edge
* - Direction up
*/
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* Reset prescaler value.
* Running the clock at 5kHz.
*/
/*
* On STM32F4 the timers are not running directly from pure APB1 or
* APB2 clock busses. The APB1 and APB2 clocks used for timers might
* be the double of the APB1 and APB2 clocks. This depends on the
* setting in DCKCFGR register. By default the behaviour is the
* following: If the Prescaler APBx is greater than 1 the derived timer
* APBx clocks will be double of the original APBx frequencies. Only if
* the APBx prescaler is set to 1 the derived timer APBx will equal the
* original APBx frequencies.
*
* In our case here the APB1 is devided by 4 system frequency and APB2
* divided by 2. This means APB1 timer will be 2 x APB1 and APB2 will
* be 2 x APB2. So when we try to calculate the prescaler value we have
* to use rcc_apb1_freqency * 2!!!
*
* For additional information see reference manual for the stm32f4
* familiy of chips. Page 204 and 213
*/
timer_set_prescaler(TIM2, ((rcc_apb1_frequency * 2) / 10000));
/* Disable preload. */
timer_disable_preload(TIM2);
/* Continous mode. */
timer_continuous_mode(TIM2);
/* Period (36kHz). */
timer_set_period(TIM2, 100);
/* Counter enable. */
timer_enable_counter(TIM2);
/* Enable update interrupt. */
timer_enable_irq(TIM2, TIM_DIER_UIE);
}
static void adc_setup(void)
{
//ADC
rcc_periph_clock_enable(RCC_ADC12);
rcc_periph_clock_enable(RCC_GPIOA);
//ADC
//gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO0); //pa0 //dead
gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO1); //pa1
gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO2); //pa2
gpio_mode_setup(GPIOF, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO4); //f4
if ((ADC1_CR & ADC_CR_ADEN) != 0 ){ //basically is ADC read yet. wait until ADDIS is done
ADC1_CR |= ADC_CR_ADDIS;
while (ADC1_CR & ADC_CR_ADDIS){}
}
ADC1_CFGR = ADC_CFGR_EXTEN_DISABLED | ADC_CFGR_RES_8_BIT ; //ADC_CFGR_CONT |ADC_CFGR_DMAEN | ADC_CFGR_EXTEN_RISING_EDGE |ADC_CFGR_EXTSEL_EVENT_4 |
ADC1_CFGR &= ~ADC_CFGR_ALIGN;
ADC_CCR = ADC_CCR_CKMODE_DIV1;
ADC1_IER = ADC_IER_EOCIE; //only on if you want to see one conversion at a time
ADC1_CR = ADC_CR_ADVREGEN_INTERMEDIATE;
ADC1_CR = ADC_CR_ADVREGEN_ENABLE;
ADC1_SMPR1 = (ADC_SMPR1_SMP_19DOT5CYC) << 9;
//ADC_SMPR1_SMP_1DOT5CYC = 4.8MSPS
//ADC_SMPR1_SMP_2DOT5CYC = 4.36MSPS
//ADC_SMPR1_SMP_4DOT5CYC = 3.7MSPS
//ADC_SMPR1_SMP_7DOT5CYC = 3.0MSPS, gets a bit unstable if higher.
//ADC_SMPR1_SMP_19DOT5CYC = 1.7MSPS
//ADC_SMPR1_SMP_61DOT5CYC = 685.7kSPS
//ADC_SMPR1_SMP_181DOT5CYC = 252.6kSPS
//ADC_SMPR1_SMP_601DOT5CYC = 78.7kSPS
ADC1_SQR1 = ( ( 3 ) << ADC_SQR1_SQ1_LSB ); //PA2
//calibration
//ADC1_CR |= ADC_CR_ADCALDIF; single
ADC1_CR |= ADC_CR_ADCAL; //single ended
while ((ADC1_CR & ADC_CR_ADCAL) != 0) {}
ADC1_CR |= ADC_CR_ADCALDIF; //diff
ADC1_CR |= ADC_CR_ADCAL;
while ((ADC1_CR & ADC_CR_ADCAL) != 0) {}
// power on ADC
ADC1_CR |= ADC_CR_ADEN;
nvic_enable_irq(NVIC_ADC1_2_IRQ); //only on if you want to see one conversion at a time
/* Wait for ADC starting up. */
while ((ADC1_ISR & ADC_ISR_ADRDY) == 0){}
ADC1_ISR = ADC_ISR_ADRDY;
}
void i2c3_hw_init(void) {
i2c3.reg_addr = (void *)I2C3;
i2c3.init_struct = NULL;
i2c3.errors = &i2c3_errors;
i2c3.watchdog = -1;
/* zeros error counter */
ZEROS_ERR_COUNTER(i2c3_errors);
/* reset peripheral to default state ( sometimes not achieved on reset :( ) */
//rcc_periph_reset_pulse(RST_I2C3);
/* Configure and enable I2C3 event interrupt --------------------------------*/
nvic_set_priority(NVIC_I2C3_EV_IRQ, NVIC_I2C3_IRQ_PRIO);
nvic_enable_irq(NVIC_I2C3_EV_IRQ);
/* Configure and enable I2C3 err interrupt ----------------------------------*/
nvic_set_priority(NVIC_I2C3_ER_IRQ, NVIC_I2C3_IRQ_PRIO+1);
nvic_enable_irq(NVIC_I2C3_ER_IRQ);
/* Enable peripheral clocks -------------------------------------------------*/
/* Enable I2C3 clock */
rcc_periph_clock_enable(RCC_I2C3);
/* setup gpio clock and pins */
i2c_setup_gpio(I2C3);
rcc_periph_reset_pulse(RST_I2C3);
// enable peripheral
i2c_peripheral_enable(I2C3);
/*
* XXX: there is a function to do that already in libopencm3 but I am not
* sure if it is correct, using direct register instead (esden)
*/
//i2c_set_own_7bit_slave_address(I2C3, 0);
I2C_OAR1(I2C3) = 0 | 0x4000;
// enable error interrupts
i2c_enable_interrupt(I2C3, I2C_CR2_ITERREN);
i2c_setbitrate(&i2c3, I2C3_CLOCK_SPEED);
}
void can_setup(void)
{
/* Enable peripheral clocks. */
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN);
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN);
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_CANEN);
/* Configure CAN pin: RX (input pull-up). */
gpio_set_mode(GPIOA, GPIO_MODE_INPUT,
GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_CAN_RX);
gpio_set(GPIOA, GPIO_CAN_RX);
/* Configure CAN pin: TX. */
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_CAN_TX);
/* NVIC setup. */
nvic_enable_irq(NVIC_USB_LP_CAN_RX0_IRQ);
nvic_set_priority(NVIC_USB_LP_CAN_RX0_IRQ, 1);
/* Reset CAN. */
can_reset(CAN1);
/* CAN cell init. */
if (can_init(CAN1,
false, /* TTCM: Time triggered comm mode? */
true, /* ABOM: Automatic bus-off management? */
false, /* AWUM: Automatic wakeup mode? */
false, /* NART: No automatic retransmission? */
false, /* RFLM: Receive FIFO locked mode? */
false, /* TXFP: Transmit FIFO priority? */
CAN_BTR_SJW_1TQ,
CAN_BTR_TS1_3TQ,
CAN_BTR_TS2_4TQ,
12)) /* BRP+1: Baud rate prescaler */
{
gpio_set(GPIOA, GPIO6); /* LED0 off */
gpio_set(GPIOA, GPIO7); /* LED1 off */
gpio_set(GPIOB, GPIO0); /* LED2 off */
gpio_clear(GPIOB, GPIO1); /* LED3 on */
/* Die because we failed to initialize. */
while (1)
__asm__("nop");
}
/* CAN filter 0 init. */
can_filter_id_mask_32bit_init(CAN1,
0, /* Filter ID */
0, /* CAN ID */
0, /* CAN ID mask */
0, /* FIFO assignment (here: FIFO0) */
true); /* Enable the filter. */
/* Enable CAN RX interrupt. */
can_enable_irq(CAN1, CAN_IER_FMPIE0);
}
void frosted_scheduler_on(void)
{
nvic_set_priority(NVIC_PENDSV_IRQ, 2);
nvic_set_priority(NVIC_SV_CALL_IRQ, 1);
nvic_set_priority(NVIC_SYSTICK_IRQ, 0);
nvic_enable_irq(NVIC_SYSTICK_IRQ);
_sched_active = 1;
systick_interrupt_enable();
}
void cc3k_global_irq_enable(char val) {
if (val) {
nvic_enable_irq(NVIC_EXTI0_1_IRQ);
systick_interrupt_enable();
} else {
nvic_disable_irq(NVIC_EXTI0_1_IRQ);
systick_interrupt_disable();
}
}
/* Configure USART2 as a 38400, 8N1 serial port that has an interrupt
* driven receive function (transmit is blocking)
*/
void uart_setup(int baud)
{
/* Setup GPIO pins for USART2 transmit. */
gpio_mode_setup(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO6);
gpio_mode_setup(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO7);
gpio_set_output_options(GPIOC, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ, GPIO7);
gpio_set_af(GPIOC, GPIO_AF8, GPIO6);
gpio_set_af(GPIOC, GPIO_AF8, GPIO7);
/* Setup USART6 parameters. */
usart_set_baudrate(USART6, baud);
usart_set_databits(USART6, 8);
usart_set_stopbits(USART6, USART_STOPBITS_1);
usart_set_mode(USART6, USART_MODE_TX_RX);
usart_set_parity(USART6, USART_PARITY_NONE);
usart_set_flow_control(USART6, USART_FLOWCONTROL_NONE);
/* Allow for receive interrupts */
buf_ndx = 0;
read_ndx = 0;
nvic_enable_irq(NVIC_USART6_IRQ);
/* Finally enable the USART. */
usart_enable(USART6);
usart_enable_rx_interrupt(USART6);
/* Setup USART2 parameters. */
usart_set_baudrate(USART2, 38400);
usart_set_databits(USART2, 8);
usart_set_stopbits(USART2, USART_STOPBITS_1);
usart_set_mode(USART2, USART_MODE_TX_RX);
usart_set_parity(USART2, USART_PARITY_NONE);
usart_set_flow_control(USART2, USART_FLOWCONTROL_NONE);
/* Allow for receive interrupts */
buf_ndx = 0;
read_ndx = 0;
nvic_enable_irq(NVIC_USART2_IRQ);
/* Finally enable the USART. */
usart_enable(USART2);
usart_enable_rx_interrupt(USART2);
}
void baro_init()
{
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO14);
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO13 | GPIO15);
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, GPIO12);
deselect_slave();
spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_8, SPI_CR1_CPOL,
SPI_CR1_CPHA, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
spi_enable_ss_output(SPI2);
spi_enable(SPI2);
dma_set_peripheral_address(DMA1, DMA_CHANNEL3, SPI2_DR);
dma_set_read_from_memory(DMA1, DMA_CHANNEL3);
dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL3);
dma_set_peripheral_size(DMA1, DMA_CHANNEL3, DMA_CCR_PSIZE_8BIT);
dma_set_memory_size(DMA1, DMA_CHANNEL3, DMA_CCR_MSIZE_8BIT);
dma_set_priority(DMA1, DMA_CHANNEL3, DMA_CCR_PL_HIGH);
dma_set_peripheral_address(DMA1, DMA_CHANNEL4, SPI2_DR);
dma_set_read_from_peripheral(DMA1, DMA_CHANNEL4);
dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL4);
dma_set_peripheral_size(DMA1, DMA_CHANNEL4, DMA_CCR_PSIZE_8BIT);
dma_set_memory_size(DMA1, DMA_CHANNEL4, DMA_CCR_MSIZE_8BIT);
dma_set_priority(DMA1, DMA_CHANNEL4, DMA_CCR_PL_VERY_HIGH);
dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL4);
timer_reset(TIM4);
timer_enable_irq(TIM4, TIM_DIER_UIE);
timer_set_mode(TIM4, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* 3200 / 16 = 200 Hz */
timer_set_prescaler(TIM4, 32);
timer_set_period(TIM4, 5625);
nvic_set_priority(NVIC_TIM4_IRQ, 16 * 2);
nvic_set_priority(NVIC_DMA1_CHANNEL4_IRQ, 16 * 2);
nvic_enable_irq(NVIC_TIM4_IRQ);
nvic_enable_irq(NVIC_DMA1_CHANNEL4_IRQ);
read_calibration_data();
}
/** Setup the USART for recieve with DMA. This function sets up the DMA
* controller and additional USART parameters for DMA receive. The USART must
* first be configured using \ref usart_setup_common. */
void usart_rx_dma_setup(void) {
/* Set up the USART1 RX DMA and interrupts. */
/* Enable clock to DMA peripheral. */
RCC_AHB1ENR |= RCC_AHB1ENR_DMA2EN;
/* Enable RX DMA on the USART. */
usart_enable_rx_dma(USART1);
/* USART1 RX - DMA2, stream 5, channel 4. */
/* Make sure stream is disabled to start. */
DMA2_S5CR &= ~DMA_SxCR_EN;
DMA2_S5CR = 0;
/* Configure the DMA controller. */
/* Error interrupts. */
DMA2_S5CR = DMA_SxCR_DMEIE | DMA_SxCR_TEIE |
/* Transfer complete interrupt. */
DMA_SxCR_TCIE |
/* Enable circular buffer mode. */
DMA_SxCR_CIRC |
DMA_SxCR_DIR_PERIPHERAL_TO_MEM |
/* Increment the memory address after each transfer. */
DMA_SxCR_MINC |
/* 8 bit transfers from USART peripheral. */
DMA_SxCR_PSIZE_8BIT |
/* and to memory. */
DMA_SxCR_MSIZE_8BIT |
/* Low priority. */
DMA_SxCR_PL_LOW |
/* The channel selects which request line will trigger a
* transfer. In this case, channel 4 = UART1_RX
* (see CD00225773.pdf Table 23). */
DMA_SxCR_CHSEL(4);
/* Transfer up the the length of the buffer. */
DMA2_S5NDTR = USART_RX_BUFFER_LEN;
DMA2_S5PAR = &USART1_DR; /* DMA from the USART1 data register. */
DMA2_S5M0AR = rx_buff; /* to the rx_buff. */
// TODO: Investigate more about the best FIFO settings.
DMA2_S5FCR = DMA_SxFCR_DMDIS | /* Enable DMA stream FIFO. */
DMA_SxFCR_FTH_2_4_FULL | /* Trigger level 1/2 full. */
DMA_SxFCR_FEIE; /* Enable FIFO error interrupt. */
rx_rd = 0; /* Buffer is empty to begin with. */
rd_wraps = wr_wraps = 0;
/* Enable DMA2 Stream 5 (RX) interrupts with the NVIC. */
nvic_enable_irq(NVIC_DMA2_STREAM5_IRQ);
/* Enable the DMA channel. */
DMA2_S5CR |= DMA_SxCR_EN;
}
/*
M0 Core Manage USB
*/
int main(void)
{
iap_cmd_res_t iap_cmd_res;
usb_descriptor_serial_number_t serial_number;
airspy_usb_req_init();
usb_set_configuration_changed_cb(usb_configuration_changed);
usb_peripheral_reset();
usb_device_init(0, &usb_device);
usb_queue_init(&usb_endpoint_control_out_queue);
usb_queue_init(&usb_endpoint_control_in_queue);
usb_queue_init(&usb_endpoint_bulk_out_queue);
usb_queue_init(&usb_endpoint_bulk_in_queue);
usb_endpoint_init(&usb_endpoint_control_out);
usb_endpoint_init(&usb_endpoint_control_in);
/* Read IAP Serial Number Identification */
iap_cmd_res.cmd_param.command_code = IAP_CMD_READ_SERIAL_NO;
iap_cmd_call(&iap_cmd_res);
if(iap_cmd_res.status_res.status_ret == CMD_SUCCESS)
{
/* Only retrieve 2 last 32bits for Serial Number */
serial_number.sn_32b[0] = iap_cmd_res.status_res.iap_result[2];
serial_number.sn_32b[1] = iap_cmd_res.status_res.iap_result[3];
usb_descriptor_fill_string_serial_number(serial_number);
}
nvic_set_priority(NVIC_USB0_IRQ, 255);
nvic_set_priority(NVIC_M4CORE_IRQ, 1);
nvic_enable_irq(NVIC_M4CORE_IRQ);
usb_run(&usb_device);
while(true)
{
signal_wfe();
if( (get_usb_buffer_offset() >= 16384) &&
(phase == 1) )
{
usb_transfer_schedule_block(&usb_endpoint_bulk_in, &usb_bulk_buffer[0x0000], 0x4000, NULL, NULL);
phase = 0;
}
if( (get_usb_buffer_offset() < 16384) &&
(phase == 0) )
{
usb_transfer_schedule_block(&usb_endpoint_bulk_in, &usb_bulk_buffer[0x4000], 0x4000, NULL, NULL);
phase = 1;
}
}
}
void timer_setup() {
RCC_APB1ENR |= RCC_APB1ENR_TIM2EN;
timer_set_prescaler(TIM2, 1);
timer_set_period(TIM2, rcc_ppre1_frequency / 100);
timer_enable_irq(TIM2, TIM_DIER_UIE);
TIM2_CNT = 0;
timer_enable_counter(TIM2);
nvic_enable_irq(NVIC_TIM2_IRQ);
}
void ROBOT_initIsr(uint32_t port, uint32_t exti, uint8_t irqn, uint8_t priority, enum exti_trigger_type trig)
{
// exti
exti_select_source(exti, port);
exti_set_trigger(exti, trig);
exti_enable_request(exti);
// enable interrupt
nvic_enable_irq(irqn);
nvic_set_priority(irqn,priority);
}
/*
* IRQ setup:
* Trigger an interrupt whenever a button is depressed.
*/
static void irq_setup(void)
{
const uint32_t btnpins = USR_SW1 | USR_SW2;
/* Trigger interrupt on rising-edge (when button is depressed) */
gpio_configure_trigger(GPIOF, GPIO_TRIG_EDGE_RISE, btnpins);
/* Finally, Enable interrupt */
gpio_enable_interrupts(GPIOF, btnpins);
/* Enable the interrupt in the NVIC as well */
nvic_enable_irq(NVIC_GPIOF_IRQ);
}
void acq_start()
{
spi_enable(SPI_C1);
spi_enable_rx_dma(SPI_C1);
dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL2);
dma_enable_half_transfer_interrupt(DMA1, DMA_CHANNEL2);
dma_enable_channel(DMA1, DMA_CHANNEL2);
nvic_enable_irq(NVIC_DMA1_CHANNEL2_IRQ);
}
/* *************** HAL API functions **************************************** */
void hal_init( void ) {
int ret = 0;
/* Reset variables used in file. */
hal_system_time = 0;
// hal_reset_flags();
/* Enable GPIOA clock. Enable AFIO clock. */
rcc_peripheral_enable_clock(&RCC_APB2ENR,
RCC_APB2ENR_IOPAEN |
RCC_APB2ENR_IOPBEN |
RCC_APB2ENR_IOPCEN |
RCC_APB2ENR_SPI1EN |
RCC_APB2ENR_AFIOEN );
/* The following pins are output pins. */
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL,RST); //reset
gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL,SLP_TR); //sleep
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL,SEL); //cs
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL,
SCK | MOSI | MISO); //sck mosi miso
spi_disable(RF_SPI);
SPI2_I2SCFGR = 0;
/* Setup SPI parameters. */
spi_init_master(RF_SPI, SPI_CR1_BAUDRATE_FPCLK_DIV_16, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
spi_set_unidirectional_mode(RF_SPI);
spi_set_full_duplex_mode(RF_SPI); /* Not receive-only */
spi_enable_software_slave_management(RF_SPI);
spi_set_nss_high(RF_SPI);
spi_enable_ss_output(RF_SPI); /* Required, see NSS, 25.3.1 section. */
/* Finally enable the SPI. */
spi_enable(RF_SPI);
/* Set GPIO4 (in GPIO port C) to 'input float'. */
gpio_set_mode(RF_IRQ_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, RF_IRQ_PIN);
gpio_clear(RF_IRQ_PORT, RF_IRQ_PIN);
/* Configure the EXTI subsystem. */
exti_select_source(EXTI4, RF_IRQ_PORT);
exti_set_trigger(EXTI4, EXTI_TRIGGER_RISING);
exti_enable_request(EXTI4);
exti_reset_request(EXTI4);
PRINTF("Enabling interrupts\r\n");
/* Enable EXTI0 interrupt. */
nvic_enable_irq(NVIC_EXTI4_IRQ);
nvic_set_priority(NVIC_EXTI4_IRQ,4);
//@@@!? timer_init();
// ret = trx_init();
// if(ret!=0)
// {
// PRINTF("rf231:hal init failed\r\n");
// }else
// {
// PRINTF("rf231:hal init success\r\n");
// }
}
int MSCenable(void){
USBD_API_INIT_PARAM_T usb_param;
USB_CORE_DESCS_T desc;
ErrorCode_t ret = LPC_OK;
USB_CORE_CTRL_T *pCtrl;
flashInit();
usb_clock_init();
usb_phy_enable();
/* Init USB API structure */
g_pUsbApi = (const USBD_API_T *) LPC_ROM_API->usbdApiBase;
/* initialize call back structures */
memset((void *) &usb_param, 0, sizeof(USBD_API_INIT_PARAM_T));
usb_param.usb_reg_base = LPC_USB_BASE;
usb_param.mem_base = USB_STACK_MEM_BASE;
usb_param.mem_size = USB_STACK_MEM_SIZE;
usb_param.max_num_ep = 2;
/* Set the USB descriptors */
desc.device_desc = (uint8_t *) USB_msc_DeviceDescriptor;
desc.string_desc = (uint8_t *) USB_msc_StringDescriptor;
desc.high_speed_desc = USB_msc_HsConfigDescriptor;
desc.full_speed_desc = USB_msc_FsConfigDescriptor;
desc.device_qualifier = (uint8_t *) USB_msc_DeviceQualifier;
/* USB Initialization */
ret = USBD_API->hw->Init(&g_hUsb, &desc, &usb_param);
if (ret == LPC_OK) {
/* WORKAROUND for artf45032 ROM driver BUG:
Due to a race condition there is the chance that a second NAK event will
occur before the default endpoint0 handler has completed its preparation
of the DMA engine for the first NAK event. This can cause certain fields
in the DMA descriptors to be in an invalid state when the USB controller
reads them, thereby causing a hang.
*/
pCtrl = (USB_CORE_CTRL_T *) g_hUsb; /* convert the handle to control structure */
g_Ep0BaseHdlr = pCtrl->ep_event_hdlr[0];/* retrieve the default EP0_OUT handler */
pCtrl->ep_event_hdlr[0] = EP0_patch;/* set our patch routine as EP0_OUT handler */
ret = mscDisk_init(g_hUsb, &desc, &usb_param);
if (ret == LPC_OK) {
/* enable USB interrrupts */
nvic_enable_irq(NVIC_USB0_IRQ);
/* now connect */
USBD_API->hw->Connect(g_hUsb, 1);
return 0;
}
}
return 1;
}
void PPMin_Start()
{
if (Model.protocol == PROTOCOL_PPM)
CLOCK_StopTimer();
PPMin_Init();
ppmSync = 0;
timer_enable_counter(TIM1);
nvic_enable_irq(NVIC_EXTI9_5_IRQ);
exti_enable_request(_PWM_EXTI);
ppmSync = 0;
}
void client_server_serialirq_init(void)
{
serial_rb_init(&srx, &(srx_buf[0]), YWASP_SERIAL_RX_BUF);
serial_rb_init(&stx, &(stx_buf[0]), YWASP_SERIAL_TX_BUF);
/* Enable the USART1 interrupt. */
nvic_enable_irq(NVIC_USART1_IRQ);
/* Enable USART1 Receive interrupt. */
USART_CR1(USART1) |= USART_CR1_RXNEIE;
}
/** PWM arch init called by generic pwm driver
*/
void actuators_dualpwm_arch_init(void)
{
/*-----------------------------------
* Configure timer peripheral clocks
*-----------------------------------*/
#if PWM_USE_TIM1
rcc_periph_clock_enable(RCC_TIM1);
#endif
#if PWM_USE_TIM2
rcc_periph_clock_enable(RCC_TIM2);
#endif
#if PWM_USE_TIM3
rcc_periph_clock_enable(RCC_TIM3);
#endif
#if PWM_USE_TIM4
rcc_periph_clock_enable(RCC_TIM4);
#endif
#if PWM_USE_TIM5
rcc_periph_clock_enable(RCC_TIM5);
#endif
#if PWM_USE_TIM8
rcc_periph_clock_enable(RCC_TIM8);
#endif
#if PWM_USE_TIM9
rcc_periph_clock_enable(RCC_TIM9);
#endif
#if PWM_USE_TIM12
rcc_periph_clock_enable(RCC_TIM12);
#endif
/*----------------
* Configure GPIO
*----------------*/
#ifdef DUAL_PWM_SERVO_5
gpio_setup_pin_af(DUAL_PWM_SERVO_5_GPIO, DUAL_PWM_SERVO_5_PIN, DUAL_PWM_SERVO_5_AF, TRUE);
#endif
#ifdef DUAL_PWM_SERVO_6
gpio_setup_pin_af(DUAL_PWM_SERVO_6_GPIO, DUAL_PWM_SERVO_6_PIN, DUAL_PWM_SERVO_6_AF, TRUE);
#endif
#if DUAL_PWM_USE_TIM5
set_servo_timer(TIM5, TIM5_SERVO_HZ, PWM_TIM5_CHAN_MASK);
nvic_set_priority(NVIC_TIM5_IRQ, 2);
nvic_enable_irq(NVIC_TIM5_IRQ);
timer_enable_irq(TIM5, TIM_DIER_CC1IE);
#endif
//calculation the values to put into the timer registers to generate pulses every 4ms and 16ms.
ratio_4ms = (ONE_MHZ_CLK / 250) - 1;
ratio_16ms = (ONE_MHZ_CLK / 62.5) - 1;
}
/**
* We set this timer to count uSecs.
* The interrupt is only to indicate that it timed out and to shut itself off.
*/
void setup_tim7(void)
{
timer_clear_flag(TIM7, TIM_SR_UIF);
TIM7_CNT = 1;
timer_set_prescaler(TIM7, 23); // 24Mhz/1Mhz - 1
timer_set_period(TIM7, RHT_INTER_BIT_TIMEOUT_USEC);
timer_enable_irq(TIM7, TIM_DIER_UIE);
nvic_enable_irq(NVIC_TIM7_IRQ);
timer_enable_counter(TIM7);
}
/* Enable serial data reception by providing a callback function
to accept received character and status. Disable by calling with argument NULL.
Callback executes in interrupt context and must be short.
*/
void UART_StartReceive(usart_callback_t *isr_callback)
{
rx_callback = isr_callback;
if (isr_callback) {
nvic_enable_irq(get_nvic_irq(UART_CFG.uart));
usart_enable_rx_interrupt(UART_CFG.uart);
} else {
usart_disable_rx_interrupt(UART_CFG.uart);
nvic_disable_irq(get_nvic_irq(UART_CFG.uart));
}
}
void freq_capture_setup(void) {
/* Configure PE11 (AF1: TIM1_CH2) (SYNC_IN). */
rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPEEN);
gpio_mode_setup(GPIOE, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO11);
gpio_set_af(GPIOE, GPIO_AF1, GPIO11);
/* Timer1: Input compare */
/* Enable timer clock. */
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN);
/* Reset timer. */
timer_reset(TIM1);
/* Configure timer1. */
timer_set_mode(TIM1,
TIM_CR1_CKD_CK_INT, // Internal clock
TIM_CR1_CMS_EDGE, // Edge synchronization
TIM_CR1_DIR_UP); // Count upward
timer_set_prescaler(TIM1, TIMER1_PRESCALER);
timer_set_period(TIM1, TIMER1_PERIOD); //Sets TIM1_ARR
timer_continuous_mode(TIM1);
/* Configure PE13: Toggle pin on falling edge via interrupt */
//rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPEEN);
//gpio_mode_setup(GPIOE, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLDOWN, GPIO13);
/* Configure input capture. */
timer_ic_disable(TIM1, TIM_IC2);
timer_ic_set_polarity(TIM1, TIM_IC2, TIM_IC_RISING);
timer_ic_set_prescaler(TIM1, TIM_IC2, TIM_IC_PSC_OFF);
timer_ic_set_input(TIM1, TIM_IC2, TIM_IC_IN_TI2);
// See RM, p. 561: digital filter
//timer_ic_set_filter(TIM1, TIM_IC2, TIM_IC_DTF_DIV_32_N_8);
timer_ic_set_filter(TIM1, TIM_IC2, TIM_IC_OFF);
timer_ic_enable(TIM1, TIM_IC2);
/* Enable counter. */
timer_enable_counter(TIM1);
timer_clear_flag (TIM1, TIM_SR_CC2IF);
/* Enable IRQs */
nvic_enable_irq(NVIC_TIM1_UP_TIM10_IRQ);
timer_enable_irq(TIM1, TIM_DIER_UIE);
nvic_enable_irq(NVIC_TIM1_CC_IRQ);
timer_enable_irq(TIM1, TIM_DIER_CC2IE);
}
void cdcacm_init(void) {
//system setup
rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPAEN);
rcc_peripheral_enable_clock(&RCC_AHB2ENR, RCC_AHB2ENR_OTGFSEN);
gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE,
GPIO9 | GPIO11 | GPIO12);
gpio_set_af(GPIOA, GPIO_AF10, GPIO9 | GPIO11 | GPIO12);
cdcacm_usb_init();
nvic_set_priority(NVIC_OTG_FS_IRQ, IRQ_PRI_USB);
nvic_enable_irq(NVIC_OTG_FS_IRQ);
while (cdcacm_get_config() != 1) { wait(1); }; //wait until usb is configured
}
void jack_setup() {
nvic_set_priority(NVIC_EXTI1_IRQ,0x00);
/* Enable EXTI1 interrupt. */
nvic_enable_irq(NVIC_EXTI1_IRQ);
gpio_mode_setup(JACK_SENSE_PORT, GPIO_MODE_INPUT, GPIO_PUPD_NONE, JACK_SENSE_PIN);
/* Configure the EXTI subsystem. */
exti_select_source(EXTI1, JACK_SENSE_PORT);
exti_set_trigger(EXTI1, EXTI_TRIGGER_BOTH);
exti_enable_request(EXTI1);
}
/*
* Another ms timer, this one used to generate an overflow interrupt at 1ms
* It is used to toggle leds and write tick counts
*/
static void setup_tim6(void)
{
timer_reset(TIM6);
/* 24Mhz / 10khz -1. */
timer_set_prescaler(TIM6, 2399); /* 24Mhz/10000hz - 1 */
/* 10khz for 10 ticks = 1 khz overflow = 1ms overflow interrupts */
timer_set_period(TIM6, 10);
nvic_enable_irq(NVIC_TIM6_IRQ);
timer_enable_update_event(TIM6); /* default at reset! */
timer_enable_irq(TIM6, TIM_DIER_UIE);
timer_enable_counter(TIM6);
}
void hal_uart_dma_set_csr_irq_handler( void (*the_irq_handler)(void)){
if (the_irq_handler){
/* Configure the EXTI13 interrupt (USART3_CTS is on PB13) */
nvic_enable_irq(NVIC_EXTI15_10_IRQ);
exti_select_source(EXTI13, GPIOB);
exti_set_trigger(EXTI13, EXTI_TRIGGER_RISING);
exti_enable_request(EXTI13);
} else {
exti_disable_request(EXTI13);
nvic_disable_irq(NVIC_EXTI15_10_IRQ);
}
cts_irq_handler = the_irq_handler;
}
