void nx__twi_write_async(U32 dev_addr, U8 *data, U32 len)
{
U32 mode = ((dev_addr & 0x7f) << 16) | AT91C_TWI_IADRSZ_NO;
NX_ASSERT(dev_addr == 1);
NX_ASSERT(data != NULL);
NX_ASSERT(len > 0);
NX_ASSERT(nx__twi_ready());
twi_state.mode = TWI_TX_BUSY;
twi_state.ptr = data;
twi_state.len = len;
*AT91C_TWI_MMR = mode;
*AT91C_TWI_CR = AT91C_TWI_START | AT91C_TWI_MSEN;
*AT91C_TWI_IER = AT91C_TWI_TXRDY;
}
static nx__ram_function bool nx__efc_do_write(U32 page) {
U32 ret;
NX_ASSERT(page < EFC_PAGES);
// turn off systick callbacks
nx_systick_suspend();
// sync
nx_systick_wait_ms(1);
// manually call avr update
nx__avr_fast_update();
// wait for avr update
while (!nx__twi_ready());
// disable interrupts
nx_interrupts_disable();
/* Trigger the flash write command. */
*AT91C_MC_FCR = EFC_WRITE + ((page & 0x000003FF) << 8);
/* Wait for the command to complete. */
do {
ret = *AT91C_MC_FSR;
} while (!(ret & AT91C_MC_FRDY));
// reenable interrupts
nx_interrupts_enable();
// sync
nx_systick_wait_ms(1);
// turn on systick callbacks
nx_systick_resume();
/* Check the command result by reading the status register
* only once to avoid the bits being cleared.
*/
if (ret & AT91C_MC_LOCKE || ret & AT91C_MC_PROGE)
return FALSE;
return TRUE;
}
