static void pc_dimm_md_fill_device_info(const MemoryDeviceState *md, MemoryDeviceInfo *info) { PCDIMMDeviceInfo *di = g_new0(PCDIMMDeviceInfo, 1); const DeviceClass *dc = DEVICE_GET_CLASS(md); const PCDIMMDevice *dimm = PC_DIMM(md); const DeviceState *dev = DEVICE(md); if (dev->id) { di->has_id = true; di->id = g_strdup(dev->id); } di->hotplugged = dev->hotplugged; di->hotpluggable = dc->hotpluggable; di->addr = dimm->addr; di->slot = dimm->slot; di->node = dimm->node; di->size = object_property_get_uint(OBJECT(dimm), PC_DIMM_SIZE_PROP, NULL); di->memdev = object_get_canonical_path(OBJECT(dimm->hostmem)); if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { info->u.nvdimm.data = di; info->type = MEMORY_DEVICE_INFO_KIND_NVDIMM; } else { info->u.dimm.data = di; info->type = MEMORY_DEVICE_INFO_KIND_DIMM; } }
uint16_t pvpanic_port(void) { Object *o = object_resolve_path_type("", TYPE_PVPANIC, NULL); if (!o) { return 0; } return object_property_get_uint(o, PVPANIC_IOPORT_PROP, NULL); }
/* ACPI 6.0: 5.2.25.1 System Physical Address Range Structure */ static void nvdimm_build_structure_spa(GArray *structures, DeviceState *dev) { NvdimmNfitSpa *nfit_spa; uint64_t addr = object_property_get_uint(OBJECT(dev), PC_DIMM_ADDR_PROP, NULL); uint64_t size = object_property_get_uint(OBJECT(dev), PC_DIMM_SIZE_PROP, NULL); uint32_t node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, NULL); int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP, NULL); nfit_spa = acpi_data_push(structures, sizeof(*nfit_spa)); nfit_spa->type = cpu_to_le16(0 /* System Physical Address Range Structure */); nfit_spa->length = cpu_to_le16(sizeof(*nfit_spa)); nfit_spa->spa_index = cpu_to_le16(nvdimm_slot_to_spa_index(slot)); /* * Control region is strict as all the device info, such as SN, index, * is associated with slot id. */ nfit_spa->flags = cpu_to_le16(1 /* Control region is strictly for management during hot add/online operation */ | 2 /* Data in Proximity Domain field is valid*/); /* NUMA node. */ nfit_spa->proximity_domain = cpu_to_le32(node); /* the region reported as PMEM. */ memcpy(nfit_spa->type_guid, nvdimm_nfit_spa_uuid, sizeof(nvdimm_nfit_spa_uuid)); nfit_spa->spa_base = cpu_to_le64(addr); nfit_spa->spa_length = cpu_to_le64(size); /* It is the PMEM and can be cached as writeback. */ nfit_spa->mem_attr = cpu_to_le64(0x8ULL /* EFI_MEMORY_WB */ | 0x8000ULL /* EFI_MEMORY_NV */); }
void pc_dimm_plug(DeviceState *dev, MachineState *machine, uint64_t align, Error **errp) { int slot; PCDIMMDevice *dimm = PC_DIMM(dev); PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); MemoryRegion *vmstate_mr = ddc->get_vmstate_memory_region(dimm, &error_abort); MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); Error *local_err = NULL; uint64_t addr; addr = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); if (local_err) { goto out; } addr = memory_device_get_free_addr(machine, !addr ? NULL : &addr, align, memory_region_size(mr), &local_err); if (local_err) { goto out; } object_property_set_uint(OBJECT(dev), addr, PC_DIMM_ADDR_PROP, &local_err); if (local_err) { goto out; } trace_mhp_pc_dimm_assigned_address(addr); slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP, &local_err); if (local_err) { goto out; } slot = pc_dimm_get_free_slot(slot == PC_DIMM_UNASSIGNED_SLOT ? NULL : &slot, machine->ram_slots, &local_err); if (local_err) { goto out; } object_property_set_int(OBJECT(dev), slot, PC_DIMM_SLOT_PROP, &local_err); if (local_err) { goto out; } trace_mhp_pc_dimm_assigned_slot(slot); memory_device_plug_region(machine, mr, addr); vmstate_register_ram(vmstate_mr, dev); out: error_propagate(errp, local_err); }
/* aux-slave implementation */ static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent) { AUXBus *bus = AUX_BUS(qdev_get_parent_bus(dev)); AUXSlave *s; /* Don't print anything if the device is I2C "bridge". */ if (aux_bus_is_bridge(bus, dev)) { return; } s = AUX_SLAVE(dev); monitor_printf(mon, "%*smemory " TARGET_FMT_plx "/" TARGET_FMT_plx "\n", indent, "", object_property_get_uint(OBJECT(s->mmio), "addr", NULL), memory_region_size(s->mmio)); }
static int pc_existing_dimms_capacity_internal(Object *obj, void *opaque) { pc_dimms_capacity *cap = opaque; uint64_t *size = &cap->size; if (object_dynamic_cast(obj, TYPE_PC_DIMM)) { DeviceState *dev = DEVICE(obj); if (dev->realized) { (*size) += object_property_get_uint(obj, PC_DIMM_SIZE_PROP, cap->errp); } if (cap->errp && *cap->errp) { return 1; } } object_child_foreach(obj, pc_existing_dimms_capacity_internal, opaque); return 0; }
int qmp_pc_dimm_device_list(Object *obj, void *opaque) { MemoryDeviceInfoList ***prev = opaque; if (object_dynamic_cast(obj, TYPE_PC_DIMM)) { DeviceState *dev = DEVICE(obj); if (dev->realized) { MemoryDeviceInfoList *elem = g_new0(MemoryDeviceInfoList, 1); MemoryDeviceInfo *info = g_new0(MemoryDeviceInfo, 1); PCDIMMDeviceInfo *di = g_new0(PCDIMMDeviceInfo, 1); DeviceClass *dc = DEVICE_GET_CLASS(obj); PCDIMMDevice *dimm = PC_DIMM(obj); if (dev->id) { di->has_id = true; di->id = g_strdup(dev->id); } di->hotplugged = dev->hotplugged; di->hotpluggable = dc->hotpluggable; di->addr = dimm->addr; di->slot = dimm->slot; di->node = dimm->node; di->size = object_property_get_uint(OBJECT(dimm), PC_DIMM_SIZE_PROP, NULL); di->memdev = object_get_canonical_path(OBJECT(dimm->hostmem)); info->u.dimm.data = di; elem->value = info; elem->next = NULL; **prev = elem; *prev = &elem->next; } } object_child_foreach(obj, qmp_pc_dimm_device_list, opaque); return 0; }
/* * ACPI 6.0: 5.2.25.2 Memory Device to System Physical Address Range Mapping * Structure */ static void nvdimm_build_structure_memdev(GArray *structures, DeviceState *dev) { NvdimmNfitMemDev *nfit_memdev; NVDIMMDevice *nvdimm = NVDIMM(OBJECT(dev)); uint64_t size = object_property_get_uint(OBJECT(dev), PC_DIMM_SIZE_PROP, NULL); int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP, NULL); uint32_t handle = nvdimm_slot_to_handle(slot); nfit_memdev = acpi_data_push(structures, sizeof(*nfit_memdev)); nfit_memdev->type = cpu_to_le16(1 /* Memory Device to System Address Range Map Structure*/); nfit_memdev->length = cpu_to_le16(sizeof(*nfit_memdev)); nfit_memdev->nfit_handle = cpu_to_le32(handle); /* * associate memory device with System Physical Address Range * Structure. */ nfit_memdev->spa_index = cpu_to_le16(nvdimm_slot_to_spa_index(slot)); /* associate memory device with Control Region Structure. */ nfit_memdev->dcr_index = cpu_to_le16(nvdimm_slot_to_dcr_index(slot)); /* The memory region on the device. */ nfit_memdev->region_len = cpu_to_le64(size); /* The device address starts from 0. */ nfit_memdev->region_dpa = cpu_to_le64(0); /* Only one interleave for PMEM. */ nfit_memdev->interleave_ways = cpu_to_le16(1); if (nvdimm->unarmed) { nfit_memdev->flags |= cpu_to_le16(ACPI_NFIT_MEM_NOT_ARMED); } }
void pc_dimm_memory_plug(DeviceState *dev, MemoryHotplugState *hpms, MemoryRegion *mr, uint64_t align, Error **errp) { int slot; MachineState *machine = MACHINE(qdev_get_machine()); PCDIMMDevice *dimm = PC_DIMM(dev); PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); MemoryRegion *vmstate_mr = ddc->get_vmstate_memory_region(dimm); Error *local_err = NULL; uint64_t existing_dimms_capacity = 0; uint64_t addr; addr = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); if (local_err) { goto out; } addr = pc_dimm_get_free_addr(hpms->base, memory_region_size(&hpms->mr), !addr ? NULL : &addr, align, memory_region_size(mr), &local_err); if (local_err) { goto out; } existing_dimms_capacity = pc_existing_dimms_capacity(&local_err); if (local_err) { goto out; } if (existing_dimms_capacity + memory_region_size(mr) > machine->maxram_size - machine->ram_size) { error_setg(&local_err, "not enough space, currently 0x%" PRIx64 " in use of total hot pluggable 0x" RAM_ADDR_FMT, existing_dimms_capacity, machine->maxram_size - machine->ram_size); goto out; } object_property_set_uint(OBJECT(dev), addr, PC_DIMM_ADDR_PROP, &local_err); if (local_err) { goto out; } trace_mhp_pc_dimm_assigned_address(addr); slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP, &local_err); if (local_err) { goto out; } slot = pc_dimm_get_free_slot(slot == PC_DIMM_UNASSIGNED_SLOT ? NULL : &slot, machine->ram_slots, &local_err); if (local_err) { goto out; } object_property_set_int(OBJECT(dev), slot, PC_DIMM_SLOT_PROP, &local_err); if (local_err) { goto out; } trace_mhp_pc_dimm_assigned_slot(slot); if (kvm_enabled() && !kvm_has_free_slot(machine)) { error_setg(&local_err, "hypervisor has no free memory slots left"); goto out; } if (!vhost_has_free_slot()) { error_setg(&local_err, "a used vhost backend has no free" " memory slots left"); goto out; } memory_region_add_subregion(&hpms->mr, addr - hpms->base, mr); vmstate_register_ram(vmstate_mr, dev); numa_set_mem_node_id(addr, memory_region_size(mr), dimm->node); out: error_propagate(errp, local_err); }
uint64_t pc_dimm_get_free_addr(uint64_t address_space_start, uint64_t address_space_size, uint64_t *hint, uint64_t align, uint64_t size, Error **errp) { GSList *list = NULL, *item; uint64_t new_addr, ret = 0; uint64_t address_space_end = address_space_start + address_space_size; g_assert(QEMU_ALIGN_UP(address_space_start, align) == address_space_start); if (!address_space_size) { error_setg(errp, "memory hotplug is not enabled, " "please add maxmem option"); goto out; } if (hint && QEMU_ALIGN_UP(*hint, align) != *hint) { error_setg(errp, "address must be aligned to 0x%" PRIx64 " bytes", align); goto out; } if (QEMU_ALIGN_UP(size, align) != size) { error_setg(errp, "backend memory size must be multiple of 0x%" PRIx64, align); goto out; } assert(address_space_end > address_space_start); object_child_foreach(qdev_get_machine(), pc_dimm_built_list, &list); if (hint) { new_addr = *hint; } else { new_addr = address_space_start; } /* find address range that will fit new DIMM */ for (item = list; item; item = g_slist_next(item)) { PCDIMMDevice *dimm = item->data; uint64_t dimm_size = object_property_get_uint(OBJECT(dimm), PC_DIMM_SIZE_PROP, errp); if (errp && *errp) { goto out; } if (ranges_overlap(dimm->addr, dimm_size, new_addr, size)) { if (hint) { DeviceState *d = DEVICE(dimm); error_setg(errp, "address range conflicts with '%s'", d->id); goto out; } new_addr = QEMU_ALIGN_UP(dimm->addr + dimm_size, align); } } ret = new_addr; if (new_addr < address_space_start) { error_setg(errp, "can't add memory [0x%" PRIx64 ":0x%" PRIx64 "] at 0x%" PRIx64, new_addr, size, address_space_start); } else if ((new_addr + size) > address_space_end) { error_setg(errp, "can't add memory [0x%" PRIx64 ":0x%" PRIx64 "] beyond 0x%" PRIx64, new_addr, size, address_space_end); } out: g_slist_free(list); return ret; }
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) { BCM2835PeripheralState *s = BCM2835_PERIPHERALS(dev); Object *obj; MemoryRegion *ram; Error *err = NULL; uint64_t ram_size, vcram_size; int n; obj = object_property_get_link(OBJECT(dev), "ram", &err); if (obj == NULL) { error_setg(errp, "%s: required ram link not found: %s", __func__, error_get_pretty(err)); return; } ram = MEMORY_REGION(obj); ram_size = memory_region_size(ram); /* Map peripherals and RAM into the GPU address space. */ memory_region_init_alias(&s->peri_mr_alias, OBJECT(s), "bcm2835-peripherals", &s->peri_mr, 0, memory_region_size(&s->peri_mr)); memory_region_add_subregion_overlap(&s->gpu_bus_mr, BCM2835_VC_PERI_BASE, &s->peri_mr_alias, 1); /* RAM is aliased four times (different cache configurations) on the GPU */ for (n = 0; n < 4; n++) { memory_region_init_alias(&s->ram_alias[n], OBJECT(s), "bcm2835-gpu-ram-alias[*]", ram, 0, ram_size); memory_region_add_subregion_overlap(&s->gpu_bus_mr, (hwaddr)n << 30, &s->ram_alias[n], 0); } /* Interrupt Controller */ object_property_set_bool(OBJECT(&s->ic), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->peri_mr, ARMCTRL_IC_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ic), 0)); sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic)); /* UART0 */ qdev_prop_set_chr(DEVICE(s->uart0), "chardev", serial_hds[0]); object_property_set_bool(OBJECT(s->uart0), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->peri_mr, UART0_OFFSET, sysbus_mmio_get_region(s->uart0, 0)); sysbus_connect_irq(s->uart0, 0, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_UART)); /* AUX / UART1 */ qdev_prop_set_chr(DEVICE(&s->aux), "chardev", serial_hds[1]); object_property_set_bool(OBJECT(&s->aux), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->peri_mr, UART1_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->aux), 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->aux), 0, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_AUX)); /* Mailboxes */ object_property_set_bool(OBJECT(&s->mboxes), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->peri_mr, ARMCTRL_0_SBM_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mboxes), 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->mboxes), 0, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_ARM_IRQ, INTERRUPT_ARM_MAILBOX)); /* Framebuffer */ vcram_size = object_property_get_uint(OBJECT(s), "vcram-size", &err); if (err) { error_propagate(errp, err); return; } object_property_set_uint(OBJECT(&s->fb), ram_size - vcram_size, "vcram-base", &err); if (err) { error_propagate(errp, err); return; } object_property_set_bool(OBJECT(&s->fb), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->mbox_mr, MBOX_CHAN_FB << MBOX_AS_CHAN_SHIFT, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->fb), 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->fb), 0, qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_FB)); /* Property channel */ object_property_set_bool(OBJECT(&s->property), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->mbox_mr, MBOX_CHAN_PROPERTY << MBOX_AS_CHAN_SHIFT, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->property), 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->property), 0, qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_PROPERTY)); /* Random Number Generator */ object_property_set_bool(OBJECT(&s->rng), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->peri_mr, RNG_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0)); /* Extended Mass Media Controller */ object_property_set_int(OBJECT(&s->sdhci), BCM2835_SDHC_CAPAREG, "capareg", &err); if (err) { error_propagate(errp, err); return; } object_property_set_bool(OBJECT(&s->sdhci), true, "pending-insert-quirk", &err); if (err) { error_propagate(errp, err); return; } object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->peri_mr, EMMC_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhci), 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_ARASANSDIO)); /* SDHOST */ object_property_set_bool(OBJECT(&s->sdhost), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->peri_mr, MMCI0_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhost), 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhost), 0, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_SDIO)); /* DMA Channels */ object_property_set_bool(OBJECT(&s->dma), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->peri_mr, DMA_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 0)); memory_region_add_subregion(&s->peri_mr, DMA15_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 1)); for (n = 0; n <= 12; n++) { sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), n, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_DMA0 + n)); } /* GPIO */ object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->peri_mr, GPIO_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0)); object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus", &err); if (err) { error_propagate(errp, err); return; } }
static void aspeed_board_init(MachineState *machine, const AspeedBoardConfig *cfg) { AspeedBoardState *bmc; AspeedSoCClass *sc; DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); ram_addr_t max_ram_size; bmc = g_new0(AspeedBoardState, 1); object_initialize(&bmc->soc, (sizeof(bmc->soc)), cfg->soc_name); object_property_add_child(OBJECT(machine), "soc", OBJECT(&bmc->soc), &error_abort); sc = ASPEED_SOC_GET_CLASS(&bmc->soc); object_property_set_uint(OBJECT(&bmc->soc), ram_size, "ram-size", &error_abort); object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1", &error_abort); object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs", &error_abort); if (machine->kernel_filename) { /* * When booting with a -kernel command line there is no u-boot * that runs to unlock the SCU. In this case set the default to * be unlocked as the kernel expects */ object_property_set_int(OBJECT(&bmc->soc), ASPEED_SCU_PROT_KEY, "hw-prot-key", &error_abort); } object_property_set_bool(OBJECT(&bmc->soc), true, "realized", &error_abort); /* * Allocate RAM after the memory controller has checked the size * was valid. If not, a default value is used. */ ram_size = object_property_get_uint(OBJECT(&bmc->soc), "ram-size", &error_abort); memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size); memory_region_add_subregion(get_system_memory(), sc->info->sdram_base, &bmc->ram); object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram), &error_abort); max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", &error_abort); memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, "max_ram", max_ram_size - ram_size); memory_region_add_subregion(get_system_memory(), sc->info->sdram_base + ram_size, &bmc->max_ram); aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort); aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort); /* Install first FMC flash content as a boot rom. */ if (drive0) { AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; MemoryRegion *boot_rom = g_new(MemoryRegion, 1); /* * create a ROM region using the default mapping window size of * the flash module. The window size is 64MB for the AST2400 * SoC and 128MB for the AST2500 SoC, which is twice as big as * needed by the flash modules of the Aspeed machines. */ memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom", fl->size, &error_abort); memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, boot_rom); write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); } aspeed_board_binfo.kernel_filename = machine->kernel_filename; aspeed_board_binfo.initrd_filename = machine->initrd_filename; aspeed_board_binfo.kernel_cmdline = machine->kernel_cmdline; aspeed_board_binfo.ram_size = ram_size; aspeed_board_binfo.loader_start = sc->info->sdram_base; if (cfg->i2c_init) { cfg->i2c_init(bmc); } arm_load_kernel(ARM_CPU(first_cpu), &aspeed_board_binfo); }
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) { BCM2835PeripheralState *s = BCM2835_PERIPHERALS(dev); Object *obj; MemoryRegion *ram; Error *err = NULL; uint64_t ram_size, vcram_size; int n; obj = object_property_get_link(OBJECT(dev), "ram", &err); if (obj == NULL) { error_setg(errp, "%s: required ram link not found: %s", __func__, error_get_pretty(err)); return; } ram = MEMORY_REGION(obj); ram_size = memory_region_size(ram); /* Map peripherals and RAM into the GPU address space. */ memory_region_init_alias(&s->peri_mr_alias, OBJECT(s), "bcm2835-peripherals", &s->peri_mr, 0, memory_region_size(&s->peri_mr)); memory_region_add_subregion_overlap(&s->gpu_bus_mr, BCM2835_VC_PERI_BASE, &s->peri_mr_alias, 1); /* RAM is aliased four times (different cache configurations) on the GPU */ for (n = 0; n < 4; n++) { memory_region_init_alias(&s->ram_alias[n], OBJECT(s), "bcm2835-gpu-ram-alias[*]", ram, 0, ram_size); memory_region_add_subregion_overlap(&s->gpu_bus_mr, (hwaddr)n << 30, &s->ram_alias[n], 0); } /* Interrupt Controller */ object_property_set_bool(OBJECT(&s->ic), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->peri_mr, ARMCTRL_IC_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ic), 0)); sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic)); /* UART0 */ qdev_prop_set_chr(DEVICE(s->uart0), "chardev", serial_hd(0)); object_property_set_bool(OBJECT(s->uart0), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->peri_mr, UART0_OFFSET, sysbus_mmio_get_region(s->uart0, 0)); sysbus_connect_irq(s->uart0, 0, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_UART)); /* AUX / UART1 */ qdev_prop_set_chr(DEVICE(&s->aux), "chardev", serial_hd(1)); object_property_set_bool(OBJECT(&s->aux), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->peri_mr, UART1_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->aux), 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->aux), 0, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_AUX)); /* System timer */ object_property_set_bool(OBJECT(&s->st), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->peri_mr, ST_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->st), 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->st), 0, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_TIMER0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->st), 1, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_TIMER1)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->st), 2, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_TIMER2)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->st), 3, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_TIMER3)); /* ARM timer */ object_property_set_bool(OBJECT(&s->timer), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->peri_mr, ARMCTRL_TIMER0_1_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer), 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_ARM_IRQ, INTERRUPT_ARM_TIMER)); /* USB controller */ object_property_set_bool(OBJECT(&s->usb), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->peri_mr, USB_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->usb), 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb), 0, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_USB)); /* MPHI - Message-based Parallel Host Interface */ object_property_set_bool(OBJECT(&s->mphi), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->peri_mr, MPHI_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mphi), 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->mphi), 0, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_HOSTPORT)); /* Mailboxes */ object_property_set_bool(OBJECT(&s->mboxes), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->peri_mr, ARMCTRL_0_SBM_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mboxes), 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->mboxes), 0, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_ARM_IRQ, INTERRUPT_ARM_MAILBOX)); /* Power management */ object_property_set_bool(OBJECT(&s->power), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->mbox_mr, MBOX_CHAN_POWER << MBOX_AS_CHAN_SHIFT, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->power), 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->power), 0, qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_POWER)); /* Framebuffer */ vcram_size = object_property_get_uint(OBJECT(s), "vcram-size", &err); if (err) { error_propagate(errp, err); return; } object_property_set_uint(OBJECT(&s->fb), ram_size - vcram_size, "vcram-base", &err); if (err) { error_propagate(errp, err); return; } object_property_set_bool(OBJECT(&s->fb), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->mbox_mr, MBOX_CHAN_FB << MBOX_AS_CHAN_SHIFT, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->fb), 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->fb), 0, qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_FB)); /* Property channel */ object_property_set_bool(OBJECT(&s->property), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->mbox_mr, MBOX_CHAN_PROPERTY << MBOX_AS_CHAN_SHIFT, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->property), 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->property), 0, qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_PROPERTY)); /* Random Number Generator */ object_property_set_bool(OBJECT(&s->rng), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->peri_mr, RNG_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0)); /* Extended Mass Media Controller * * Compatible with: * - SD Host Controller Specification Version 3.0 Draft 1.0 * - SDIO Specification Version 3.0 * - MMC Specification Version 4.4 * * For the exact details please refer to the Arasan documentation: * SD3.0_Host_AHB_eMMC4.4_Usersguide_ver5.9_jan11_10.pdf */ object_property_set_uint(OBJECT(&s->sdhci), 3, "sd-spec-version", &err); object_property_set_uint(OBJECT(&s->sdhci), BCM2835_SDHC_CAPAREG, "capareg", &err); object_property_set_bool(OBJECT(&s->sdhci), true, "pending-insert-quirk", &err); if (err) { error_propagate(errp, err); return; } object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->peri_mr, EMMC_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhci), 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_ARASANSDIO)); /* SDHOST */ object_property_set_bool(OBJECT(&s->sdhost), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->peri_mr, MMCI0_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhost), 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhost), 0, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_SDIO)); /* DMA Channels */ object_property_set_bool(OBJECT(&s->dma), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->peri_mr, DMA_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 0)); memory_region_add_subregion(&s->peri_mr, DMA15_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 1)); for (n = 0; n <= 12; n++) { sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), n, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_DMA0 + n)); } /* GPIO */ object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->peri_mr, GPIO_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0)); object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus", &err); if (err) { error_propagate(errp, err); return; } }