static void __init bcm2708_timer_init(void)
{
if (of_have_populated_dt()) {
of_clk_init(NULL);
clocksource_of_init();
return;
}
/* init high res timer */
bcm2708_clocksource_init();
/*
* Make irqs happen for the system timer
*/
setup_irq(IRQ_TIMER3, &bcm2708_timer_irq);
sched_clock_register(bcm2708_read_sched_clock, 32, STC_FREQ_HZ);
timer0_clockevent.mult =
div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift);
timer0_clockevent.max_delta_ns =
clockevent_delta2ns(0xffffffff, &timer0_clockevent);
timer0_clockevent.min_delta_ns =
clockevent_delta2ns(0xf, &timer0_clockevent);
timer0_clockevent.cpumask = cpumask_of(0);
clockevents_register_device(&timer0_clockevent);
register_current_timer_delay(&bcm2708_delay_timer);
}
int __init arch_board_early_init(void)
{
/* Host aspace, Heap, Device tree, and Host IRQ available.
*
* Do necessary early stuff like:
* iomapping devices,
* SOC clocking init,
* Setting-up system data in device tree nodes,
* ....
*/
/* Determine generic board matches from nodeid table */
generic_board_matches =
vmm_devtree_nidtbl_create_matches("generic_board");
/* Early init of generic boards with
* matching nodeid table enteries.
*/
if (generic_board_matches) {
vmm_devtree_iterate_matching(NULL,
generic_board_matches,
generic_board_early,
NULL);
}
/* Initialize clocking framework */
of_clk_init(NULL);
return VMM_OK;
}
void __init plat_time_init(void)
{
ralink_of_remap();
of_clk_init(NULL);
clocksource_probe();
}
static void __init sama5_dt_timer_init(void)
{
#if defined(CONFIG_COMMON_CLK)
of_clk_init(NULL);
#endif
at91sam926x_pit_init();
}
int __init omap_clk_init(void)
{
int ret = 0;
if (!omap_clk_soc_init)
return 0;
ti_clk_init_features();
omap2_clk_setup_ll_ops();
ret = omap_control_init();
if (ret)
return ret;
ret = omap_prcm_init();
if (ret)
return ret;
of_clk_init(NULL);
ti_dt_clk_init_retry_clks();
ti_dt_clockdomains_setup();
ret = omap_clk_soc_init();
return ret;
}
static void __init ath79_of_plat_time_init(void)
{
struct device_node *np;
struct clk *clk;
unsigned long cpu_clk_rate;
of_clk_init(NULL);
np = of_get_cpu_node(0, NULL);
if (!np) {
pr_err("Failed to get CPU node\n");
return;
}
clk = of_clk_get(np, 0);
if (IS_ERR(clk)) {
pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk));
return;
}
cpu_clk_rate = clk_get_rate(clk);
pr_info("CPU clock: %lu.%03lu MHz\n",
cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000);
mips_hpt_frequency = cpu_clk_rate / 2;
clk_put(clk);
}
int __init omap_clk_init(void)
{
int ret = 0;
if (!omap_clk_soc_init)
return 0;
ti_clk_init_features();
if (of_have_populated_dt()) {
ret = omap_control_init();
if (ret)
return ret;
ret = omap_prcm_init();
if (ret)
return ret;
of_clk_init(NULL);
ti_dt_clk_init_retry_clks();
ti_dt_clockdomains_setup();
}
ret = omap_clk_soc_init();
return ret;
}
static void __init v2m_dt_timer_init(void)
{
struct device_node *node = NULL;
of_clk_init(NULL);
do {
node = of_find_compatible_node(node, NULL, "arm,sp804");
} while (node && vexpress_get_site_by_node(node) != VEXPRESS_SITE_MB);
if (node) {
pr_info("Using SP804 '%s' as a clock & events source\n",
node->full_name);
WARN_ON(clk_register_clkdev(of_clk_get_by_name(node,
"timclken1"), "v2m-timer0", "sp804"));
WARN_ON(clk_register_clkdev(of_clk_get_by_name(node,
"timclken2"), "v2m-timer1", "sp804"));
v2m_sp804_init(of_iomap(node, 0),
irq_of_parse_and_map(node, 0));
}
if (arch_timer_of_register() != 0)
twd_local_timer_of_register();
if (arch_timer_sched_clock_init() != 0)
versatile_sched_clock_init(vexpress_get_24mhz_clock_base(),
24000000);
}
static void __init sun6i_timer_init(void)
{
of_clk_init(NULL);
if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
sun6i_reset_init();
clocksource_probe();
}
void __init vexpress_clk_of_init(void)
{
struct device_node *node;
struct clk *clk;
struct clk *refclk, *timclk;
of_clk_init(NULL);
node = of_find_compatible_node(NULL, NULL, "arm,sp810");
vexpress_sp810_init(of_iomap(node, 0));
of_clk_add_provider(node, vexpress_sp810_of_get, NULL);
/* Select "better" (faster) parent for SP804 timers */
refclk = of_clk_get_by_name(node, "refclk");
timclk = of_clk_get_by_name(node, "timclk");
if (!WARN_ON(IS_ERR(refclk) || IS_ERR(timclk))) {
int i = 0;
if (clk_get_rate(refclk) > clk_get_rate(timclk))
clk = refclk;
else
clk = timclk;
for (i = 0; i < ARRAY_SIZE(vexpress_sp810_timerclken); i++)
WARN_ON(clk_set_parent(vexpress_sp810_timerclken[i],
clk));
}
WARN_ON(clk_register_clkdev(vexpress_sp810_timerclken[0],
"v2m-timer0", "sp804"));
WARN_ON(clk_register_clkdev(vexpress_sp810_timerclken[1],
"v2m-timer1", "sp804"));
}
static void __init rk3036_dt_init_timer(void)
{
rockchip_pmu_ops.set_power_domain = rk3036_sys_set_power_domain;
rockchip_pmu_ops.power_domain_is_on = rk3036_pmu_power_domain_is_on;
rockchip_pmu_ops.set_idle_request = rk3036_pmu_set_idle_request;
of_clk_init(NULL);
clocksource_of_init();
}
static void __init mmp_init_time(void)
{
#ifdef CONFIG_CACHE_TAUROS2
tauros2_init(0);
#endif
mmp_dt_init_timer();
of_clk_init(NULL);
}
static void __init v2m_dt_timer_init(void)
{
of_clk_init(NULL);
clocksource_of_init();
versatile_sched_clock_init(vexpress_get_24mhz_clock_base(),
24000000);
}
void __init vtwm_clk_init(void __iomem *base)
{
if (!base)
return;
pmc_base = base;
of_clk_init(NULL);
}
static void __init emev2_add_standard_devices_dt(void)
{
#ifdef CONFIG_COMMON_CLK
of_clk_init(NULL);
#else
emev2_clock_init();
#endif
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static void __init ox820_timer_init(void)
{
of_clk_init(NULL);
#if LINUX_VERSION_CODE < KERNEL_VERSION(4,2,0)
clocksource_of_init();
#else
clocksource_probe();
#endif
}
static int __init sh_of_clk_init(void)
{
#ifdef CONFIG_COMMON_CLK
/* Disabled pending move to COMMON_CLK framework. */
pr_info("SH generic board support: scanning for clk providers\n");
of_clk_init(NULL);
#endif
return 0;
}
static void __init hisi_timer_init(void)
{
acore_timer_enable();
of_clk_init(NULL);
clocksource_of_init();
hisi_local_timer_register();
}
void __init sunxi_timer_init(void)
{
struct device_node *node;
unsigned long rate = 0;
struct clk *clk;
int ret, irq;
u32 val;
node = of_find_matching_node(NULL, sunxi_timer_dt_ids);
if (!node)
panic("No sunxi timer node");
timer_base = of_iomap(node, 0);
if (!timer_base)
panic("Can't map registers");
irq = irq_of_parse_and_map(node, 0);
if (irq <= 0)
panic("Can't parse IRQ");
of_clk_init(NULL);
clk = of_clk_get(node, 0);
if (IS_ERR(clk))
panic("Can't get timer clock");
rate = clk_get_rate(clk);
writel(rate / (TIMER_SCAL * HZ),
timer_base + TIMER0_INTVAL_REG);
/* set clock source to HOSC, 16 pre-division */
val = readl(timer_base + TIMER0_CTL_REG);
val &= ~(0x07 << 4);
val &= ~(0x03 << 2);
val |= (4 << 4) | (1 << 2);
writel(val, timer_base + TIMER0_CTL_REG);
/* set mode to auto reload */
val = readl(timer_base + TIMER0_CTL_REG);
writel(val | TIMER0_CTL_AUTORELOAD, timer_base + TIMER0_CTL_REG);
ret = setup_irq(irq, &sunxi_timer_irq);
if (ret)
pr_warn("failed to setup irq %d\n", irq);
/* Enable timer0 interrupt */
val = readl(timer_base + TIMER_CTL_REG);
writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG);
sunxi_clockevent.cpumask = cpumask_of(0);
clockevents_config_and_register(&sunxi_clockevent, rate / TIMER_SCAL,
0x1, 0xff);
}
void __init time_init(void)
{
if (machine_desc->init_time) {
machine_desc->init_time();
} else {
#ifdef CONFIG_COMMON_CLK
of_clk_init(NULL);
#endif
clocksource_of_init();
}
}
static void __init bcm2709_timer_init(void)
{
// timer control
writel(0, __io_address(ARM_LOCAL_CONTROL));
// timer pre_scaler
writel(0x80000000, __io_address(ARM_LOCAL_PRESCALER)); // 19.2MHz
//writel(0x06AAAAAB, __io_address(ARM_LOCAL_PRESCALER)); // 1MHz
of_clk_init(NULL);
clocksource_of_init();
}
void __init time_init(void)
{
if (machine_desc->init_time) {
machine_desc->init_time();
} else {
#ifdef CONFIG_COMMON_CLK
of_clk_init(NULL);
#endif
timer_probe();
}
}
void __init plat_time_init(void)
{
unsigned long rate = pic32_get_pbclk(7);
of_clk_init(NULL);
pr_info("CPU Clock: %ldMHz\n", rate / 1000000);
mips_hpt_frequency = rate / 2;
timer_probe();
}
static void sprd_init_time(void)
{
if(of_have_populated_dt()){
sc8830_pmu_init();
of_clk_init(NULL);
clocksource_of_init();
}else{
sci_clock_init();
sci_enable_timer_early();
sci_timer_init();
}
}
static void __init bcm2709_dt_init(void)
{
int ret;
of_clk_init(NULL);
ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
if (ret) {
pr_err("of_platform_populate failed: %d\n", ret);
/* Proceed as if CONFIG_OF was not defined */
} else {
use_dt = 1;
}
}
void __init time_init(void)
{
u32 arch_timer_rate;
of_clk_init(NULL);
clocksource_of_init();
arch_timer_rate = arch_timer_get_rate();
if (!arch_timer_rate)
panic("Unable to initialise architected timer.\n");
/* Calibrate the delay loop directly */
lpj_fine = arch_timer_rate / HZ;
}
static int __init customize_machine(void)
{
of_clk_init(NULL);
/*
* Traverses flattened DeviceTree - registering platform devices
* (if any) complete with their resources
*/
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
if (machine_desc->init_machine)
machine_desc->init_machine();
return 0;
}
void __init exynos_init_time(void)
{
if (of_have_populated_dt()) {
#ifdef CONFIG_OF
of_clk_init(NULL);
clocksource_of_init();
#endif
} else {
/* todo: remove after migrating legacy E4 platforms to dt */
#ifdef CONFIG_ARCH_EXYNOS4
exynos4_clk_init(NULL, !soc_is_exynos4210(), S5P_VA_CMU, readl(S5P_VA_CHIPID + 8) & 1);
exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
#endif
mct_init();
}
}
void __init time_init(void)
{
#ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT
printk("Calibrating CPU frequency ");
platform_calibrate_ccount();
printk("%d.%02d MHz\n", (int)ccount_freq/1000000,
(int)(ccount_freq/10000)%100);
#else
ccount_freq = CONFIG_XTENSA_CPU_CLOCK*1000000UL;
#endif
clocksource_register_hz(&ccount_clocksource, ccount_freq);
local_timer_setup(0);
setup_irq(this_cpu_ptr(&ccount_timer)->evt.irq, &timer_irqaction);
sched_clock_register(ccount_sched_clock_read, 32, ccount_freq);
of_clk_init(NULL);
clocksource_probe();
}
static void __init bcm2709_timer_init(void)
{
extern void dc4_arch_timer_init(void);
// timer control
writel(0, __io_address(ARM_LOCAL_CONTROL));
// timer pre_scaler
writel(0x80000000, __io_address(ARM_LOCAL_PRESCALER)); // 19.2MHz
//writel(0x06AAAAAB, __io_address(ARM_LOCAL_PRESCALER)); // 1MHz
if (use_dt)
{
of_clk_init(NULL);
clocksource_of_init();
}
else
dc4_arch_timer_init();
}