static int tpo_td043_probe_of(struct spi_device *spi)
{
struct device_node *node = spi->dev.of_node;
struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
struct omap_dss_device *in;
int gpio;
gpio = of_get_named_gpio(node, "reset-gpios", 0);
if (!gpio_is_valid(gpio)) {
dev_err(&spi->dev, "failed to parse enable gpio\n");
return gpio;
}
ddata->nreset_gpio = gpio;
in = omapdss_of_find_source_for_first_ep(node);
if (IS_ERR(in)) {
dev_err(&spi->dev, "failed to find video source\n");
return PTR_ERR(in);
}
ddata->in = in;
return 0;
}
static int hdmic_probe_of(struct platform_device *pdev)
{
struct panel_drv_data *ddata = platform_get_drvdata(pdev);
struct device_node *node = pdev->dev.of_node;
struct omap_dss_device *in;
int gpio;
/* HPD GPIO */
gpio = of_get_named_gpio(node, "hpd-gpios", 0);
if (gpio_is_valid(gpio))
ddata->hpd_gpio = gpio;
else
ddata->hpd_gpio = -ENODEV;
in = omapdss_of_find_source_for_first_ep(node);
if (IS_ERR(in)) {
dev_err(&pdev->dev, "failed to find video source\n");
return PTR_ERR(in);
}
ddata->in = in;
return 0;
}
static int of_max77888_dt(struct device *dev, struct max77888_platform_data *pdata)
{
struct device_node *np_max77888 = dev->of_node;
int ret;
if(!np_max77888)
return -EINVAL;
pdata->irq_gpio = of_get_named_gpio(np_max77888, "max77888,irq-gpio", 0);
pdata->wakeup = of_property_read_bool(np_max77888, "max77888,wakeup");
ret = of_property_read_u32(np_max77888, "max77888,irqf-trigger",
&pdata->irqf_trigger);
if (ret < 0) {
pr_err("%s: not found irqf_trigger(%d)\n", __func__, ret);
pdata->irqf_trigger = -1;
return ret;
}
pr_info("%s: irq-gpio: %u irqf-trigger:0x%08x)\n", __func__, pdata->irq_gpio,
pdata->irqf_trigger);
return 0;
}
static void aic31xx_pdata_from_of(struct aic31xx_priv *aic31xx)
{
struct device_node *np = aic31xx->dev->of_node;
unsigned int value = MICBIAS_2_0V;
int ret;
of_property_read_u32(np, "ai31xx-micbias-vg", &value);
switch (value) {
case MICBIAS_2_0V:
case MICBIAS_2_5V:
case MICBIAS_AVDDV:
aic31xx->pdata.micbias_vg = value;
break;
default:
dev_err(aic31xx->dev,
"Bad ai31xx-micbias-vg value %d DT\n",
value);
aic31xx->pdata.micbias_vg = MICBIAS_2_0V;
}
ret = of_get_named_gpio(np, "gpio-reset", 0);
if (ret > 0)
aic31xx->pdata.gpio_reset = ret;
}
static struct pixcir_ts_platform_data *pixcir_parse_dt(struct device *dev)
{
struct pixcir_ts_platform_data *pdata;
struct device_node *np = dev->of_node;
const struct of_device_id *match;
match = of_match_device(of_match_ptr(pixcir_of_match), dev);
if (!match)
return ERR_PTR(-EINVAL);
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return ERR_PTR(-ENOMEM);
pdata->chip = *(const struct pixcir_i2c_chip_data *)match->data;
pdata->gpio_attb = of_get_named_gpio(np, "attb-gpio", 0);
/* gpio_attb validity is checked in probe */
if (of_property_read_u32(np, "touchscreen-size-x", &pdata->x_max)) {
dev_err(dev, "Failed to get touchscreen-size-x property\n");
return ERR_PTR(-EINVAL);
}
pdata->x_max -= 1;
if (of_property_read_u32(np, "touchscreen-size-y", &pdata->y_max)) {
dev_err(dev, "Failed to get touchscreen-size-y property\n");
return ERR_PTR(-EINVAL);
}
pdata->y_max -= 1;
dev_dbg(dev, "%s: x %d, y %d, gpio %d\n", __func__,
pdata->x_max + 1, pdata->y_max + 1, pdata->gpio_attb);
return pdata;
}
/* Fail if any of the required gpios is absent. */
static int mdm_dt_parse_gpios(struct mdm_ctrl *mdm)
{
int i, val, rc = 0;
struct device_node *node = mdm->dev->of_node;
// enum of_gpio_flags flags = OF_GPIO_ACTIVE_LOW;
for (i = 0; i < NUM_GPIOS; i++)
mdm->gpios[i] = INVALID_GPIO;
for (i = 0; i < ARRAY_SIZE(gpio_map); i++) {
val = of_get_named_gpio(node, gpio_map[i].name, 0);
if (val >= 0) {
MDM_GPIO(mdm, gpio_map[i].index) = val;
pr_info("[MIF] %s, gpio : %s\n", __func__, gpio_map[i].name);
}
}
#if 0
/* These two are special because they can be inverted. */
val = of_get_named_gpio_flags(node, "qcom,ap2mdm-soft-reset-gpio",
0, &flags);
if (val >= 0) {
MDM_GPIO(mdm, AP2MDM_SOFT_RESET) = val;
if (flags & OF_GPIO_ACTIVE_LOW)
mdm->soft_reset_inverted = 1;
}
#endif
/* Verify that the required gpios have valid values */
for (i = 0; i < ARRAY_SIZE(required_gpios); i++) {
if (MDM_GPIO(mdm, required_gpios[i]) == INVALID_GPIO) {
rc = -ENXIO;
break;
}
}
mdm_debug_gpio_show(mdm);
return rc;
}
static int of_max77803_dt(struct device *dev, struct max77803_platform_data *pdata)
{
struct device_node *np = dev->of_node;
int retval = 0;
if(!np)
return -EINVAL;
pdata->irq_gpio = of_get_named_gpio_flags(np, "max77803,irq-gpio",
0, &pdata->irq_gpio_flags);
of_property_read_u32(np, "max77803,irq-base", &pdata->irq_base);
pdata->wakeup = of_property_read_bool(np, "max77803,wakeup");
retval = of_get_named_gpio(np, "max77803,wc-irq-gpio", 0);
if (retval < 0)
pdata->wc_irq_gpio = 0;
else
pdata->wc_irq_gpio = retval;
pr_info("%s: irq-gpio: %u \n", __func__, pdata->irq_gpio);
pr_info("%s: irq-base: %u \n", __func__, pdata->irq_base);
pr_info("%s: wc-irq-gpio: %u \n", __func__, pdata->wc_irq_gpio);
return 0;
}
static int fpc1020_request_named_gpio(struct fpc1020_data *fpc1020,
const char *label, int *gpio)
{
struct device *dev = fpc1020->dev;
struct device_node *np = dev->of_node;
int rc = 0;
rc = of_get_named_gpio(np, label, 0);
if (rc < 0) {
dev_err(dev, "failed to get '%s'\n", label);
return rc;
} else {
*gpio = rc;
}
rc = devm_gpio_request(dev, *gpio, label);
if (rc) {
dev_err(dev, "failed to request gpio %d\n", *gpio);
return rc;
}
dev_dbg(dev, "%s %d\n", label, *gpio);
return 0;
}
static int sensor_2p2_power_setpin(struct platform_device *pdev,
struct exynos_platform_fimc_is_module *pdata)
{
struct device *dev;
struct device_node *dnode;
int gpio_reset = 0;
int gpio_comp_rst = 0;
int gpio_mclk = 0;
int gpio_none = 0;
BUG_ON(!pdev);
dev = &pdev->dev;
dnode = dev->of_node;
dev_info(dev, "%s E v4\n", __func__);
gpio_comp_rst = of_get_named_gpio(dnode, "gpio_comp_reset", 0);
if (!gpio_is_valid(gpio_comp_rst)) {
dev_err(dev, "failed to get main comp reset gpio\n");
return -EINVAL;
} else {
gpio_request_one(gpio_comp_rst, GPIOF_OUT_INIT_LOW, "CAM_GPIO_OUTPUT_LOW");
gpio_free(gpio_comp_rst);
}
gpio_reset = of_get_named_gpio(dnode, "gpio_reset", 0);
if (!gpio_is_valid(gpio_reset)) {
dev_err(dev, "failed to get PIN_RESET\n");
return -EINVAL;
} else {
gpio_request_one(gpio_reset, GPIOF_OUT_INIT_LOW, "CAM_GPIO_OUTPUT_LOW");
gpio_free(gpio_reset);
}
gpio_mclk = of_get_named_gpio(dnode, "gpio_mclk", 0);
if (!gpio_is_valid(gpio_mclk)) {
dev_err(dev, "%s: failed to get mclk\n", __func__);
return -EINVAL;
} else {
if (gpio_request_one(gpio_mclk, GPIOF_OUT_INIT_LOW, "CAM_MCLK_OUTPUT_LOW")) {
dev_err(dev, "%s: failed to gpio request mclk\n", __func__);
return -ENODEV;
}
gpio_free(gpio_mclk);
}
SET_PIN_INIT(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON);
SET_PIN_INIT(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF);
#ifdef CONFIG_COMPANION_STANDBY_USE
SET_PIN_INIT(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_ENABLE);
SET_PIN_INIT(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_DISABLE);
#endif
SET_PIN_INIT(pdata, SENSOR_SCENARIO_VISION, GPIO_SCENARIO_ON);
SET_PIN_INIT(pdata, SENSOR_SCENARIO_VISION, GPIO_SCENARIO_OFF);
#ifdef CONFIG_OIS_USE
SET_PIN_INIT(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_ON);
SET_PIN_INIT(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_OFF);
#endif
/* Normal on */
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, gpio_reset, "sen_rst low", PIN_OUTPUT, 0, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, gpio_none, "VDDAF_2.8V_CAM", PIN_REGULATOR, 1, 2000);
SET_PIN_VOLTAGE(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, gpio_none, "VDDA_2.9V_CAM", PIN_REGULATOR, 1, 0, 2950000);
#ifdef CONFIG_OIS_USE
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, gpio_none, "OIS_VDD_2.8V", PIN_REGULATOR, 1, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, gpio_none, "OIS_VM_2.8V", PIN_REGULATOR, 1, 2500);
#endif
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, gpio_none, "VDDIO_1.8V_CAM", PIN_REGULATOR, 1, 0);
SET_PIN_VOLTAGE(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, gpio_none, "VDDD_1.2V_CAM", PIN_REGULATOR, 1, 0, 1200000);
SET_PIN_VOLTAGE(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, gpio_none, "VDDD_RET_1.0V_COMP", PIN_REGULATOR, 1, 0, 1000000);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, gpio_none, "VDDIO_1.8V_COMP", PIN_REGULATOR, 1, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, gpio_none, "VDDA_1.8V_COMP", PIN_REGULATOR, 1, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, gpio_none, "VDDD_CORE_1.0V_COMP", PIN_REGULATOR, 1, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, gpio_none, "VDDD_NORET_0.9V_COMP", PIN_REGULATOR, 1, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, gpio_none, "VDDD_CORE_0.8V_COMP", PIN_REGULATOR, 1, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, gpio_none, "pin", PIN_FUNCTION, 2, 2000);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, gpio_comp_rst, "comp_rst high", PIN_OUTPUT, 1, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, gpio_reset, "sen_rst high", PIN_OUTPUT, 1, 2000);
/* Normal off */
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, gpio_none, "VDDAF_2.8V_CAM", PIN_REGULATOR, 0, 1000);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, gpio_none, "pin", PIN_FUNCTION, 0, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, gpio_none, "pin", PIN_FUNCTION, 1, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, gpio_none, "pin", PIN_FUNCTION, 0, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, gpio_reset, "sen_rst", PIN_OUTPUT, 0, 15);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, gpio_comp_rst, "comp_rst low", PIN_OUTPUT, 0, 10);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, gpio_none, "VDDD_CORE_0.8V_COMP", PIN_REGULATOR, 0, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, gpio_none, "VDDD_NORET_0.9V_COMP", PIN_REGULATOR, 0, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, gpio_none, "VDDD_CORE_1.0V_COMP", PIN_REGULATOR, 0, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, gpio_none, "VDDA_1.8V_COMP", PIN_REGULATOR, 0, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, gpio_none, "VDDIO_1.8V_COMP", PIN_REGULATOR, 0, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, gpio_none, "VDDD_RET_1.0V_COMP", PIN_REGULATOR, 0, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, gpio_none, "VDDA_2.9V_CAM", PIN_REGULATOR, 0, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, gpio_none, "VDDD_1.2V_CAM", PIN_REGULATOR, 0, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, gpio_none, "VDDIO_1.8V_CAM", PIN_REGULATOR, 0, 0);
#ifdef CONFIG_OIS_USE
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, gpio_none, "OIS_VDD_2.8V", PIN_REGULATOR, 0, 2000);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, gpio_none, "OIS_VM_2.8V", PIN_REGULATOR, 0, 0);
#endif
#ifdef CONFIG_COMPANION_STANDBY_USE
/* STANDBY DISABLE */
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_DISABLE, gpio_reset, "sen_rst low", PIN_OUTPUT, 0, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_DISABLE, gpio_none, "VDDAF_2.8V_CAM", PIN_REGULATOR, 1, 2000);
SET_PIN_VOLTAGE(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_DISABLE, gpio_none, "VDDA_2.9V_CAM", PIN_REGULATOR, 1, 0, 2950000);
#ifdef CONFIG_OIS_USE
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_DISABLE, gpio_none, "OIS_VDD_2.8V", PIN_REGULATOR, 1, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_DISABLE, gpio_none, "OIS_VM_2.8V", PIN_REGULATOR, 1, 2500);
#endif
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_DISABLE, gpio_none, "VDDIO_1.8V_CAM", PIN_REGULATOR, 1, 0);
SET_PIN_VOLTAGE(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_DISABLE, gpio_none, "VDDD_1.2V_CAM", PIN_REGULATOR, 1, 0, 1200000);
SET_PIN_VOLTAGE(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_DISABLE, gpio_none, "VDDD_RET_1.0V_COMP", PIN_REGULATOR, 1, 0, 1000000);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_DISABLE, gpio_none, "VDDA_1.8V_COMP", PIN_REGULATOR, 1, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_DISABLE, gpio_none, "VDDD_CORE_1.0V_COMP", PIN_REGULATOR, 1, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_DISABLE, gpio_none, "VDDD_NORET_0.9V_COMP", PIN_REGULATOR, 1, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_DISABLE, gpio_none, "VDDD_CORE_0.8V_COMP", PIN_REGULATOR, 1, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_DISABLE, gpio_none, "pin", PIN_FUNCTION, 2, 2000);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_DISABLE, gpio_comp_rst, "comp_rst high", PIN_OUTPUT, 1, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_DISABLE, gpio_reset, "sen_rst high", PIN_OUTPUT, 1, 2000);
/* STANDBY ENABLE */
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_ENABLE, gpio_none, "VDDAF_2.8V_CAM", PIN_REGULATOR, 0, 1000);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_ENABLE, gpio_none, "pin", PIN_FUNCTION, 0, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_ENABLE, gpio_none, "pin", PIN_FUNCTION, 1, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_ENABLE, gpio_none, "pin", PIN_FUNCTION, 0, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_ENABLE, gpio_reset, "sen_rst", PIN_OUTPUT, 0, 15);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_ENABLE, gpio_comp_rst, "comp_rst low", PIN_OUTPUT, 0, 10);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_ENABLE, gpio_none, "VDDD_CORE_0.8V_COMP", PIN_REGULATOR, 0, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_ENABLE, gpio_none, "VDDD_NORET_0.9V_COMP", PIN_REGULATOR, 0, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_ENABLE, gpio_none, "VDDD_CORE_1.0V_COMP", PIN_REGULATOR, 0, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_ENABLE, gpio_none, "VDDA_1.8V_COMP", PIN_REGULATOR, 0, 1000);
SET_PIN_VOLTAGE(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_ENABLE, gpio_none, "VDDD_RET_1.0V_COMP", PIN_REGULATOR, 1, 0, 700000);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_ENABLE, gpio_none, "VDDA_2.9V_CAM", PIN_REGULATOR, 0, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_ENABLE, gpio_none, "VDDD_1.2V_CAM", PIN_REGULATOR, 0, 0);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_ENABLE, gpio_none, "VDDIO_1.8V_CAM", PIN_REGULATOR, 0, 0);
#ifdef CONFIG_OIS_USE
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_ENABLE, gpio_none, "OIS_VDD_2.8V", PIN_REGULATOR, 0, 2000);
SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_STANDBY_ENABLE, gpio_none, "OIS_VM_2.8V", PIN_REGULATOR, 0, 0);
#endif
#endif
#ifdef CONFIG_OIS_USE
/* OIS_FACTORY - POWER ON */
SET_PIN(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_ON, gpio_none, "VDDAF_2.8V_CAM", PIN_REGULATOR, 1, 0);
SET_PIN(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_ON, gpio_none, "OIS_VDD_2.8V", PIN_REGULATOR, 1, 0);
SET_PIN(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_ON, gpio_none, "OIS_VM_2.8V", PIN_REGULATOR, 1, 2500);
SET_PIN(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_ON, gpio_none, "VDDIO_1.8V_CAM", PIN_REGULATOR, 1, 0);
SET_PIN(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_ON, gpio_reset, "sen_rst high", PIN_OUTPUT, 1, 0);
/* OIS_FACTORY - POWER OFF */
SET_PIN(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_OFF, gpio_reset, "sen_rst low", PIN_OUTPUT, 0, 0);
SET_PIN(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_OFF, gpio_none, "VDDIO_1.8V_CAM", PIN_REGULATOR, 0, 0);
SET_PIN(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_OFF, gpio_none, "OIS_VDD_2.8V", PIN_REGULATOR, 0, 2000);
SET_PIN(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_OFF, gpio_none, "OIS_VM_2.8V", PIN_REGULATOR, 0, 0);
SET_PIN(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_OFF, gpio_none, "VDDAF_2.8V_CAM", PIN_REGULATOR, 0, 0);
#endif
dev_info(dev, "%s X v4\n", __func__);
return 0;
}
static int __devinit spi_sirfsoc_probe(struct platform_device *pdev)
{
struct sirfsoc_spi *sspi;
struct spi_master *master;
struct resource *mem_res;
int num_cs, cs_gpio, irq;
int i;
int ret;
ret = of_property_read_u32(pdev->dev.of_node,
"sirf,spi-num-chipselects", &num_cs);
if (ret < 0) {
dev_err(&pdev->dev, "Unable to get chip select number\n");
goto err_cs;
}
master = spi_alloc_master(&pdev->dev, sizeof(*sspi) + sizeof(int) * num_cs);
if (!master) {
dev_err(&pdev->dev, "Unable to allocate SPI master\n");
return -ENOMEM;
}
platform_set_drvdata(pdev, master);
sspi = spi_master_get_devdata(master);
mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!mem_res) {
dev_err(&pdev->dev, "Unable to get IO resource\n");
ret = -ENODEV;
goto free_master;
}
master->num_chipselect = num_cs;
for (i = 0; i < master->num_chipselect; i++) {
cs_gpio = of_get_named_gpio(pdev->dev.of_node, "cs-gpios", i);
if (cs_gpio < 0) {
dev_err(&pdev->dev, "can't get cs gpio from DT\n");
ret = -ENODEV;
goto free_master;
}
sspi->chipselect[i] = cs_gpio;
if (cs_gpio == 0)
continue; /* use cs from spi controller */
ret = gpio_request(cs_gpio, DRIVER_NAME);
if (ret) {
while (i > 0) {
i--;
if (sspi->chipselect[i] > 0)
gpio_free(sspi->chipselect[i]);
}
dev_err(&pdev->dev, "fail to request cs gpios\n");
goto free_master;
}
}
sspi->base = devm_ioremap_resource(&pdev->dev, mem_res);
if (IS_ERR(sspi->base)) {
ret = PTR_ERR(sspi->base);
goto free_master;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
ret = -ENXIO;
goto free_master;
}
ret = devm_request_irq(&pdev->dev, irq, spi_sirfsoc_irq, 0,
DRIVER_NAME, sspi);
if (ret)
goto free_master;
sspi->bitbang.master = spi_master_get(master);
sspi->bitbang.chipselect = spi_sirfsoc_chipselect;
sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer;
sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer;
sspi->bitbang.master->setup = spi_sirfsoc_setup;
master->bus_num = pdev->id;
sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
sspi->p = pinctrl_get_select_default(&pdev->dev);
ret = IS_ERR(sspi->p);
if (ret)
goto free_master;
sspi->clk = clk_get(&pdev->dev, NULL);
if (IS_ERR(sspi->clk)) {
ret = -EINVAL;
goto free_pin;
}
clk_prepare_enable(sspi->clk);
sspi->ctrl_freq = clk_get_rate(sspi->clk);
init_completion(&sspi->done);
tasklet_init(&sspi->tasklet_tx, spi_sirfsoc_tasklet_tx,
(unsigned long)sspi);
writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
/* We are not using dummy delay between command and data */
writel(0, sspi->base + SIRFSOC_SPI_DUMMY_DELAY_CTL);
ret = spi_bitbang_start(&sspi->bitbang);
if (ret)
goto free_clk;
dev_info(&pdev->dev, "registerred, bus number = %d\n", master->bus_num);
return 0;
free_clk:
clk_disable_unprepare(sspi->clk);
clk_put(sspi->clk);
free_pin:
pinctrl_put(sspi->p);
free_master:
spi_master_put(master);
err_cs:
return ret;
}
static int spi_imx_probe(struct vmm_device *dev,
const struct vmm_devtree_nodeid *devid)
{
virtual_addr_t vaddr = 0;
struct spi_master *master;
struct spi_imx_data *spi_imx;
int i;
int ret = VMM_OK;
u32 num_cs;
if (!vmm_devtree_is_available(dev->of_node)) {
dev_info(dev, "device is disabled\n");
return ret;
}
ret = vmm_devtree_read_u32(dev->of_node, "fsl,spi-num-chipselects",
&num_cs);
if (ret < 0) {
return ret;
}
master = spi_alloc_master(dev, sizeof(struct spi_imx_data) +
sizeof(int) * num_cs);
if (!master) {
dev_err(dev, "cannot allocate master\n");
return -ENOMEM;
}
vmm_devdrv_set_data(dev, master);
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
master->num_chipselect = num_cs;
spi_imx = spi_master_get_devdata(master);
spi_imx->bitbang.master = master;
for (i = 0; i < master->num_chipselect; i++) {
int cs_gpio = of_get_named_gpio(dev->of_node, "cs-gpios", i);
spi_imx->chipselect[i] = cs_gpio;
if (!gpio_is_valid(cs_gpio))
continue;
ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME);
if (ret) {
dev_err(dev, "can't get cs gpios\n");
goto out_gpio_free;
}
}
spi_imx->bitbang.chipselect = spi_imx_chipselect;
spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
spi_imx->bitbang.master->setup = spi_imx_setup;
spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
init_completion(&spi_imx->xfer_done);
spi_imx->devtype_data = devid->data;
ret = vmm_devtree_request_regmap(dev->of_node, &vaddr, 0, "i.MX SPI");
if (VMM_OK != ret) {
ret = PTR_ERR(spi_imx->base);
goto out_gpio_free;
}
spi_imx->base = (void __iomem *)vaddr;
master->bus_num = vmm_devtree_alias_get_id(dev->of_node, "spi");
if (0 > master->bus_num) {
ret = master->bus_num;
goto out_gpio_free;
}
spi_imx->irq = vmm_devtree_irq_parse_map(dev->of_node, 0);
if (!spi_imx->irq) {
ret = VMM_ENODEV;
goto out_gpio_free;
}
ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx);
if (VMM_OK != ret) {
dev_err(dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
goto out_gpio_free;
}
spi_imx->clk_ipg = clk_get(dev, "ipg");
if (IS_ERR(spi_imx->clk_ipg)) {
ret = PTR_ERR(spi_imx->clk_ipg);
goto out_gpio_free;
}
spi_imx->clk_per = clk_get(dev, "per");
if (IS_ERR(spi_imx->clk_per)) {
ret = PTR_ERR(spi_imx->clk_per);
goto out_gpio_free;
}
ret = clk_prepare_enable(spi_imx->clk_per);
if (ret)
goto out_gpio_free;
ret = clk_prepare_enable(spi_imx->clk_ipg);
if (ret)
goto out_put_per;
spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
spi_imx->devtype_data->reset(spi_imx);
spi_imx->devtype_data->intctrl(spi_imx, 0);
master->dev.of_node = dev->of_node;
ret = spi_bitbang_start(&spi_imx->bitbang);
if (ret) {
dev_err(dev, "bitbang start failed with %d\n", ret);
goto out_clk_put;
}
/* FIXME: This should not disable the clock, as they are still set as
used by the UART */
#if 0
clk_disable(spi_imx->clk_ipg);
clk_disable(spi_imx->clk_per);
#endif
return ret;
out_clk_put:
/* FIXME: This should not disable the clock, as they are still set as
used by the UART */
#if 0
clk_disable_unprepare(spi_imx->clk_ipg);
#endif
out_put_per:
/* FIXME: This should not disable the clock, as they are still set as
used by the UART */
#if 0
clk_disable_unprepare(spi_imx->clk_per);
#endif
out_gpio_free:
while (i-- > 0) {
gpio_free(spi_imx->chipselect[i]);
}
spi_master_put(master);
dev_err(dev, "probing failed\n");
return ret;
}
static int cptk_probe_dt(struct device_node *np, struct device *dev, struct cptk_platform_data *pdata) {
const struct of_device_id *match;
static int* tk_keymap = NULL;
if (!np) {
dev_err(dev, "%s: device node is NULL\n", __func__);
return -EINVAL;
}
match = of_match_device(cptk_dt_ids, dev);
if (!match) {
dev_err(dev, "%s: compatible mismatch\n", __func__);
return -EINVAL;
}
pdata->gpio = of_get_named_gpio(np, "cypress,gpio_int", 0);
if (pdata->gpio < 0) {
dev_err(dev, "%s: error in reading gpio for irq\n", __func__);
return pdata->gpio;
}
pdata->en_pin = of_get_named_gpio(np, "cypress,gpio_ldo_en", 0);
if (pdata->en_pin < 0) {
dev_err(dev, "%s: error in reading gpio for enabling ldo\n", __func__);
goto error;
}
if (of_property_read_u32(np, "cypress,mod_ver", &pdata->mod_ver)) {
dev_err(dev, "%s: error reading property cypress,mod_ver\n", __func__);
goto error;
}
if (of_property_read_u32(np, "cypress,firm_ver", &pdata->firm_ver)) {
dev_err(dev, "%s: error reading property cypress,firm_ver\n", __func__);
goto error;
}
if (of_property_read_u32(np, "cypress,tk_keymap_size", &pdata->keymap_size)) {
dev_err(dev, "%s: error reading property cypress,keymap size\n", __func__);
goto error;
}
tk_keymap = devm_kzalloc(dev, sizeof(unsigned int) * pdata->keymap_size, GFP_KERNEL);
if (of_property_read_u32_array(np, "cypress,tk_keymap", tk_keymap, pdata->keymap_size)) {
dev_err(dev, "%s: error reading property cypress,keymap\n", __func__);
goto error1;
}
pdata->keymap = tk_keymap;
if (of_property_read_string(np, "cypress,fw_name", &pdata->fw_name)) {
dev_err(dev, "%s: error reading property cypress,fw_name\n", __func__);
goto error1;
}
pdata->power = &tk_power_on;
return 0;
error1:
if(pdata->keymap)
devm_kfree(dev, (void *)pdata->keymap);
error:
return -EINVAL;
}
static int __init exynos_pcie_probe(struct platform_device *pdev)
{
struct exynos_pcie *exynos_pcie;
struct pcie_port *pp;
struct device_node *np = pdev->dev.of_node;
struct resource *elbi_base;
struct resource *phy_base;
struct resource *block_base;
struct resource *pmu_base;
int ret;
exynos_pcie = devm_kzalloc(&pdev->dev, sizeof(*exynos_pcie),
GFP_KERNEL);
if (!exynos_pcie) {
dev_err(&pdev->dev, "no memory for exynos pcie\n");
return -ENOMEM;
}
pp = &exynos_pcie->pp;
pp->dev = &pdev->dev;
exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
exynos_pcie->clk = devm_clk_get(&pdev->dev, "pcie");
if (IS_ERR(exynos_pcie->clk)) {
dev_err(&pdev->dev, "Failed to get pcie rc clock\n");
return PTR_ERR(exynos_pcie->clk);
}
ret = clk_prepare_enable(exynos_pcie->clk);
if (ret)
return ret;
elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
exynos_pcie->elbi_base = devm_ioremap_resource(&pdev->dev, elbi_base);
if (IS_ERR(exynos_pcie->elbi_base))
return PTR_ERR(exynos_pcie->elbi_base);
phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1);
exynos_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy_base);
if (IS_ERR(exynos_pcie->phy_base))
return PTR_ERR(exynos_pcie->phy_base);
block_base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
exynos_pcie->block_base = devm_ioremap_resource(&pdev->dev, block_base);
if (IS_ERR(exynos_pcie->block_base))
return PTR_ERR(exynos_pcie->block_base);
pmu_base = platform_get_resource(pdev, IORESOURCE_MEM, 3);
exynos_pcie->pmu_base = devm_ioremap_resource(&pdev->dev, pmu_base);
if (IS_ERR(exynos_pcie->pmu_base))
return PTR_ERR(exynos_pcie->pmu_base);
ret = add_pcie_port(pp, pdev);
if (ret > 0)
goto fail_bus_clk;
platform_set_drvdata(pdev, exynos_pcie);
return 0;
fail_bus_clk:
clk_disable_unprepare(exynos_pcie->bus_clk);
//fail_clk:
// clk_disable_unprepare(exynos_pcie->clk);
return ret;
}
static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
{
struct exynos_dp_device *dp = dev_get_drvdata(dev);
struct platform_device *pdev = to_platform_device(dev);
struct drm_device *drm_dev = data;
struct resource *res;
unsigned int irq_flags;
int ret = 0;
dp->dev = &pdev->dev;
dp->dpms_mode = DRM_MODE_DPMS_OFF;
dp->video_info = exynos_dp_dt_parse_pdata(&pdev->dev);
if (IS_ERR(dp->video_info))
return PTR_ERR(dp->video_info);
dp->phy = devm_phy_get(dp->dev, "dp");
if (IS_ERR(dp->phy)) {
dev_err(dp->dev, "no DP phy configured\n");
ret = PTR_ERR(dp->phy);
if (ret) {
/*
* phy itself is not enabled, so we can move forward
* assigning NULL to phy pointer.
*/
if (ret == -ENOSYS || ret == -ENODEV)
dp->phy = NULL;
else
return ret;
}
}
if (!dp->panel) {
ret = exynos_dp_dt_parse_panel(dp);
if (ret)
return ret;
}
dp->clock = devm_clk_get(&pdev->dev, "dp");
if (IS_ERR(dp->clock)) {
dev_err(&pdev->dev, "failed to get clock\n");
return PTR_ERR(dp->clock);
}
clk_prepare_enable(dp->clock);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(dp->reg_base))
return PTR_ERR(dp->reg_base);
dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0);
if (gpio_is_valid(dp->hpd_gpio)) {
/*
* Set up the hotplug GPIO from the device tree as an interrupt.
* Simply specifying a different interrupt in the device tree
* doesn't work since we handle hotplug rather differently when
* using a GPIO. We also need the actual GPIO specifier so
* that we can get the current state of the GPIO.
*/
ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN,
"hpd_gpio");
if (ret) {
dev_err(&pdev->dev, "failed to get hpd gpio\n");
return ret;
}
dp->irq = gpio_to_irq(dp->hpd_gpio);
irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
} else {
dp->hpd_gpio = -ENODEV;
dp->irq = platform_get_irq(pdev, 0);
irq_flags = 0;
}
if (dp->irq == -ENXIO) {
dev_err(&pdev->dev, "failed to get irq\n");
return -ENODEV;
}
INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
exynos_dp_phy_init(dp);
exynos_dp_init_dp(dp);
ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,
irq_flags, "exynos-dp", dp);
if (ret) {
dev_err(&pdev->dev, "failed to request irq\n");
return ret;
}
disable_irq(dp->irq);
dp->drm_dev = drm_dev;
return exynos_drm_create_enc_conn(drm_dev, &dp->display);
}
static int mdss_panel_parse_dt(struct device_node *np,
struct mdss_dsi_ctrl_pdata *ctrl_pdata)
{
u32 tmp;
int rc, i, len;
const char *data;
static const char *pdest;
struct mdss_panel_info *pinfo = &(ctrl_pdata->panel_data.panel_info);
rc = of_property_read_u32(np, "qcom,mdss-dsi-panel-width", &tmp);
if (rc) {
pr_err("%s:%d, panel width not specified\n",
__func__, __LINE__);
return -EINVAL;
}
pinfo->xres = (!rc ? tmp : 640);
rc = of_property_read_u32(np, "qcom,mdss-dsi-panel-height", &tmp);
if (rc) {
pr_err("%s:%d, panel height not specified\n",
__func__, __LINE__);
return -EINVAL;
}
pinfo->yres = (!rc ? tmp : 480);
rc = of_property_read_u32(np,
"qcom,mdss-pan-physical-width-dimension", &tmp);
pinfo->physical_width = (!rc ? tmp : 0);
rc = of_property_read_u32(np,
"qcom,mdss-pan-physical-height-dimension", &tmp);
pinfo->physical_height = (!rc ? tmp : 0);
rc = of_property_read_u32(np, "qcom,mdss-dsi-h-left-border", &tmp);
pinfo->lcdc.xres_pad = (!rc ? tmp : 0);
rc = of_property_read_u32(np, "qcom,mdss-dsi-h-right-border", &tmp);
if (!rc)
pinfo->lcdc.xres_pad += tmp;
rc = of_property_read_u32(np, "qcom,mdss-dsi-v-top-border", &tmp);
pinfo->lcdc.yres_pad = (!rc ? tmp : 0);
rc = of_property_read_u32(np, "qcom,mdss-dsi-v-bottom-border", &tmp);
if (!rc)
pinfo->lcdc.yres_pad += tmp;
rc = of_property_read_u32(np, "qcom,mdss-dsi-bpp", &tmp);
if (rc) {
pr_err("%s:%d, bpp not specified\n", __func__, __LINE__);
return -EINVAL;
}
pinfo->bpp = (!rc ? tmp : 24);
pinfo->mipi.mode = DSI_VIDEO_MODE;
data = of_get_property(np, "qcom,mdss-dsi-panel-type", NULL);
if (data && !strncmp(data, "dsi_cmd_mode", 12))
pinfo->mipi.mode = DSI_CMD_MODE;
rc = of_property_read_u32(np, "qcom,mdss-dsi-pixel-packing", &tmp);
tmp = (!rc ? tmp : 0);
rc = mdss_panel_dt_get_dst_fmt(pinfo->bpp,
pinfo->mipi.mode, tmp,
&(pinfo->mipi.dst_format));
if (rc) {
pr_debug("%s: problem determining dst format. Set Default\n",
__func__);
pinfo->mipi.dst_format =
DSI_VIDEO_DST_FORMAT_RGB888;
}
pdest = of_get_property(np,
"qcom,mdss-dsi-panel-destination", NULL);
if (strlen(pdest) != 9) {
pr_err("%s: Unknown pdest specified\n", __func__);
return -EINVAL;
}
if (!strncmp(pdest, "display_1", 9))
pinfo->pdest = DISPLAY_1;
else if (!strncmp(pdest, "display_2", 9))
pinfo->pdest = DISPLAY_2;
else {
pr_debug("%s: pdest not specified. Set Default\n",
__func__);
pinfo->pdest = DISPLAY_1;
}
rc = of_property_read_u32(np, "qcom,mdss-dsi-h-front-porch", &tmp);
pinfo->lcdc.h_front_porch = (!rc ? tmp : 6);
rc = of_property_read_u32(np, "qcom,mdss-dsi-h-back-porch", &tmp);
pinfo->lcdc.h_back_porch = (!rc ? tmp : 6);
rc = of_property_read_u32(np, "qcom,mdss-dsi-h-pulse-width", &tmp);
pinfo->lcdc.h_pulse_width = (!rc ? tmp : 2);
rc = of_property_read_u32(np, "qcom,mdss-dsi-h-sync-skew", &tmp);
pinfo->lcdc.hsync_skew = (!rc ? tmp : 0);
rc = of_property_read_u32(np, "qcom,mdss-dsi-v-back-porch", &tmp);
pinfo->lcdc.v_back_porch = (!rc ? tmp : 6);
rc = of_property_read_u32(np, "qcom,mdss-dsi-v-front-porch", &tmp);
pinfo->lcdc.v_front_porch = (!rc ? tmp : 6);
rc = of_property_read_u32(np, "qcom,mdss-dsi-v-pulse-width", &tmp);
pinfo->lcdc.v_pulse_width = (!rc ? tmp : 2);
rc = of_property_read_u32(np,
"qcom,mdss-dsi-underflow-color", &tmp);
pinfo->lcdc.underflow_clr = (!rc ? tmp : 0xff);
rc = of_property_read_u32(np,
"qcom,mdss-dsi-border-color", &tmp);
pinfo->lcdc.border_clr = (!rc ? tmp : 0);
pinfo->bklt_ctrl = UNKNOWN_CTRL;
data = of_get_property(np, "qcom,mdss-dsi-bl-pmic-control-type", NULL);
if (data) {
if (!strncmp(data, "bl_ctrl_wled", 12)) {
led_trigger_register_simple("bkl-trigger",
&bl_led_trigger);
pr_debug("%s: SUCCESS-> WLED TRIGGER register\n",
__func__);
ctrl_pdata->bklt_ctrl = BL_WLED;
} else if (!strncmp(data, "bl_ctrl_pwm", 11)) {
ctrl_pdata->bklt_ctrl = BL_PWM;
#ifdef EXPRESSWIRED
spin_lock(&bl_ctrl_lock);
gpio_set_value(GPIO_BL_CTRL, 0);
udelay(1500);
udelay(1500);
gpio_set_value(GPIO_BL_CTRL, 1);
udelay(200);
gpio_set_value(GPIO_BL_CTRL, 0);
udelay(300);
gpio_set_value(GPIO_BL_CTRL, 1);
udelay(400);
spin_unlock(&bl_ctrl_lock);
#endif
#if !defined(CONFIG_BACKLIGHT_IC_KTD2801)
rc = of_property_read_u32(np,
"qcom,mdss-dsi-bl-pmic-pwm-frequency", &tmp);
if (rc) {
pr_err("%s:%d, Error, panel pwm_period\n",
__func__, __LINE__);
return -EINVAL;
}
ctrl_pdata->pwm_period = tmp;
rc = of_property_read_u32(np,
"qcom,mdss-dsi-bl-pmic-bank-select", &tmp);
if (rc) {
pr_err("%s:%d, Error, dsi lpg channel\n",
__func__, __LINE__);
return -EINVAL;
}
ctrl_pdata->pwm_lpg_chan = tmp;
tmp = of_get_named_gpio(np,
"qcom,mdss-dsi-pwm-gpio", 0);
ctrl_pdata->pwm_pmic_gpio = tmp;
#endif
#if defined(CONFIG_BACKLIGHT_IC_KTD2801)
#ifndef EXPRESSWIRED
msd.bl_ap_pwm= of_get_named_gpio(np,
"qcom,bl-wled", 0);
if (!gpio_is_valid(msd.bl_ap_pwm)) {
pr_err("%s:%d, bl_ap_pwm gpio not specified\n",
__func__, __LINE__);
} else {
rc = gpio_request(msd.bl_ap_pwm, "bl_ap_pwm");
if (rc) {
pr_err("request bl_ap_pwm gpio failed, rc=%d\n",rc);
gpio_free(msd.bl_ap_pwm);
}else{
rc = gpio_tlmm_config(GPIO_CFG(msd.bl_ap_pwm, 0,
GPIO_CFG_OUTPUT,GPIO_CFG_NO_PULL,GPIO_CFG_8MA),GPIO_CFG_ENABLE);
if (rc)
pr_err("request bl_ap_pwm failed, rc=%d\n",rc);
}
}
#endif
#endif
} else if (!strncmp(data, "bl_ctrl_dcs", 11)) {
ctrl_pdata->bklt_ctrl = BL_DCS_CMD;
}
#if defined(CONFIG_BACKLIGHT_IC_KTD253)
else if (!strncmp(data, "bl_ctrl_gpio_swing", 18)) {
ctrl_pdata->bklt_ctrl = BL_GPIO_SWING;
}
#endif
}
rc = of_property_read_u32(np, "qcom,mdss-brightness-max-level", &tmp);
pinfo->brightness_max = (!rc ? tmp : MDSS_MAX_BL_BRIGHTNESS);
rc = of_property_read_u32(np, "qcom,mdss-dsi-bl-min-level", &tmp);
pinfo->bl_min = (!rc ? tmp : 0);
rc = of_property_read_u32(np, "qcom,mdss-dsi-bl-max-level", &tmp);
pinfo->bl_max = (!rc ? tmp : 255);
ctrl_pdata->bklt_max = pinfo->bl_max;
rc = of_property_read_u32(np, "qcom,mdss-dsi-interleave-mode", &tmp);
pinfo->mipi.interleave_mode = (!rc ? tmp : 0);
pinfo->mipi.vsync_enable = of_property_read_bool(np,
"qcom,mdss-dsi-te-check-enable");
pinfo->mipi.hw_vsync_mode = of_property_read_bool(np,
"qcom,mdss-dsi-te-using-te-pin");
rc = of_property_read_u32(np,
"qcom,mdss-dsi-h-sync-pulse", &tmp);
pinfo->mipi.pulse_mode_hsa_he = (!rc ? tmp : false);
pinfo->mipi.hfp_power_stop = of_property_read_bool(np,
"qcom,mdss-dsi-hfp-power-mode");
pinfo->mipi.hsa_power_stop = of_property_read_bool(np,
"qcom,mdss-dsi-hsa-power-mode");
pinfo->mipi.hbp_power_stop = of_property_read_bool(np,
"qcom,mdss-dsi-hbp-power-mode");
pinfo->mipi.bllp_power_stop = of_property_read_bool(np,
"qcom,mdss-dsi-bllp-power-mode");
pinfo->mipi.eof_bllp_power_stop = of_property_read_bool(
np, "qcom,mdss-dsi-bllp-eof-power-mode");
rc = of_property_read_u32(np,
"qcom,mdss-dsi-traffic-mode", &tmp);
pinfo->mipi.traffic_mode =
(!rc ? tmp : DSI_NON_BURST_SYNCH_PULSE);
rc = of_property_read_u32(np,
"qcom,mdss-dsi-te-dcs-command", &tmp);
pinfo->mipi.insert_dcs_cmd =
(!rc ? tmp : 1);
rc = of_property_read_u32(np,
"qcom,mdss-dsi-te-v-sync-continue-lines", &tmp);
pinfo->mipi.wr_mem_continue =
(!rc ? tmp : 0x3c);
rc = of_property_read_u32(np,
"qcom,mdss-dsi-te-v-sync-rd-ptr-irq-line", &tmp);
pinfo->mipi.wr_mem_start =
(!rc ? tmp : 0x2c);
rc = of_property_read_u32(np,
"qcom,mdss-dsi-te-pin-select", &tmp);
pinfo->mipi.te_sel =
(!rc ? tmp : 1);
rc = of_property_read_u32(np, "qcom,mdss-dsi-virtual-channel-id", &tmp);
pinfo->mipi.vc = (!rc ? tmp : 0);
rc = of_property_read_u32(np, "qcom,mdss-dsi-color-order", &tmp);
pinfo->mipi.rgb_swap = (!rc ? tmp : DSI_RGB_SWAP_RGB);
rc = of_property_read_u32(np, "qcom,mdss-force-clk-lane-hs", &tmp);
pinfo->mipi.force_clk_lane_hs = (!rc ? tmp : 0);
pinfo->mipi.data_lane0 = of_property_read_bool(np,
"qcom,mdss-dsi-lane-0-state");
pinfo->mipi.data_lane1 = of_property_read_bool(np,
"qcom,mdss-dsi-lane-1-state");
pinfo->mipi.data_lane2 = of_property_read_bool(np,
"qcom,mdss-dsi-lane-2-state");
pinfo->mipi.data_lane3 = of_property_read_bool(np,
"qcom,mdss-dsi-lane-3-state");
rc = of_property_read_u32(np, "qcom,mdss-dsi-lane-map", &tmp);
pinfo->mipi.dlane_swap = (!rc ? tmp : 0);
rc = of_property_read_u32(np, "qcom,mdss-dsi-t-clk-pre", &tmp);
pinfo->mipi.t_clk_pre = (!rc ? tmp : 0x24);
rc = of_property_read_u32(np, "qcom,mdss-dsi-t-clk-post", &tmp);
pinfo->mipi.t_clk_post = (!rc ? tmp : 0x03);
rc = of_property_read_u32(np, "qcom,mdss-dsi-stream", &tmp);
pinfo->mipi.stream = (!rc ? tmp : 0);
rc = of_property_read_u32(np, "qcom,mdss-dsi-mdp-trigger", &tmp);
pinfo->mipi.mdp_trigger =
(!rc ? tmp : DSI_CMD_TRIGGER_SW);
if (pinfo->mipi.mdp_trigger > 6) {
pr_err("%s:%d, Invalid mdp trigger. Forcing to sw trigger",
__func__, __LINE__);
pinfo->mipi.mdp_trigger =
DSI_CMD_TRIGGER_SW;
}
rc = of_property_read_u32(np, "qcom,mdss-dsi-dma-trigger", &tmp);
pinfo->mipi.dma_trigger =
(!rc ? tmp : DSI_CMD_TRIGGER_SW);
if (pinfo->mipi.dma_trigger > 6) {
pr_err("%s:%d, Invalid dma trigger. Forcing to sw trigger",
__func__, __LINE__);
pinfo->mipi.dma_trigger =
DSI_CMD_TRIGGER_SW;
}
data = of_get_property(np, "qcom,mdss-dsi-panel-mode-gpio-state", &tmp);
if (data) {
if (!strcmp(data, "high"))
pinfo->mode_gpio_state = MODE_GPIO_HIGH;
else if (!strcmp(data, "low"))
pinfo->mode_gpio_state = MODE_GPIO_LOW;
} else {
pinfo->mode_gpio_state = MODE_GPIO_NOT_VALID;
}
rc = of_property_read_u32(np, "qcom,mdss-dsi-panel-frame-rate", &tmp);
pinfo->mipi.frame_rate = (!rc ? tmp : 60);
rc = of_property_read_u32(np, "qcom,mdss-dsi-panel-clock-rate", &tmp);
pinfo->clk_rate = (!rc ? tmp : 0);
data = of_get_property(np,
"qcom,platform-strength-ctrl", &len);
if ((!data) || (len != 2)) {
pr_err("%s:%d, Unable to read Phy Strength ctrl settings",
__func__, __LINE__);
return -EINVAL;
}
pinfo->mipi.dsi_phy_db.strength[0] = data[0];
pinfo->mipi.dsi_phy_db.strength[1] = data[1];
data = of_get_property(np,
"qcom,platform-regulator-settings", &len);
if ((!data) || (len != 7)) {
pr_err("%s:%d, Unable to read Phy regulator settings",
__func__, __LINE__);
return -EINVAL;
}
for (i = 0; i < len; i++) {
pinfo->mipi.dsi_phy_db.regulator[i]
= data[i];
}
data = of_get_property(np, "qcom,mdss-dsi-panel-timings", &len);
if ((!data) || (len != 12)) {
pr_err("%s:%d, Unable to read Phy timing settings",
__func__, __LINE__);
goto error;
}
for (i = 0; i < len; i++)
pinfo->mipi.dsi_phy_db.timing[i] = data[i];
pinfo->mipi.lp11_init = of_property_read_bool(np,
"qcom,mdss-dsi-lp11-init");
rc = of_property_read_u32(np, "qcom,mdss-dsi-init-delay-us", &tmp);
pinfo->mipi.init_delay = (!rc ? tmp : 0);
mdss_dsi_parse_fbc_params(np, pinfo);
if(lcd_id == 0x55bc90){ //BOE
mdss_dsi_parse_dcs_cmds(np, &ctrl_pdata->on_cmds,
"qcom,mdss-dsi-on-command", "qcom,mdss-dsi-on-command-state");
}else if(lcd_id == 0x558cc0){ //SDC
mdss_dsi_parse_dcs_cmds(np, &ctrl_pdata->on_cmds,
"qcom,mdss-dsi-on-sdc-command", "qcom,mdss-dsi-on-command-state");
}else{
mdss_dsi_parse_dcs_cmds(np, &ctrl_pdata->on_cmds,
"qcom,mdss-dsi-on-command", "qcom,mdss-dsi-on-command-state");
}
mdss_dsi_parse_dcs_cmds(np, &ctrl_pdata->off_cmds,
"qcom,mdss-dsi-off-command", "qcom,mdss-dsi-off-command-state");
return 0;
error:
return -EINVAL;
}
static int rk_usb_control_probe(struct platform_device *pdev)
{
int gpio, err;
struct device_node *np = pdev->dev.of_node;
int ret = 0;
control_usb = devm_kzalloc(&pdev->dev, sizeof(*control_usb),GFP_KERNEL);
if (!control_usb) {
dev_err(&pdev->dev, "unable to alloc memory for control usb\n");
ret = -ENOMEM;
goto out;
}
control_usb->chip_id = RK3288_USB_CTLR;
control_usb->remote_wakeup = of_property_read_bool(np,
"rockchip,remote_wakeup");
control_usb->usb_irq_wakeup = of_property_read_bool(np,
"rockchip,usb_irq_wakeup");
INIT_DELAYED_WORK(&control_usb->usb_charger_det_work, usb_battery_charger_detect_work);
control_usb->host_gpios = devm_kzalloc(&pdev->dev, sizeof(struct gpio), GFP_KERNEL);
if(!control_usb->host_gpios){
dev_err(&pdev->dev, "unable to alloc memory for host_gpios\n");
ret = -ENOMEM;
goto out;
}
gpio = of_get_named_gpio(np, "host_drv_gpio", 0);
control_usb->host_gpios->gpio = gpio;
if(!gpio_is_valid(gpio)){
dev_err(&pdev->dev, "invalid host gpio%d\n", gpio);
}else{
err = devm_gpio_request(&pdev->dev, gpio, "host_drv_gpio");
if (err) {
dev_err(&pdev->dev,
"failed to request GPIO%d for host_drv\n",
gpio);
ret = err;
goto out;
}
gpio_direction_output(control_usb->host_gpios->gpio, 1);
}
control_usb->otg_gpios = devm_kzalloc(&pdev->dev, sizeof(struct gpio), GFP_KERNEL);
if(!control_usb->otg_gpios){
dev_err(&pdev->dev, "unable to alloc memory for otg_gpios\n");
ret = -ENOMEM;
goto out;
}
gpio = of_get_named_gpio(np, "otg_drv_gpio", 0);
control_usb->otg_gpios->gpio = gpio;
if(!gpio_is_valid(gpio)){
dev_err(&pdev->dev, "invalid otg gpio%d\n", gpio);
}else{
err = devm_gpio_request(&pdev->dev, gpio, "otg_drv_gpio");
if (err) {
dev_err(&pdev->dev,
"failed to request GPIO%d for otg_drv\n",
gpio);
ret = err;
goto out;
}
gpio_direction_output(control_usb->otg_gpios->gpio, 0);
}
out:
return ret;
}
int dsi_panel_device_register(struct device_node *pan_node,
struct mdss_dsi_ctrl_pdata *ctrl_pdata)
{
struct mipi_panel_info *mipi;
int rc, i, len;
struct device_node *dsi_ctrl_np = NULL;
struct platform_device *ctrl_pdev = NULL;
bool dynamic_fps;
const char *data;
struct mdss_panel_info *pinfo = &(ctrl_pdata->panel_data.panel_info);
enum of_gpio_flags flags;
mipi = &(pinfo->mipi);
pinfo->type =
((mipi->mode == DSI_VIDEO_MODE)
? MIPI_VIDEO_PANEL : MIPI_CMD_PANEL);
rc = mdss_dsi_clk_div_config(pinfo, mipi->frame_rate);
if (rc) {
pr_err("%s: unable to initialize the clk dividers\n", __func__);
return rc;
}
dsi_ctrl_np = of_parse_phandle(pan_node,
"qcom,mdss-dsi-panel-controller", 0);
if (!dsi_ctrl_np) {
pr_err("%s: Dsi controller node not initialized\n", __func__);
return -EPROBE_DEFER;
}
ctrl_pdev = of_find_device_by_node(dsi_ctrl_np);
rc = mdss_dsi_regulator_init(ctrl_pdev);
if (rc) {
pr_err("%s: failed to init regulator, rc=%d\n",
__func__, rc);
return rc;
}
data = of_get_property(ctrl_pdev->dev.of_node,
"qcom,platform-strength-ctrl", &len);
if ((!data) || (len != 2)) {
pr_err("%s:%d, Unable to read Phy Strength ctrl settings",
__func__, __LINE__);
return -EINVAL;
}
pinfo->mipi.dsi_phy_db.strength[0] = data[0];
pinfo->mipi.dsi_phy_db.strength[1] = data[1];
data = of_get_property(ctrl_pdev->dev.of_node,
"qcom,platform-regulator-settings", &len);
if ((!data) || (len != 7)) {
pr_err("%s:%d, Unable to read Phy regulator settings",
__func__, __LINE__);
return -EINVAL;
}
for (i = 0; i < len; i++) {
pinfo->mipi.dsi_phy_db.regulator[i]
= data[i];
}
data = of_get_property(ctrl_pdev->dev.of_node,
"qcom,platform-bist-ctrl", &len);
if ((!data) || (len != 6)) {
pr_err("%s:%d, Unable to read Phy Bist Ctrl settings",
__func__, __LINE__);
return -EINVAL;
}
for (i = 0; i < len; i++) {
pinfo->mipi.dsi_phy_db.bistctrl[i]
= data[i];
}
data = of_get_property(ctrl_pdev->dev.of_node,
"qcom,platform-lane-config", &len);
if ((!data) || (len != 45)) {
pr_err("%s:%d, Unable to read Phy lane configure settings",
__func__, __LINE__);
return -EINVAL;
}
for (i = 0; i < len; i++) {
pinfo->mipi.dsi_phy_db.lanecfg[i] =
data[i];
}
ctrl_pdata->shared_pdata.broadcast_enable = of_property_read_bool(
pan_node, "qcom,mdss-dsi-panel-broadcast-mode");
dynamic_fps = of_property_read_bool(pan_node,
"qcom,mdss-dsi-pan-enable-dynamic-fps");
if (dynamic_fps) {
pinfo->dynamic_fps = true;
data = of_get_property(pan_node,
"qcom,mdss-dsi-pan-fps-update", NULL);
if (data) {
if (!strcmp(data, "dfps_suspend_resume_mode")) {
pinfo->dfps_update =
DFPS_SUSPEND_RESUME_MODE;
pr_debug("%s: dfps mode: suspend/resume\n",
__func__);
} else if (!strcmp(data,
"dfps_immediate_clk_mode")) {
pinfo->dfps_update =
DFPS_IMMEDIATE_CLK_UPDATE_MODE;
pr_debug("%s: dfps mode: Immediate clk\n",
__func__);
} else if (!strcmp(data,
"dfps_immediate_porch_mode")) {
pinfo->dfps_update =
DFPS_IMMEDIATE_PORCH_UPDATE_MODE;
pr_debug("%s: dfps mode: Immediate porch\n",
__func__);
} else {
pr_debug("%s: dfps to default mode\n",
__func__);
pinfo->dfps_update =
DFPS_SUSPEND_RESUME_MODE;
pr_debug("%s: dfps mode: suspend/resume\n",
__func__);
}
} else {
pr_debug("%s: dfps update mode not configured\n",
__func__);
pinfo->dynamic_fps =
false;
pr_debug("%s: dynamic FPS disabled\n",
__func__);
}
pinfo->new_fps = pinfo->mipi.frame_rate;
}
pinfo->panel_max_fps = mdss_panel_get_framerate(pinfo);
pinfo->panel_max_vtotal = mdss_panel_get_vtotal(pinfo);
ctrl_pdata->disp_en_gpio = of_get_named_gpio(ctrl_pdev->dev.of_node,
"qcom,platform-enable-gpio", 0);
if (!gpio_is_valid(ctrl_pdata->disp_en_gpio))
pr_err("%s:%d, Disp_en gpio not specified\n",
__func__, __LINE__);
ctrl_pdata->disp_te_gpio = of_get_named_gpio(ctrl_pdev->dev.of_node,
"qcom,platform-te-gpio", 0);
if (!gpio_is_valid(ctrl_pdata->disp_te_gpio)) {
pr_err("%s:%d, Disp_te gpio not specified\n",
__func__, __LINE__);
} else {
int func;
rc = gpio_request(ctrl_pdata->disp_te_gpio, "disp_te");
if (rc) {
pr_err("request TE gpio failed, rc=%d\n",
rc);
return -ENODEV;
}
if (pinfo->type == MIPI_CMD_PANEL)
func = 1;
else
func = 0;
rc = gpio_tlmm_config(GPIO_CFG(
ctrl_pdata->disp_te_gpio, func,
GPIO_CFG_INPUT,
GPIO_CFG_PULL_DOWN,
GPIO_CFG_2MA),
GPIO_CFG_ENABLE);
if (rc) {
pr_err("%s: unable to config tlmm = %d\n",
__func__, ctrl_pdata->disp_te_gpio);
gpio_free(ctrl_pdata->disp_te_gpio);
return -ENODEV;
}
rc = gpio_direction_input(ctrl_pdata->disp_te_gpio);
if (rc) {
pr_err("set_direction for disp_en gpio failed, rc=%d\n",
rc);
gpio_free(ctrl_pdata->disp_te_gpio);
return -ENODEV;
}
pr_debug("%s: te_gpio=%d\n", __func__,
ctrl_pdata->disp_te_gpio);
}
ctrl_pdata->rst_gpio = of_get_named_gpio(ctrl_pdev->dev.of_node,
"qcom,platform-reset-gpio", 0);
if (!gpio_is_valid(ctrl_pdata->rst_gpio))
pr_err("%s:%d, reset gpio not specified\n",
__func__, __LINE__);
ctrl_pdata->mode_gpio = of_get_named_gpio(
ctrl_pdev->dev.of_node,
"qcom,platform-mode-gpio", 0);
if (pinfo->mode_gpio_state != MODE_GPIO_NOT_VALID) {
if (!gpio_is_valid(ctrl_pdata->mode_gpio))
pr_info("%s:%d, mode gpio not specified\n",
__func__, __LINE__);
}
if (ctrl_pdata->partial_mode_enabled) {
ctrl_pdata->mipi_d0_sel = of_get_named_gpio_flags(
ctrl_pdev->dev.of_node, "mmi,mipi-d0-sel", 0, &flags);
if (!gpio_is_valid(ctrl_pdata->mipi_d0_sel)) {
pr_info("%s:%d, mipi d0 sel gpio not specified\n",
__func__, __LINE__);
ctrl_pdata->partial_mode_enabled = false;
} else {
rc = gpio_request_one(ctrl_pdata->mipi_d0_sel, flags,
"mipi_d0_sel");
if (rc) {
pr_err("request mipi d0 sel gpio failed, rc=%d\n",
rc);
if (gpio_is_valid(ctrl_pdata->disp_te_gpio))
gpio_free(ctrl_pdata->disp_te_gpio);
ctrl_pdata->partial_mode_enabled = false;
return -ENODEV;
}
gpio_export(ctrl_pdata->mipi_d0_sel, 1);
}
}
if (mdss_dsi_clk_init(ctrl_pdev, ctrl_pdata)) {
pr_err("%s: unable to initialize Dsi ctrl clks\n", __func__);
return -EPERM;
}
if (mdss_dsi_retrieve_ctrl_resources(ctrl_pdev,
pinfo->pdest,
ctrl_pdata)) {
pr_err("%s: unable to get Dsi controller res\n", __func__);
return -EPERM;
}
ctrl_pdata->panel_data.event_handler = mdss_dsi_event_handler;
if (ctrl_pdata->bklt_ctrl == BL_PWM)
mdss_dsi_panel_pwm_cfg(ctrl_pdata);
mdss_dsi_ctrl_init(ctrl_pdata);
/*
* register in mdp driver
*/
ctrl_pdata->pclk_rate = mipi->dsi_pclk_rate;
ctrl_pdata->byte_clk_rate = pinfo->clk_rate / 8;
pr_debug("%s: pclk=%d, bclk=%d\n", __func__,
ctrl_pdata->pclk_rate, ctrl_pdata->byte_clk_rate);
ctrl_pdata->ctrl_state = CTRL_STATE_UNKNOWN;
if (pinfo->cont_splash_enabled) {
pinfo->panel_power_on = 1;
/*
* This call intends to call to gpio_request for display's
* reset gpio, because with cont_splash_enabled, there is
* no call to the mdss_dsi_panel_reset(1), but when the first
* suspend call, it will call mdss_dsi_panel_reset(0). This
* will call to gpio_free() for reset spio, and WARN() msg will
* be called because gpio_free() is called without gpio_request
*/
rc = mdss_dsi_panel_reset(&(ctrl_pdata->panel_data), 1);
if (rc) {
pr_err("%s: Panel reset on failed\n", __func__);
return rc;
}
rc = mdss_dsi_panel_power_on(&(ctrl_pdata->panel_data), 1);
if (rc) {
pr_err("%s: Panel power on failed\n", __func__);
return rc;
}
mdss_dsi_clk_ctrl(ctrl_pdata, DSI_ALL_CLKS, 1);
ctrl_pdata->ctrl_state |=
(CTRL_STATE_PANEL_INIT | CTRL_STATE_MDP_ACTIVE);
} else {
pinfo->panel_power_on = 0;
}
rc = mdss_register_panel(ctrl_pdev, &(ctrl_pdata->panel_data));
if (rc) {
pr_err("%s: unable to register MIPI DSI panel\n", __func__);
return rc;
}
if (pinfo->pdest == DISPLAY_1) {
mdss_debug_register_base("dsi0",
ctrl_pdata->ctrl_base, ctrl_pdata->reg_size);
ctrl_pdata->ndx = 0;
} else {
mdss_debug_register_base("dsi1",
ctrl_pdata->ctrl_base, ctrl_pdata->reg_size);
ctrl_pdata->ndx = 1;
}
pr_debug("%s: Panel data initialized\n", __func__);
return 0;
}
static int twl6040_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct twl6040_platform_data *pdata = client->dev.platform_data;
struct device_node *node = client->dev.of_node;
struct twl6040 *twl6040;
struct mfd_cell *cell = NULL;
int irq, ret, children = 0;
if (!pdata && !node) {
dev_err(&client->dev, "Platform data is missing\n");
return -EINVAL;
}
/* In order to operate correctly we need valid interrupt config */
if (!client->irq) {
dev_err(&client->dev, "Invalid IRQ configuration\n");
return -EINVAL;
}
twl6040 = devm_kzalloc(&client->dev, sizeof(struct twl6040),
GFP_KERNEL);
if (!twl6040) {
ret = -ENOMEM;
goto err;
}
twl6040->regmap = devm_regmap_init_i2c(client, &twl6040_regmap_config);
if (IS_ERR(twl6040->regmap)) {
ret = PTR_ERR(twl6040->regmap);
goto err;
}
i2c_set_clientdata(client, twl6040);
twl6040->supplies[0].supply = "vio";
twl6040->supplies[1].supply = "v2v1";
ret = devm_regulator_bulk_get(&client->dev, TWL6040_NUM_SUPPLIES,
twl6040->supplies);
if (ret != 0) {
dev_err(&client->dev, "Failed to get supplies: %d\n", ret);
goto regulator_get_err;
}
ret = regulator_bulk_enable(TWL6040_NUM_SUPPLIES, twl6040->supplies);
if (ret != 0) {
dev_err(&client->dev, "Failed to enable supplies: %d\n", ret);
goto regulator_get_err;
}
twl6040->dev = &client->dev;
twl6040->irq = client->irq;
mutex_init(&twl6040->mutex);
init_completion(&twl6040->ready);
twl6040->rev = twl6040_reg_read(twl6040, TWL6040_REG_ASICREV);
/* ERRATA: Automatic power-up is not possible in ES1.0 */
if (twl6040_get_revid(twl6040) > TWL6040_REV_ES1_0) {
if (pdata)
twl6040->audpwron = pdata->audpwron_gpio;
else
twl6040->audpwron = of_get_named_gpio(node,
"ti,audpwron-gpio", 0);
} else
twl6040->audpwron = -EINVAL;
if (gpio_is_valid(twl6040->audpwron)) {
ret = devm_gpio_request_one(&client->dev, twl6040->audpwron,
GPIOF_OUT_INIT_LOW, "audpwron");
if (ret)
goto gpio_err;
}
ret = regmap_add_irq_chip(twl6040->regmap, twl6040->irq,
IRQF_ONESHOT, 0, &twl6040_irq_chip,
&twl6040->irq_data);
if (ret < 0)
goto gpio_err;
twl6040->irq_ready = regmap_irq_get_virq(twl6040->irq_data,
TWL6040_IRQ_READY);
twl6040->irq_th = regmap_irq_get_virq(twl6040->irq_data,
TWL6040_IRQ_TH);
ret = devm_request_threaded_irq(twl6040->dev, twl6040->irq_ready, NULL,
twl6040_readyint_handler, IRQF_ONESHOT,
"twl6040_irq_ready", twl6040);
if (ret) {
dev_err(twl6040->dev, "READY IRQ request failed: %d\n", ret);
goto readyirq_err;
}
ret = devm_request_threaded_irq(twl6040->dev, twl6040->irq_th, NULL,
twl6040_thint_handler, IRQF_ONESHOT,
"twl6040_irq_th", twl6040);
if (ret) {
dev_err(twl6040->dev, "Thermal IRQ request failed: %d\n", ret);
goto thirq_err;
}
/* dual-access registers controlled by I2C only */
twl6040_set_bits(twl6040, TWL6040_REG_ACCCTL, TWL6040_I2CSEL);
/*
* The main functionality of twl6040 to provide audio on OMAP4+ systems.
* We can add the ASoC codec child whenever this driver has been loaded.
* The ASoC codec can work without pdata, pass the platform_data only if
* it has been provided.
*/
irq = regmap_irq_get_virq(twl6040->irq_data, TWL6040_IRQ_PLUG);
cell = &twl6040->cells[children];
cell->name = "twl6040-codec";
twl6040_codec_rsrc[0].start = irq;
twl6040_codec_rsrc[0].end = irq;
cell->resources = twl6040_codec_rsrc;
cell->num_resources = ARRAY_SIZE(twl6040_codec_rsrc);
if (pdata && pdata->codec) {
cell->platform_data = pdata->codec;
cell->pdata_size = sizeof(*pdata->codec);
}
children++;
if (twl6040_has_vibra(pdata, node)) {
irq = regmap_irq_get_virq(twl6040->irq_data, TWL6040_IRQ_VIB);
cell = &twl6040->cells[children];
cell->name = "twl6040-vibra";
twl6040_vibra_rsrc[0].start = irq;
twl6040_vibra_rsrc[0].end = irq;
cell->resources = twl6040_vibra_rsrc;
cell->num_resources = ARRAY_SIZE(twl6040_vibra_rsrc);
if (pdata && pdata->vibra) {
cell->platform_data = pdata->vibra;
cell->pdata_size = sizeof(*pdata->vibra);
}
children++;
}
/*
* Enable the GPO driver in the following cases:
* DT booted kernel or legacy boot with valid gpo platform_data
*/
if (!pdata || (pdata && pdata->gpo)) {
cell = &twl6040->cells[children];
cell->name = "twl6040-gpo";
if (pdata) {
cell->platform_data = pdata->gpo;
cell->pdata_size = sizeof(*pdata->gpo);
}
children++;
}
ret = mfd_add_devices(&client->dev, -1, twl6040->cells, children,
NULL, 0, NULL);
if (ret)
goto mfd_err;
return 0;
mfd_err:
devm_free_irq(&client->dev, twl6040->irq_th, twl6040);
thirq_err:
devm_free_irq(&client->dev, twl6040->irq_ready, twl6040);
readyirq_err:
regmap_del_irq_chip(twl6040->irq, twl6040->irq_data);
gpio_err:
regulator_bulk_disable(TWL6040_NUM_SUPPLIES, twl6040->supplies);
regulator_get_err:
i2c_set_clientdata(client, NULL);
err:
return ret;
}
static int spi_imx_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
const struct of_device_id *of_id =
of_match_device(spi_imx_dt_ids, &pdev->dev);
struct spi_imx_master *mxc_platform_info =
dev_get_platdata(&pdev->dev);
struct spi_master *master;
struct spi_imx_data *spi_imx;
struct resource *res;
int i, ret, num_cs;
if (!np && !mxc_platform_info) {
dev_err(&pdev->dev, "can't get the platform data\n");
return -EINVAL;
}
ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
if (ret < 0) {
if (mxc_platform_info)
num_cs = mxc_platform_info->num_chipselect;
else
return ret;
}
master = spi_alloc_master(&pdev->dev,
sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
if (!master)
return -ENOMEM;
platform_set_drvdata(pdev, master);
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
master->bus_num = pdev->id;
master->num_chipselect = num_cs;
spi_imx = spi_master_get_devdata(master);
spi_imx->bitbang.master = master;
for (i = 0; i < master->num_chipselect; i++) {
int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
if (!gpio_is_valid(cs_gpio) && mxc_platform_info)
cs_gpio = mxc_platform_info->chipselect[i];
spi_imx->chipselect[i] = cs_gpio;
if (!gpio_is_valid(cs_gpio))
continue;
ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i],
DRIVER_NAME);
if (ret) {
dev_err(&pdev->dev, "can't get cs gpios\n");
goto out_master_put;
}
}
spi_imx->bitbang.chipselect = spi_imx_chipselect;
spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
spi_imx->bitbang.master->setup = spi_imx_setup;
spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
init_completion(&spi_imx->xfer_done);
spi_imx->devtype_data = of_id ? of_id->data :
(struct spi_imx_devtype_data *) pdev->id_entry->driver_data;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(spi_imx->base)) {
ret = PTR_ERR(spi_imx->base);
goto out_master_put;
}
spi_imx->irq = platform_get_irq(pdev, 0);
if (spi_imx->irq < 0) {
ret = -EINVAL;
goto out_master_put;
}
ret = devm_request_irq(&pdev->dev, spi_imx->irq, spi_imx_isr, 0,
DRIVER_NAME, spi_imx);
if (ret) {
dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
goto out_master_put;
}
spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
if (IS_ERR(spi_imx->clk_ipg)) {
ret = PTR_ERR(spi_imx->clk_ipg);
goto out_master_put;
}
spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
if (IS_ERR(spi_imx->clk_per)) {
ret = PTR_ERR(spi_imx->clk_per);
goto out_master_put;
}
ret = clk_prepare_enable(spi_imx->clk_per);
if (ret)
goto out_master_put;
ret = clk_prepare_enable(spi_imx->clk_ipg);
if (ret)
goto out_put_per;
spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
spi_imx->devtype_data->reset(spi_imx);
spi_imx->devtype_data->intctrl(spi_imx, 0);
master->dev.of_node = pdev->dev.of_node;
ret = spi_bitbang_start(&spi_imx->bitbang);
if (ret) {
dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
goto out_clk_put;
}
dev_info(&pdev->dev, "probed\n");
clk_disable(spi_imx->clk_ipg);
clk_disable(spi_imx->clk_per);
return ret;
out_clk_put:
clk_disable_unprepare(spi_imx->clk_ipg);
out_put_per:
clk_disable_unprepare(spi_imx->clk_per);
out_master_put:
spi_master_put(master);
return ret;
}
static int idtp9017_parse_dt(struct device_node *dev_node,
struct idtp9017_chip *chip) {
int ret = -1;
chip->wlc_active_n_gpio = of_get_named_gpio(dev_node,
"idt,wlc_active_n_gpio", 0);
if (chip->wlc_active_n_gpio < 0) {
pr_err("Fail to get wlc_active_n_gpio\n");
goto out;
} else {
pr_info("Get wlc_active_n_gpio : %d\n",
chip->wlc_active_n_gpio);
}
chip->wlc_full_chg_gpio = of_get_named_gpio(dev_node,
"idt,wlc_full_chg_gpio", 0);
if (chip->wlc_full_chg_gpio < 0) {
pr_err("Fail to get wlc_full_chg_gpio\n");
goto out;
} else {
pr_info("Get wlc_full_chg_gpio : %d\n",
chip->wlc_full_chg_gpio);
}
chip->wlc_off_gpio = of_get_named_gpio(dev_node,
"idt,wlc_off_gpio", 0);
if (chip->wlc_off_gpio < 0) {
pr_err("Fail to get wlc_off_gpio\n");
goto out;
} else {
pr_info("Get wlc_off_gpio : %d\n",
chip->wlc_off_gpio);
}
ret = of_property_read_u32(dev_node,
"idt,mode_depth", &chip->mode_depth);
if (ret) {
pr_err("Not exist die_shdn_off paramaeter\n");
chip->mode_depth = 0;
} else {
pr_info("Get mode_depth : %d\n",
chip->mode_depth);
}
ret = of_property_read_u32(dev_node,
"idt,fod1-gain", &chip->fod1_gain);
if (ret) {
pr_err("Not exist die_shdn_off paramaeter\n");
chip->fod1_gain = 0;
} else {
pr_info("Get fod1_gain : %d\n",
chip->fod1_gain);
}
ret = of_property_read_u32(dev_node,
"idt,fod2-gain", &chip->fod2_gain);
if (ret) {
pr_err("Not exist die_shdn_off paramaeter\n");
chip->fod2_gain = 0;
} else {
pr_info("Get fod2_gain : %d\n",
chip->fod2_gain);
}
ret = of_property_read_u32(dev_node,
"idt,die-shdn-off", &chip->die_shdn_off);
if (ret) {
pr_err("Not exist die_shdn_off paramaeter\n");
chip->die_shdn_off = 0;
} else {
pr_info("Get die_shdn_off : %d\n",
chip->die_shdn_off);
}
ret = of_property_read_u32(dev_node,
"idt,die-shdn-hys", &chip->die_shdn_hys);
if (ret) {
pr_err("Not exist die_shdn_hys paramaeter\n");
chip->die_shdn_hys = 0;
} else {
pr_info("Get shdn_hys : %d\n",
chip->die_shdn_hys);
}
ret = of_property_read_u32(dev_node,
"idt,die-temp-off", &chip->die_temp_off);
if (ret) {
pr_err("Not exist tmep_off paramaeter\n");
chip->die_temp_off = 0;
} else {
pr_info("Get temp_off : %d\n",
chip->die_temp_off);
}
ret = of_property_read_u32(dev_node,
"idt,die-temp-hys", &chip->die_temp_hys);
if (ret) {
pr_err("Not exist temp_hys paramaeter\n");
chip->die_temp_hys = 0;
} else {
pr_info("Get temp_hys : %d\n",
chip->die_temp_hys);
}
ret = of_property_read_u32(dev_node,
"idt,limit-current", &chip->set_limit_current_ma);
if (ret) {
pr_err("Not exist temp_hys paramaeter\n");
chip->set_limit_current_ma = 0;
} else {
pr_info("Get limit_current : %d\n",
chip->set_limit_current_ma);
}
ret = of_property_read_u32(dev_node,
"idt,out-voltage", &chip->set_out_voltage);
if (ret) {
pr_err("Not exist temp_hys paramaeter\n");
chip->set_out_voltage = 0;
} else {
pr_info("Get out_voltage : %d\n",
chip->set_out_voltage);
}
return 0;
out:
return ret;
}
static int efm32_spi_probe(struct platform_device *pdev)
{
struct efm32_spi_ddata *ddata;
struct resource *res;
int ret;
struct spi_master *master;
struct device_node *np = pdev->dev.of_node;
int num_cs, i;
if (!np)
return -EINVAL;
num_cs = of_gpio_named_count(np, "cs-gpios");
if (num_cs < 0)
return num_cs;
master = spi_alloc_master(&pdev->dev,
sizeof(*ddata) + num_cs * sizeof(unsigned));
if (!master) {
dev_dbg(&pdev->dev,
"failed to allocate spi master controller\n");
return -ENOMEM;
}
platform_set_drvdata(pdev, master);
master->dev.of_node = pdev->dev.of_node;
master->num_chipselect = num_cs;
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
ddata = spi_master_get_devdata(master);
ddata->bitbang.master = master;
ddata->bitbang.chipselect = efm32_spi_chipselect;
ddata->bitbang.setup_transfer = efm32_spi_setup_transfer;
ddata->bitbang.txrx_bufs = efm32_spi_txrx_bufs;
spin_lock_init(&ddata->lock);
init_completion(&ddata->done);
ddata->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(ddata->clk)) {
ret = PTR_ERR(ddata->clk);
dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
goto err;
}
for (i = 0; i < num_cs; ++i) {
ret = of_get_named_gpio(np, "cs-gpios", i);
if (ret < 0) {
dev_err(&pdev->dev, "failed to get csgpio#%u (%d)\n",
i, ret);
goto err;
}
ddata->csgpio[i] = ret;
dev_dbg(&pdev->dev, "csgpio#%u = %u\n", i, ddata->csgpio[i]);
ret = devm_gpio_request_one(&pdev->dev, ddata->csgpio[i],
GPIOF_OUT_INIT_LOW, DRIVER_NAME);
if (ret < 0) {
dev_err(&pdev->dev,
"failed to configure csgpio#%u (%d)\n",
i, ret);
goto err;
}
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
ret = -ENODEV;
dev_err(&pdev->dev, "failed to determine base address\n");
goto err;
}
if (resource_size(res) < 0x60) {
ret = -EINVAL;
dev_err(&pdev->dev, "memory resource too small\n");
goto err;
}
ddata->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(ddata->base)) {
ret = PTR_ERR(ddata->base);
goto err;
}
ret = platform_get_irq(pdev, 0);
if (ret <= 0) {
dev_err(&pdev->dev, "failed to get rx irq (%d)\n", ret);
goto err;
}
ddata->rxirq = ret;
ret = platform_get_irq(pdev, 1);
if (ret <= 0)
ret = ddata->rxirq + 1;
ddata->txirq = ret;
ret = clk_prepare_enable(ddata->clk);
if (ret < 0) {
dev_err(&pdev->dev, "failed to enable clock (%d)\n", ret);
goto err;
}
efm32_spi_probe_dt(pdev, master, ddata);
efm32_spi_write32(ddata, 0, REG_IEN);
efm32_spi_write32(ddata, REG_ROUTE_TXPEN | REG_ROUTE_RXPEN |
REG_ROUTE_CLKPEN |
REG_ROUTE_LOCATION(ddata->pdata.location), REG_ROUTE);
ret = request_irq(ddata->rxirq, efm32_spi_rxirq,
0, DRIVER_NAME " rx", ddata);
if (ret) {
dev_err(&pdev->dev, "failed to register rxirq (%d)\n", ret);
goto err_disable_clk;
}
ret = request_irq(ddata->txirq, efm32_spi_txirq,
0, DRIVER_NAME " tx", ddata);
if (ret) {
dev_err(&pdev->dev, "failed to register txirq (%d)\n", ret);
goto err_free_rx_irq;
}
ret = spi_bitbang_start(&ddata->bitbang);
if (ret) {
dev_err(&pdev->dev, "spi_bitbang_start failed (%d)\n", ret);
free_irq(ddata->txirq, ddata);
err_free_rx_irq:
free_irq(ddata->rxirq, ddata);
err_disable_clk:
clk_disable_unprepare(ddata->clk);
err:
spi_master_put(master);
}
return ret;
}
static int fuelgauge_parse_dt(struct device *dev,
struct sec_fuelgauge_info *fuelgauge)
{
struct device_node *np = dev->of_node;
sec_battery_platform_data_t *pdata = fuelgauge->pdata;
/* reset, irq gpio info */
if (np == NULL)
pr_err("%s np NULL\n", __func__);
else {
int ret;
ret = pdata->fg_irq = of_get_named_gpio(np, "fuelgauge,fuel_int", 0);
if (ret < 0)
pr_err("%s error reading fg_irq = %d\n", __func__, pdata->fg_irq);
#if defined(CONFIG_FUELGAUGE_MAX17050)
ret = of_property_read_u32(np, "fuelgauge,jig_gpio",
&pdata->jig_irq);
if (ret < 0)
pr_err("%s error reading jig_gpio %d\n", __func__, ret);
ret = of_get_named_gpio(np, "fuelgauge,bat_int", 0);
ta_int_gpio = ret;
sec_battery_pdata.bat_irq = gpio_to_irq(ret);
if (ret < 0)
pr_err("%s error reading bat_int = %d\n", __func__, ret);
pr_err("%s: ta_int_gpio(%d), bat_irq(%d)\n",
__func__, ret, sec_battery_pdata.bat_irq);
pr_info("%s fg_irq: %d, jig_irq: %d, capacity_max: %d, "
"cpacity_max_margin: %d, capacity_min: %d, "
"calculation_type: 0x%x, fuel_alert_soc: %d,\n"
"repeated_fuelalert: %d, Capacity: 0x%x, "
"low_battery_comp_voltage: 0x%x, "
"type_str: %s\n", __func__, pdata->fg_irq, pdata->jig_irq,
pdata->capacity_max, pdata->capacity_max_margin,
pdata->capacity_min, pdata->capacity_calculation_type,
pdata->fuel_alert_soc, pdata->repeated_fuelalert,
get_battery_data(fuelgauge).Capacity,
get_battery_data(fuelgauge).low_battery_comp_voltage,
get_battery_data(fuelgauge).type_str
);
#else
ret = of_get_named_gpio(np, "fuelgauge,bat_int", 0);
if (ret > 0) {
sec_battery_pdata.bat_irq_gpio = ret;
sec_battery_pdata.bat_irq = gpio_to_irq(ret);
pr_info("%s reading bat_int_gpio = %d\n", __func__, ret);
}
pr_info("%s: fg_irq: %d, capacity_max: %d, "
"cpacity_max_margin: %d, capacity_min: %d,"
"calculation_type: 0x%x, fuel_alert_soc: %d,\n"
"repeated_fuelalert: %d, RCOMP0: 0x%x,"
"RCOMP_charging: 0x%x, temp_cohot: %d,"
"temp_cocold: %d, is_using_model_data: %d,"
"type_str: %s,\n", __func__, pdata->fg_irq,
pdata->capacity_max, pdata->capacity_max_margin,
pdata->capacity_min, pdata->capacity_calculation_type,
pdata->fuel_alert_soc, pdata->repeated_fuelalert,
get_battery_data(fuelgauge).RCOMP0,
get_battery_data(fuelgauge).RCOMP_charging,
get_battery_data(fuelgauge).temp_cohot,
get_battery_data(fuelgauge).temp_cocold,
get_battery_data(fuelgauge).is_using_model_data,
get_battery_data(fuelgauge).type_str
);
#endif
}
return 0;
}
/*
* QCOM specific functions
*/
static int stmvl6180_get_dt_data(struct device *dev, struct cci_data *data)
{
int rc = 0;
vl6180_dbgmsg("Enter\n");
if (dev->of_node) {
struct device_node *of_node = dev->of_node;
struct msm_tof_vreg *vreg_cfg;
if (!of_node) {
vl6180_errmsg("failed %d\n", __LINE__);
return -EINVAL;
}
rc = of_property_read_u32(of_node, "cell-index", &data->pdev->id);
if (rc < 0) {
vl6180_errmsg("failed %d\n", __LINE__);
return rc;
}
vl6180_dbgmsg("cell-index: %d\n", data->pdev->id);
rc = of_property_read_u32(of_node, "qcom,cci-master", &data->cci_master);
if (rc < 0) {
vl6180_errmsg("failed %d\n", __LINE__);
/* Set default master 0 */
data->cci_master = MASTER_0;
rc = 0;
}
vl6180_dbgmsg("cci_master: %d\n", data->cci_master);
rc = of_property_read_u32(of_node, "qcom,slave-addr",&data->slave_addr);
if (rc < 0) {
vl6180_errmsg("failed %d\n", __LINE__);
data->slave_addr = 0x29;
rc = 0;
}
vl6180_dbgmsg("slave addr: %d\n", data->slave_addr);
if (of_find_property(of_node, "qcom,cam-vreg-name", NULL)) {
vreg_cfg = &data->vreg_cfg;
rc = msm_camera_get_dt_vreg_data(of_node,
&vreg_cfg->cam_vreg, &vreg_cfg->num_vreg);
if (rc < 0) {
vl6180_errmsg("failed %d\n", __LINE__);
return rc;
}
}
vl6180_dbgmsg("vreg-name: %s min_volt: %d max_volt: %d",
vreg_cfg->cam_vreg->reg_name,
vreg_cfg->cam_vreg->min_voltage,
vreg_cfg->cam_vreg->max_voltage);
data->en_gpio = of_get_named_gpio(of_node,
"stmvl6180,ldaf-en-gpio",0);
if (data->en_gpio < 0 || !gpio_is_valid(data->en_gpio)) {
vl6180_errmsg("en_gpio is unavailable or invalid\n");
return data->en_gpio;
}
data->int_gpio = of_get_named_gpio(of_node,
"stmvl6180,ldaf-int-gpio",0);
if (data->int_gpio < 0 || !gpio_is_valid(data->int_gpio)) {
vl6180_errmsg("en_gpio is unvailable or invalid\n");
return data->int_gpio;
}
vl6180_dbgmsg("ldaf_int: %u,ldaf_en: %u\n",
data->int_gpio,data->en_gpio);
rc = of_property_read_u32(of_node, "qcom,i2c-freq-mode",
&data->i2c_freq_mode);
if (rc < 0 || data->i2c_freq_mode >= I2C_MAX_MODES) {
data->i2c_freq_mode = 0;
vl6180_errmsg("invalid i2c frequency mode\n");
}
vl6180_dbgmsg("i2c_freq_mode: %u\n",data->i2c_freq_mode);
}
vl6180_dbgmsg("End rc =%d\n", rc);
return rc;
}
static int bq24192_parse_dt(struct device_node *dev_node,
struct bq24192_chip *chip)
{
int ret = 0;
chip->int_gpio =
of_get_named_gpio(dev_node, "ti,int-gpio", 0);
if (chip->int_gpio < 0) {
pr_err("failed to get int-gpio.\n");
ret = chip->int_gpio;
goto out;
}
ret = of_property_read_u32(dev_node, "ti,chg-current-ma",
&(chip->chg_current_ma));
if (ret) {
pr_err("Unable to read chg_current.\n");
return ret;
}
ret = of_property_read_u32(dev_node, "ti,term-current-ma",
&(chip->term_current_ma));
if (ret) {
pr_err("Unable to read term_current_ma.\n");
return ret;
}
ret = of_property_read_u32(dev_node, "ti,vbat-max-mv",
&chip->vbat_max_mv);
if (ret) {
pr_err("Unable to read vbat-max-mv.\n");
return ret;
}
ret = of_property_read_u32(dev_node, "ti,pre-chg-current-ma",
&chip->pre_chg_current_ma);
if (ret) {
pr_err("Unable to read pre-chg-current-ma.\n");
return ret;
}
ret = of_property_read_u32(dev_node, "ti,sys-vimin-mv",
&chip->sys_vmin_mv);
if (ret) {
pr_err("Unable to read sys-vimin-mv.\n");
return ret;
}
ret = of_property_read_u32(dev_node, "ti,vin-limit-mv",
&chip->vin_limit_mv);
if (ret) {
pr_err("Unable to read vin-limit-mv.\n");
return ret;
}
ret = of_property_read_u32(dev_node, "ti,wlc-vin-limit-mv",
&chip->wlc_vin_limit_mv);
if (ret) {
pr_err("Unable to read wlc-vin-limit-mv.\n");
return ret;
}
ret = of_property_read_u32(dev_node, "ti,step-dwn-current-ma",
&chip->step_dwn_currnet_ma);
if (ret) {
pr_err("Unable to read step-dwn-current-ma.\n");
return ret;
}
ret = of_property_read_u32(dev_node, "ti,step-dwn-thr-mv",
&chip->step_dwn_thr_mv);
if (ret) {
pr_err("Unable to read step down threshod voltage.\n");
return ret;
}
ret = of_property_read_u32(dev_node, "ti,icl-vbus-mv",
&chip->icl_vbus_mv);
if (ret) {
pr_err("Unable to read icl threshod voltage.\n");
return ret;
}
ret = of_property_read_u32(dev_node, "ti,wlc-step-dwn-i-ma",
&chip->wlc_dwn_i_ma);
if (ret) {
pr_err("Unable to read step down current for wlc.\n");
return ret;
}
ret = of_property_read_u32(dev_node, "ti,wlc-dwn-input-i-ma",
&chip->wlc_dwn_input_i_ma);
if (ret) {
pr_err("Unable to read step down input i limit for wlc.\n");
return ret;
}
chip->wlc_support =
of_property_read_bool(dev_node, "ti,wlc-support");
chip->ext_ovp_otg_ctrl =
of_property_read_bool(dev_node,
"ti,ext-ovp-otg-ctrl");
if (chip->ext_ovp_otg_ctrl) {
chip->otg_en_gpio =
of_get_named_gpio(dev_node, "ti,otg-en-gpio", 0);
if (chip->otg_en_gpio < 0) {
pr_err("Unable to get named gpio for otg_en_gpio.\n");
return chip->otg_en_gpio;
}
}
out:
return ret;
}
static int mdss_panel_parse_dt(struct platform_device *pdev,
struct mdss_panel_common_pdata *panel_data)
{
struct device_node *np = pdev->dev.of_node;
u32 res[6], tmp;
u32 fbc_res[7];
int rc, i, len;
const char *data;
static const char *bl_ctrl_type, *pdest;
bool fbc_enabled = false;
rc = of_property_read_u32_array(np, "qcom,mdss-pan-res", res, 2);
if (rc) {
pr_err("%s:%d, panel resolution not specified\n",
__func__, __LINE__);
return -EINVAL;
}
panel_data->panel_info.xres = (!rc ? res[0] : 640);
panel_data->panel_info.yres = (!rc ? res[1] : 480);
rc = of_property_read_u32(np, "qcom,mdss-pan-id", &tmp);
if (!rc)
mdss_panel_id = tmp;
pr_info("%s: Panel ID = %d\n", __func__, mdss_panel_id);
mdss_panel_flip_ud = of_property_read_bool(np, "qcom,mdss-pan-flip-ud");
if (mdss_panel_flip_ud)
pr_info("%s: Panel FLIP UD\n", __func__);
rc = of_property_read_u32_array(np, "qcom,mdss-pan-active-res", res, 2);
if (rc == 0) {
panel_data->panel_info.lcdc.xres_pad =
panel_data->panel_info.xres - res[0];
panel_data->panel_info.lcdc.yres_pad =
panel_data->panel_info.yres - res[1];
}
rc = of_property_read_u32(np, "qcom,mdss-pan-bpp", &tmp);
if (rc) {
pr_err("%s:%d, panel bpp not specified\n",
__func__, __LINE__);
return -EINVAL;
}
panel_data->panel_info.bpp = (!rc ? tmp : 24);
rc = of_property_read_u32(np, "qcom,mdss-pan-width", &tmp);
if (rc)
pr_warn("%s:%d, panel width not specified\n",
__func__, __LINE__);
panel_data->panel_info.width = (!rc ? tmp : 0);
rc = of_property_read_u32(np, "qcom,mdss-pan-height", &tmp);
if (rc)
pr_warn("%s:%d, panel height not specified\n",
__func__, __LINE__);
panel_data->panel_info.height = (!rc ? tmp : 0);
pdest = of_get_property(pdev->dev.of_node,
"qcom,mdss-pan-dest", NULL);
if (strlen(pdest) != 9) {
pr_err("%s: Unknown pdest specified\n", __func__);
return -EINVAL;
}
if (!strncmp(pdest, "display_1", 9))
panel_data->panel_info.pdest = DISPLAY_1;
else if (!strncmp(pdest, "display_2", 9))
panel_data->panel_info.pdest = DISPLAY_2;
else {
pr_debug("%s: pdest not specified. Set Default\n",
__func__);
panel_data->panel_info.pdest = DISPLAY_1;
}
rc = of_property_read_u32_array(np,
"qcom,mdss-pan-porch-values", res, 6);
panel_data->panel_info.lcdc.h_back_porch = (!rc ? res[0] : 6);
panel_data->panel_info.lcdc.h_pulse_width = (!rc ? res[1] : 2);
panel_data->panel_info.lcdc.h_front_porch = (!rc ? res[2] : 6);
panel_data->panel_info.lcdc.v_back_porch = (!rc ? res[3] : 6);
panel_data->panel_info.lcdc.v_pulse_width = (!rc ? res[4] : 2);
panel_data->panel_info.lcdc.v_front_porch = (!rc ? res[5] : 6);
rc = of_property_read_u32(np,
"qcom,mdss-pan-underflow-clr", &tmp);
panel_data->panel_info.lcdc.underflow_clr = (!rc ? tmp : 0xff);
bl_ctrl_type = of_get_property(pdev->dev.of_node,
"qcom,mdss-pan-bl-ctrl", NULL);
if ((bl_ctrl_type) && (!strncmp(bl_ctrl_type, "bl_ctrl_wled", 12))) {
led_trigger_register_simple("bkl-trigger", &bl_led_trigger);
pr_debug("%s: SUCCESS-> WLED TRIGGER register\n", __func__);
panel_data->panel_info.bklt_ctrl = BL_WLED;
} else if (!strncmp(bl_ctrl_type, "bl_ctrl_pwm", 11)) {
panel_data->panel_info.bklt_ctrl = BL_PWM;
rc = of_property_read_u32(np, "qcom,pwm-period", &tmp);
if (rc) {
pr_err("%s:%d, Error, panel pwm_period\n",
__func__, __LINE__);
return -EINVAL;
}
panel_data->panel_info.pwm_period = tmp;
rc = of_property_read_u32(np, "qcom,pwm-lpg-channel", &tmp);
if (rc) {
pr_err("%s:%d, Error, dsi lpg channel\n",
__func__, __LINE__);
return -EINVAL;
}
panel_data->panel_info.pwm_lpg_chan = tmp;
tmp = of_get_named_gpio(np, "qcom,pwm-pmic-gpio", 0);
panel_data->panel_info.pwm_pmic_gpio = tmp;
} else if (!strncmp(bl_ctrl_type, "bl_ctrl_dcs", 11)) {
panel_data->panel_info.bklt_ctrl = BL_DCS_CMD;
} else {
pr_debug("%s: Unknown backlight control\n", __func__);
panel_data->panel_info.bklt_ctrl = UNKNOWN_CTRL;
}
rc = of_property_read_u32_array(np,
"qcom,mdss-pan-bl-levels", res, 2);
panel_data->panel_info.bl_min = (!rc ? res[0] : 0);
panel_data->panel_info.bl_max = (!rc ? res[1] : 255);
rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-mode", &tmp);
panel_data->panel_info.mipi.mode = (!rc ? tmp : DSI_VIDEO_MODE);
rc = of_property_read_u32(np, "qcom,mdss-vsync-enable", &tmp);
panel_data->panel_info.mipi.vsync_enable = (!rc ? tmp : 0);
rc = of_property_read_u32(np, "qcom,mdss-hw-vsync-mode", &tmp);
panel_data->panel_info.mipi.hw_vsync_mode = (!rc ? tmp : 0);
rc = of_property_read_u32(np,
"qcom,mdss-pan-dsi-h-pulse-mode", &tmp);
panel_data->panel_info.mipi.pulse_mode_hsa_he = (!rc ? tmp : false);
rc = of_property_read_u32_array(np,
"qcom,mdss-pan-dsi-h-power-stop", res, 3);
panel_data->panel_info.mipi.hbp_power_stop = (!rc ? res[0] : false);
panel_data->panel_info.mipi.hsa_power_stop = (!rc ? res[1] : false);
panel_data->panel_info.mipi.hfp_power_stop = (!rc ? res[2] : false);
rc = of_property_read_u32_array(np,
"qcom,mdss-pan-dsi-bllp-power-stop", res, 2);
panel_data->panel_info.mipi.bllp_power_stop =
(!rc ? res[0] : false);
panel_data->panel_info.mipi.eof_bllp_power_stop =
(!rc ? res[1] : false);
rc = of_property_read_u32(np,
"qcom,mdss-pan-dsi-traffic-mode", &tmp);
panel_data->panel_info.mipi.traffic_mode =
(!rc ? tmp : DSI_NON_BURST_SYNCH_PULSE);
rc = of_property_read_u32(np,
"qcom,mdss-pan-insert-dcs-cmd", &tmp);
panel_data->panel_info.mipi.insert_dcs_cmd =
(!rc ? tmp : 1);
rc = of_property_read_u32(np,
"qcom,mdss-pan-wr-mem-continue", &tmp);
panel_data->panel_info.mipi.wr_mem_continue =
(!rc ? tmp : 0x3c);
rc = of_property_read_u32(np,
"qcom,mdss-pan-wr-mem-start", &tmp);
panel_data->panel_info.mipi.wr_mem_start =
(!rc ? tmp : 0x2c);
rc = of_property_read_u32(np,
"qcom,mdss-pan-te-sel", &tmp);
panel_data->panel_info.mipi.te_sel =
(!rc ? tmp : 1);
rc = of_property_read_u32(np,
"qcom,mdss-pan-dsi-dst-format", &tmp);
panel_data->panel_info.mipi.dst_format =
(!rc ? tmp : DSI_VIDEO_DST_FORMAT_RGB888);
rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-vc", &tmp);
panel_data->panel_info.mipi.vc = (!rc ? tmp : 0);
rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-rgb-swap", &tmp);
panel_data->panel_info.mipi.rgb_swap = (!rc ? tmp : DSI_RGB_SWAP_RGB);
rc = of_property_read_u32_array(np,
"qcom,mdss-pan-dsi-data-lanes", res, 4);
panel_data->panel_info.mipi.data_lane0 = (!rc ? res[0] : true);
panel_data->panel_info.mipi.data_lane1 = (!rc ? res[1] : false);
panel_data->panel_info.mipi.data_lane2 = (!rc ? res[2] : false);
panel_data->panel_info.mipi.data_lane3 = (!rc ? res[3] : false);
rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-dlane-swap", &tmp);
panel_data->panel_info.mipi.dlane_swap = (!rc ? tmp : 0);
rc = of_property_read_u32_array(np, "qcom,mdss-pan-dsi-t-clk", res, 2);
panel_data->panel_info.mipi.t_clk_pre = (!rc ? res[0] : 0x24);
panel_data->panel_info.mipi.t_clk_post = (!rc ? res[1] : 0x03);
rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-stream", &tmp);
panel_data->panel_info.mipi.stream = (!rc ? tmp : 0);
rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-mdp-tr", &tmp);
panel_data->panel_info.mipi.mdp_trigger =
(!rc ? tmp : DSI_CMD_TRIGGER_SW);
if (panel_data->panel_info.mipi.mdp_trigger > 6) {
pr_err("%s:%d, Invalid mdp trigger. Forcing to sw trigger",
__func__, __LINE__);
panel_data->panel_info.mipi.mdp_trigger =
DSI_CMD_TRIGGER_SW;
}
rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-dma-tr", &tmp);
panel_data->panel_info.mipi.dma_trigger =
(!rc ? tmp : DSI_CMD_TRIGGER_SW);
if (panel_data->panel_info.mipi.dma_trigger > 6) {
pr_err("%s:%d, Invalid dma trigger. Forcing to sw trigger",
__func__, __LINE__);
panel_data->panel_info.mipi.dma_trigger =
DSI_CMD_TRIGGER_SW;
}
rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-frame-rate", &tmp);
panel_data->panel_info.mipi.frame_rate = (!rc ? tmp : 60);
rc = of_property_read_u32(np, "qcom,mdss-pan-clk-rate", &tmp);
panel_data->panel_info.clk_rate = (!rc ? tmp : 0);
data = of_get_property(np, "qcom,panel-phy-regulatorSettings", &len);
if ((!data) || (len != 7)) {
pr_err("%s:%d, Unable to read Phy regulator settings",
__func__, __LINE__);
goto error;
}
for (i = 0; i < len; i++)
phy_params.regulator[i] = data[i];
data = of_get_property(np, "qcom,panel-phy-timingSettings", &len);
if ((!data) || (len != 12)) {
pr_err("%s:%d, Unable to read Phy timing settings",
__func__, __LINE__);
goto error;
}
for (i = 0; i < len; i++)
phy_params.timing[i] = data[i];
data = of_get_property(np, "qcom,panel-phy-strengthCtrl", &len);
if ((!data) || (len != 2)) {
pr_err("%s:%d, Unable to read Phy Strength ctrl settings",
__func__, __LINE__);
goto error;
}
phy_params.strength[0] = data[0];
phy_params.strength[1] = data[1];
data = of_get_property(np, "qcom,panel-phy-bistCtrl", &len);
if ((!data) || (len != 6)) {
pr_err("%s:%d, Unable to read Phy Bist Ctrl settings",
__func__, __LINE__);
goto error;
}
for (i = 0; i < len; i++)
phy_params.bistCtrl[i] = data[i];
data = of_get_property(np, "qcom,panel-phy-laneConfig", &len);
if ((!data) || (len != 45)) {
pr_err("%s:%d, Unable to read Phy lane configure settings",
__func__, __LINE__);
goto error;
}
for (i = 0; i < len; i++)
phy_params.laneCfg[i] = data[i];
panel_data->panel_info.mipi.dsi_phy_db = &phy_params;
fbc_enabled = of_property_read_bool(np,
"qcom,fbc-enabled");
if (fbc_enabled) {
pr_debug("%s:%d FBC panel enabled.\n", __func__, __LINE__);
panel_data->panel_info.fbc.enabled = 1;
rc = of_property_read_u32_array(np,
"qcom,fbc-mode", fbc_res, 7);
panel_data->panel_info.fbc.target_bpp =
(!rc ? fbc_res[0] : panel_data->panel_info.bpp);
panel_data->panel_info.fbc.comp_mode = (!rc ? fbc_res[1] : 0);
panel_data->panel_info.fbc.qerr_enable =
(!rc ? fbc_res[2] : 0);
panel_data->panel_info.fbc.cd_bias = (!rc ? fbc_res[3] : 0);
panel_data->panel_info.fbc.pat_enable = (!rc ? fbc_res[4] : 0);
panel_data->panel_info.fbc.vlc_enable = (!rc ? fbc_res[5] : 0);
panel_data->panel_info.fbc.bflc_enable =
(!rc ? fbc_res[6] : 0);
rc = of_property_read_u32_array(np,
"qcom,fbc-budget-ctl", fbc_res, 3);
panel_data->panel_info.fbc.line_x_budget =
(!rc ? fbc_res[0] : 0);
panel_data->panel_info.fbc.block_x_budget =
(!rc ? fbc_res[1] : 0);
panel_data->panel_info.fbc.block_budget =
(!rc ? fbc_res[2] : 0);
rc = of_property_read_u32_array(np,
"qcom,fbc-lossy-mode", fbc_res, 4);
panel_data->panel_info.fbc.lossless_mode_thd =
(!rc ? fbc_res[0] : 0);
panel_data->panel_info.fbc.lossy_mode_thd =
(!rc ? fbc_res[1] : 0);
panel_data->panel_info.fbc.lossy_rgb_thd =
(!rc ? fbc_res[2] : 0);
panel_data->panel_info.fbc.lossy_mode_idx =
(!rc ? fbc_res[3] : 0);
} else {
pr_debug("%s:%d Panel does not support FBC.\n",
__func__, __LINE__);
panel_data->panel_info.fbc.enabled = 0;
panel_data->panel_info.fbc.target_bpp =
panel_data->panel_info.bpp;
}
mdss_dsi_parse_dcs_cmds(np, &panel_data->on_cmds,
"qcom,panel-on-cmds", "qcom,on-cmds-dsi-state");
mdss_dsi_parse_dcs_cmds(np, &panel_data->off_cmds,
"qcom,panel-off-cmds", "qcom,off-cmds-dsi-state");
return 0;
error:
return -EINVAL;
}
static int sdhci_sirf_probe(struct platform_device *pdev)
{
struct sdhci_host *host;
struct sdhci_pltfm_host *pltfm_host;
struct sdhci_sirf_priv *priv;
struct clk *clk;
int gpio_cd;
int ret;
clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(clk)) {
dev_err(&pdev->dev, "unable to get clock");
return PTR_ERR(clk);
}
if (pdev->dev.of_node)
gpio_cd = of_get_named_gpio(pdev->dev.of_node, "cd-gpios", 0);
else
gpio_cd = -EINVAL;
host = sdhci_pltfm_init(pdev, &sdhci_sirf_pdata, sizeof(struct sdhci_sirf_priv));
if (IS_ERR(host))
return PTR_ERR(host);
pltfm_host = sdhci_priv(host);
pltfm_host->clk = clk;
priv = sdhci_pltfm_priv(pltfm_host);
priv->gpio_cd = gpio_cd;
sdhci_get_of_property(pdev);
ret = clk_prepare_enable(pltfm_host->clk);
if (ret)
goto err_clk_prepare;
ret = sdhci_add_host(host);
if (ret)
goto err_sdhci_add;
/*
* We must request the IRQ after sdhci_add_host(), as the tasklet only
* gets setup in sdhci_add_host() and we oops.
*/
if (gpio_is_valid(priv->gpio_cd)) {
ret = mmc_gpio_request_cd(host->mmc, priv->gpio_cd, 0);
if (ret) {
dev_err(&pdev->dev, "card detect irq request failed: %d\n",
ret);
goto err_request_cd;
}
mmc_gpiod_request_cd_irq(host->mmc);
}
return 0;
err_request_cd:
sdhci_remove_host(host, 0);
err_sdhci_add:
clk_disable_unprepare(pltfm_host->clk);
err_clk_prepare:
sdhci_pltfm_free(pdev);
return ret;
}
int ptn3460_init(struct drm_device *dev, struct drm_encoder *encoder,
struct i2c_client *client, struct device_node *node)
{
int ret;
struct drm_bridge *bridge;
struct ptn3460_bridge *ptn_bridge;
bridge = devm_kzalloc(dev->dev, sizeof(*bridge), GFP_KERNEL);
if (!bridge) {
DRM_ERROR("Failed to allocate drm bridge\n");
return -ENOMEM;
}
ptn_bridge = devm_kzalloc(dev->dev, sizeof(*ptn_bridge), GFP_KERNEL);
if (!ptn_bridge) {
DRM_ERROR("Failed to allocate ptn bridge\n");
return -ENOMEM;
}
ptn_bridge->client = client;
ptn_bridge->encoder = encoder;
ptn_bridge->bridge = bridge;
ptn_bridge->gpio_pd_n = of_get_named_gpio(node, "powerdown-gpio", 0);
if (gpio_is_valid(ptn_bridge->gpio_pd_n)) {
ret = gpio_request_one(ptn_bridge->gpio_pd_n,
GPIOF_OUT_INIT_HIGH, "PTN3460_PD_N");
if (ret) {
DRM_ERROR("Request powerdown-gpio failed (%d)\n", ret);
return ret;
}
}
ptn_bridge->gpio_rst_n = of_get_named_gpio(node, "reset-gpio", 0);
if (gpio_is_valid(ptn_bridge->gpio_rst_n)) {
/*
* Request the reset pin low to avoid the bridge being
* initialized prematurely
*/
ret = gpio_request_one(ptn_bridge->gpio_rst_n,
GPIOF_OUT_INIT_LOW, "PTN3460_RST_N");
if (ret) {
DRM_ERROR("Request reset-gpio failed (%d)\n", ret);
gpio_free(ptn_bridge->gpio_pd_n);
return ret;
}
}
ret = of_property_read_u32(node, "edid-emulation",
&ptn_bridge->edid_emulation);
if (ret) {
DRM_ERROR("Can't read edid emulation value\n");
goto err;
}
ret = drm_bridge_init(dev, bridge, &ptn3460_bridge_funcs);
if (ret) {
DRM_ERROR("Failed to initialize bridge with drm\n");
goto err;
}
bridge->driver_private = ptn_bridge;
encoder->bridge = bridge;
ret = drm_connector_init(dev, &ptn_bridge->connector,
&ptn3460_connector_funcs, DRM_MODE_CONNECTOR_LVDS);
if (ret) {
DRM_ERROR("Failed to initialize connector with drm\n");
goto err;
}
drm_connector_helper_add(&ptn_bridge->connector,
&ptn3460_connector_helper_funcs);
drm_connector_register(&ptn_bridge->connector);
drm_mode_connector_attach_encoder(&ptn_bridge->connector, encoder);
return 0;
err:
if (gpio_is_valid(ptn_bridge->gpio_pd_n))
gpio_free(ptn_bridge->gpio_pd_n);
if (gpio_is_valid(ptn_bridge->gpio_rst_n))
gpio_free(ptn_bridge->gpio_rst_n);
return ret;
}
int usb3503_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
{
struct usb3503_platform_data *pdata = i2c->dev.platform_data;
struct device_node *np = i2c->dev.of_node;
struct usb3503 *hub;
int err = -ENOMEM;
u32 mode = USB3503_MODE_UNKNOWN;
hub = kzalloc(sizeof(struct usb3503), GFP_KERNEL);
if (!hub) {
dev_err(&i2c->dev, "private data alloc fail\n");
return err;
}
i2c_set_clientdata(i2c, hub);
hub->client = i2c;
if (pdata) {
hub->gpio_intn = pdata->gpio_intn;
hub->gpio_connect = pdata->gpio_connect;
hub->gpio_reset = pdata->gpio_reset;
hub->mode = pdata->initial_mode;
hub->clk = pdata->ref_clk;
} else if (np) {
hub->gpio_intn = of_get_named_gpio(np, "connect-gpios", 0);
if (hub->gpio_intn == -EPROBE_DEFER)
return -EPROBE_DEFER;
hub->gpio_connect = of_get_named_gpio(np, "intn-gpios", 0);
if (hub->gpio_connect == -EPROBE_DEFER)
return -EPROBE_DEFER;
hub->gpio_reset = of_get_named_gpio(np, "reset-gpios", 0);
if (hub->gpio_reset == -EPROBE_DEFER)
return -EPROBE_DEFER;
of_property_read_u32(np, "initial-mode", &mode);
hub->mode = mode;
}
if (gpio_is_valid(hub->gpio_intn)) {
if(hub->clk == USB3503_REFCLK_24M)
err = gpio_request_one(hub->gpio_intn, GPIOF_OUT_INIT_LOW, "usb3503 intn");
else if(hub->clk == USB3503_REFCLK_26M)
err = gpio_request_one(hub->gpio_intn, GPIOF_OUT_INIT_HIGH, "usb3503 intn");
else
err = gpio_request_one(hub->gpio_intn, GPIOF_OUT_INIT_HIGH, "usb3503 intn");
if (err) {
dev_err(&i2c->dev,
"unable to request GPIO %d as connect pin (%d)\n",
hub->gpio_intn, err);
goto err_out;
}
}
if (gpio_is_valid(hub->gpio_connect)) {
err = gpio_request_one(hub->gpio_connect,
GPIOF_OUT_INIT_HIGH, "usb3503 connect");
if (err) {
dev_err(&i2c->dev,
"unable to request GPIO %d as connect pin (%d)\n",
hub->gpio_connect, err);
goto err_gpio_connect;
}
}
if (gpio_is_valid(hub->gpio_reset)) {
err = gpio_request_one(hub->gpio_reset,
GPIOF_OUT_INIT_LOW, "usb3503 reset");
if (err) {
dev_err(&i2c->dev,
"unable to request GPIO %d as reset pin (%d)\n",
hub->gpio_reset, err);
goto err_gpio_reset;
}
}
usb3503_switch_mode(hub, hub->mode);
dev_info(&i2c->dev, "%s: probed on %s mode\n", __func__,
(hub->mode == USB3503_MODE_HUB) ? "hub" : "standby");
return 0;
err_gpio_reset:
if (gpio_is_valid(hub->gpio_connect))
gpio_free(hub->gpio_connect);
err_gpio_connect:
if (gpio_is_valid(hub->gpio_intn))
gpio_free(hub->gpio_intn);
err_out:
kfree(hub);
return err;
}
static int tegra_wm8903_driver_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct snd_soc_card *card = &snd_soc_tegra_wm8903;
struct tegra_wm8903 *machine;
int ret;
machine = devm_kzalloc(&pdev->dev, sizeof(struct tegra_wm8903),
GFP_KERNEL);
if (!machine) {
dev_err(&pdev->dev, "Can't allocate tegra_wm8903 struct\n");
return -ENOMEM;
}
card->dev = &pdev->dev;
platform_set_drvdata(pdev, card);
snd_soc_card_set_drvdata(card, machine);
machine->gpio_spkr_en = of_get_named_gpio(np, "nvidia,spkr-en-gpios",
0);
if (machine->gpio_spkr_en == -EPROBE_DEFER)
return -EPROBE_DEFER;
if (gpio_is_valid(machine->gpio_spkr_en)) {
ret = devm_gpio_request_one(&pdev->dev, machine->gpio_spkr_en,
GPIOF_OUT_INIT_LOW, "spkr_en");
if (ret) {
dev_err(card->dev, "cannot get spkr_en gpio\n");
return ret;
}
}
machine->gpio_hp_mute = of_get_named_gpio(np, "nvidia,hp-mute-gpios",
0);
if (machine->gpio_hp_mute == -EPROBE_DEFER)
return -EPROBE_DEFER;
if (gpio_is_valid(machine->gpio_hp_mute)) {
ret = devm_gpio_request_one(&pdev->dev, machine->gpio_hp_mute,
GPIOF_OUT_INIT_HIGH, "hp_mute");
if (ret) {
dev_err(card->dev, "cannot get hp_mute gpio\n");
return ret;
}
}
machine->gpio_hp_det = of_get_named_gpio(np, "nvidia,hp-det-gpios", 0);
if (machine->gpio_hp_det == -EPROBE_DEFER)
return -EPROBE_DEFER;
machine->gpio_int_mic_en = of_get_named_gpio(np,
"nvidia,int-mic-en-gpios", 0);
if (machine->gpio_int_mic_en == -EPROBE_DEFER)
return -EPROBE_DEFER;
if (gpio_is_valid(machine->gpio_int_mic_en)) {
/* Disable int mic; enable signal is active-high */
ret = devm_gpio_request_one(&pdev->dev,
machine->gpio_int_mic_en,
GPIOF_OUT_INIT_LOW, "int_mic_en");
if (ret) {
dev_err(card->dev, "cannot get int_mic_en gpio\n");
return ret;
}
}
machine->gpio_ext_mic_en = of_get_named_gpio(np,
"nvidia,ext-mic-en-gpios", 0);
if (machine->gpio_ext_mic_en == -EPROBE_DEFER)
return -EPROBE_DEFER;
if (gpio_is_valid(machine->gpio_ext_mic_en)) {
/* Enable ext mic; enable signal is active-low */
ret = devm_gpio_request_one(&pdev->dev,
machine->gpio_ext_mic_en,
GPIOF_OUT_INIT_LOW, "ext_mic_en");
if (ret) {
dev_err(card->dev, "cannot get ext_mic_en gpio\n");
return ret;
}
}
ret = snd_soc_of_parse_card_name(card, "nvidia,model");
if (ret)
goto err;
ret = snd_soc_of_parse_audio_routing(card, "nvidia,audio-routing");
if (ret)
goto err;
tegra_wm8903_dai.codec_of_node = of_parse_phandle(np,
"nvidia,audio-codec", 0);
if (!tegra_wm8903_dai.codec_of_node) {
dev_err(&pdev->dev,
"Property 'nvidia,audio-codec' missing or invalid\n");
ret = -EINVAL;
goto err;
}
tegra_wm8903_dai.cpu_of_node = of_parse_phandle(np,
"nvidia,i2s-controller", 0);
if (!tegra_wm8903_dai.cpu_of_node) {
dev_err(&pdev->dev,
"Property 'nvidia,i2s-controller' missing or invalid\n");
ret = -EINVAL;
goto err;
}
tegra_wm8903_dai.platform_of_node = tegra_wm8903_dai.cpu_of_node;
ret = tegra_asoc_utils_init(&machine->util_data, &pdev->dev);
if (ret)
goto err;
ret = snd_soc_register_card(card);
if (ret) {
dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
ret);
goto err_fini_utils;
}
return 0;
err_fini_utils:
tegra_asoc_utils_fini(&machine->util_data);
err:
return ret;
}
static int __devinit spi_imx_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
const struct of_device_id *of_id =
of_match_device(spi_imx_dt_ids, &pdev->dev);
struct spi_imx_master *mxc_platform_info =
dev_get_platdata(&pdev->dev);
struct spi_master *master;
struct spi_imx_data *spi_imx;
struct resource *res;
int i, ret, num_cs;
if (!np && !mxc_platform_info) {
dev_err(&pdev->dev, "can't get the platform data\n");
return -EINVAL;
}
ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
if (ret < 0) {
if (mxc_platform_info)
num_cs = mxc_platform_info->num_chipselect;
else
return ret;
}
master = spi_alloc_master(&pdev->dev,
sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
if (!master)
return -ENOMEM;
platform_set_drvdata(pdev, master);
master->bus_num = pdev->id;
master->num_chipselect = num_cs;
spi_imx = spi_master_get_devdata(master);
spi_imx->bitbang.master = spi_master_get(master);
for (i = 0; i < master->num_chipselect; i++) {
int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
if (cs_gpio < 0 && mxc_platform_info)
cs_gpio = mxc_platform_info->chipselect[i];
spi_imx->chipselect[i] = cs_gpio;
if (cs_gpio < 0)
continue;
ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME);
if (ret) {
dev_err(&pdev->dev, "can't get cs gpios\n");
goto out_gpio_free;
}
}
spi_imx->bitbang.chipselect = spi_imx_chipselect;
spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
spi_imx->bitbang.master->setup = spi_imx_setup;
spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
init_completion(&spi_imx->xfer_done);
spi_imx->devtype_data = of_id ? of_id->data :
(struct spi_imx_devtype_data *) pdev->id_entry->driver_data;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "can't get platform resource\n");
ret = -ENOMEM;
goto out_gpio_free;
}
if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
dev_err(&pdev->dev, "request_mem_region failed\n");
ret = -EBUSY;
goto out_gpio_free;
}
spi_imx->base = ioremap(res->start, resource_size(res));
if (!spi_imx->base) {
ret = -EINVAL;
goto out_release_mem;
}
spi_imx->irq = platform_get_irq(pdev, 0);
if (spi_imx->irq < 0) {
ret = -EINVAL;
goto out_iounmap;
}
ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx);
if (ret) {
dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
goto out_iounmap;
}
spi_imx->clk = clk_get(&pdev->dev, NULL);
if (IS_ERR(spi_imx->clk)) {
dev_err(&pdev->dev, "unable to get clock\n");
ret = PTR_ERR(spi_imx->clk);
goto out_free_irq;
}
clk_enable(spi_imx->clk);
spi_imx->spi_clk = clk_get_rate(spi_imx->clk);
spi_imx->devtype_data->reset(spi_imx);
spi_imx->devtype_data->intctrl(spi_imx, 0);
master->dev.of_node = pdev->dev.of_node;
ret = spi_bitbang_start(&spi_imx->bitbang);
if (ret) {
dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
goto out_clk_put;
}
dev_info(&pdev->dev, "probed\n");
return ret;
out_clk_put:
clk_disable(spi_imx->clk);
clk_put(spi_imx->clk);
out_free_irq:
free_irq(spi_imx->irq, spi_imx);
out_iounmap:
iounmap(spi_imx->base);
out_release_mem:
release_mem_region(res->start, resource_size(res));
out_gpio_free:
while (--i >= 0) {
if (spi_imx->chipselect[i] >= 0)
gpio_free(spi_imx->chipselect[i]);
}
spi_master_put(master);
kfree(master);
platform_set_drvdata(pdev, NULL);
return ret;
}