static int of_empty_ranges_quirk(void) { if (IS_ENABLED(CONFIG_PPC)) { /* To save cycles, we cache the result */ static int quirk_state = -1; if (quirk_state < 0) quirk_state = of_machine_is_compatible("Power Macintosh") || of_machine_is_compatible("MacRISC"); return quirk_state; } return false; }
static void board_check_revision(void) { if (of_have_populated_dt()) { if (of_machine_is_compatible("nokia,n800")) board_caps = NOKIA_N800; else if (of_machine_is_compatible("nokia,n810")) board_caps = NOKIA_N810; else if (of_machine_is_compatible("nokia,n810-wimax")) board_caps = NOKIA_N810_WIMAX; } if (!board_caps) pr_err("Unknown board\n"); }
static int __init sun4i_timer_init(struct device_node *node) { int ret; u32 val; ret = timer_of_init(node, &to); if (ret) return ret; writel(~0, timer_of_base(&to) + TIMER_INTVAL_REG(1)); writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD | TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M), timer_of_base(&to) + TIMER_CTL_REG(1)); /* * sched_clock_register does not have priorities, and on sun6i and * later there is a better sched_clock registered by arm_arch_timer.c */ if (of_machine_is_compatible("allwinner,sun4i-a10") || of_machine_is_compatible("allwinner,sun5i-a13") || of_machine_is_compatible("allwinner,sun5i-a10s")) sched_clock_register(sun4i_timer_sched_read, 32, timer_of_rate(&to)); ret = clocksource_mmio_init(timer_of_base(&to) + TIMER_CNTVAL_REG(1), node->name, timer_of_rate(&to), 350, 32, clocksource_mmio_readl_down); if (ret) { pr_err("Failed to register clocksource\n"); return ret; } writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M), timer_of_base(&to) + TIMER_CTL_REG(0)); /* Make sure timer is stopped before playing with interrupts */ sun4i_clkevt_time_stop(timer_of_base(&to), 0); /* clear timer0 interrupt */ sun4i_timer_clear_interrupt(timer_of_base(&to)); clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), TIMER_SYNC_TICKS, 0xffffffff); /* Enable timer0 interrupt */ val = readl(timer_of_base(&to) + TIMER_IRQ_EN_REG); writel(val | TIMER_IRQ_EN(0), timer_of_base(&to) + TIMER_IRQ_EN_REG); return ret; }
static int wandboard_device_init(void) { if (!of_machine_is_compatible("wand,imx6dl-wandboard") && !of_machine_is_compatible("wand,imx6q-wandboard")) return 0; phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK, ar8031_phy_fixup); barebox_set_hostname("wandboard"); imx6_bbu_internal_mmc_register_handler("mmc", "/dev/mmc2.barebox", BBU_HANDLER_FLAG_DEFAULT); return 0; }
static int sabrelite_devices_init(void) { if (!of_machine_is_compatible("fsl,imx6q-sabrelite") && !of_machine_is_compatible("fsl,imx6dl-sabrelite")) return 0; sabrelite_ehci_init(); armlinux_set_architecture(3769); imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox", BBU_HANDLER_FLAG_DEFAULT); return 0; }
static void __init omap_generic_init(void) { omap_sdrc_init(NULL, NULL); of_platform_populate(NULL, omap_dt_match_table, NULL, NULL); /* * HACK: call display setup code for selected boards to enable omapdss. * This will be removed when omapdss supports DT. */ if (of_machine_is_compatible("ti,omap4-panda")) omap4_panda_display_init_of(); else if (of_machine_is_compatible("ti,omap4-sdp")) omap_4430sdp_display_init_of(); }
unsigned int hwid_map(void) { int i, hwid_logic=0; int rc=-1; for(i=0; i<ARRAY_SIZE(HWID_GPIO); i++) { hwid_logic +=( ( !!__gpio_get_value(HWID_GPIO[i].gpio) ) << i ); } pr_info("HWID_LOGIC 0x%x\r\n",hwid_logic); if(of_machine_is_compatible("qcom,msm8916")) { HWID_MAP=HWID_MAP_8916; pr_info("CPU 8916 HWID MAP\r\n"); } else if (of_machine_is_compatible("qcom,msm8936")) { HWID_MAP=HWID_MAP_8936; pr_info("CPU 8936 HWID MAP\r\n"); } else if (of_machine_is_compatible("qcom,msm8939")) { HWID_MAP=HWID_MAP_8936; //use 8936 HWID MAP replace pr_info("CPU 8939 HWID MAP\r\n"); } else { HWID_MAP=HWID_MAP_8936; pr_info("use default CPU 8936 HWID MAP\r\n"); } for(i=0; HWID_MAP[i].HWID_LOGIC!=0xff; i++) { if(hwid_logic==HWID_MAP[i].HWID_LOGIC) { FIH_PROJECT_ID = HWID_MAP[i].PROJECT; FIH_BAND_ID = HWID_MAP[i].BAND; FIH_PHASE_ID = HWID_MAP[i].PHASE; FIH_SIM_ID = HWID_MAP[i].SIM; rc=0; break; } } return rc; }
static int __init ep405_probe(void) { if (!of_machine_is_compatible("ep405")) return 0; return 1; }
static __init int efika_fabric_init(void) { struct platform_device *pdev; int rc; if (!of_machine_is_compatible("bplan,efika")) return -ENODEV; card.name = "Efika"; card.dai_link = efika_fabric_dai; card.num_links = ARRAY_SIZE(efika_fabric_dai); pdev = platform_device_alloc("soc-audio", 1); if (!pdev) { pr_err("efika_fabric_init: platform_device_alloc() failed\n"); return -ENODEV; } platform_set_drvdata(pdev, &card); rc = platform_device_add(pdev); if (rc) { pr_err("efika_fabric_init: platform_device_add() failed\n"); platform_device_put(pdev); return -ENODEV; } return 0; }
static void *ocram_init_mem(size_t size, void **other) { struct device_node *np; struct gen_pool *gp; void *sram_addr; const char *compat = "altr,ocram-edac"; if (of_machine_is_compatible("altr,socfpga-arria10")) compat = "altr,a10-ocram-edac"; np = of_find_compatible_node(NULL, NULL, compat); if (!np) return NULL; gp = of_gen_pool_get(np, "iram", 0); if (!gp) return NULL; *other = gp; sram_addr = (void *)gen_pool_alloc(gp, size); if (!sram_addr) return NULL; memset(sram_addr, 0, size); wmb(); /* Ensure data is written out */ return sram_addr; }
/* * altr_ocram_dependencies() * Test for OCRAM ECC dependencies upon entry because * the kernel startup code should have initialized the OCRAM * memory and enabled the ECC. * Fail if ECC is not on. * Test for OCRAM ECC is enabled. */ static int altr_ocram_dependencies(struct platform_device *pdev, void __iomem *base) { u32 control; void __iomem *en_addr; u32 en_mask; if (of_machine_is_compatible("altr,socfpga-arria10")) { en_addr = (void __iomem *)((uintptr_t)base + ALTR_A10_OCR_ECC_CTL_OFFSET); en_mask = ALTR_A10_OCR_ECC_EN_CTL_MASK; } else { en_addr = (void __iomem *)((uintptr_t)base + ALTR_MAN_GRP_OCRAM_ECC_OFFSET); en_mask = ALTR_OCR_ECC_EN_MASK; } control = readl(en_addr) & en_mask; if (!control) { dev_err(&pdev->dev, "OCRAM: No ECC present, or ECC disabled\n"); return -ENODEV; } return 0; }
/* * Called very early, device-tree isn't unflattened */ static int __init sbc8641_probe(void) { if (of_machine_is_compatible("wind,sbc8641")) return 1; /* Looks good */ return 0; }
static int tx6x_devices_init(void) { if (!of_machine_is_compatible("karo,imx6dl-tx6dl") && !of_machine_is_compatible("karo,imx6q-tx6q")) return 0; barebox_set_hostname("tx6u"); eth_init(); setup_pmic_voltages(); imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT); return 0; }
static int __init hvc_beat_console_init(void) { if (hvc_beat_useit && of_machine_is_compatible("Beat")) { hvc_instantiate(0, 0, &hvc_beat_get_put_ops); } return 0; }
static void __init orion5x_dt_init(void) { char *dev_name; u32 dev, rev; orion5x_id(&dev, &rev, &dev_name); printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); /* * Setup Orion address map */ orion5x_setup_cpu_mbus_bridge(); /* Setup root of clk tree */ clk_init(); /* * Don't issue "Wait for Interrupt" instruction if we are * running on D0 5281 silicon. */ if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) { printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n"); disable_hlt(); } if (of_machine_is_compatible("lacie,ethernet-disk-mini-v2")) edmini_v2_init(); of_platform_populate(NULL, of_default_bus_match_table, orion5x_auxdata_lookup, NULL); }
/* * Called very early, device-tree isn't unflattened * * This function is called to determine whether the BSP is compatible with the * supplied device-tree, which is assumed to be the correct one for the actual * board. It is expected thati, in the future, a kernel may support multiple * boards. */ static int __init gef_sbc610_probe(void) { if (of_machine_is_compatible("gef,sbc610")) return 1; return 0; }
void __init mpc85xx_rdb_pic_init(void) { struct mpic *mpic; #ifdef CONFIG_QUICC_ENGINE struct device_node *np; #endif if (of_machine_is_compatible("fsl,MPC85XXRDB-CAMP")) { mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET | MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU, 0, 256, " OpenPIC "); } else { mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU, 0, 256, " OpenPIC "); } BUG_ON(mpic == NULL); mpic_init(mpic); #ifdef CONFIG_QUICC_ENGINE np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); if (np) { qe_ic_init(np, 0, qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic); of_node_put(np); } else pr_err("%s: Could not find qe-ic node\n", __func__); #endif }
static int hummingboard_device_init(void) { if (!of_machine_is_compatible("solidrun,hummingboard/dl") && !of_machine_is_compatible("solidrun,hummingboard/q")) return 0; microsom_eth_init(); /* enable USB VBUS */ gpio_direction_output(IMX_GPIO_NR(3, 22), 1); gpio_direction_output(IMX_GPIO_NR(1, 0), 1); barebox_set_hostname("hummingboard"); return 0; }
int __init ardbeg_sdhci_init(void) { int nominal_core_mv; int min_vcore_override_mv; int boot_vcore_mv; struct board_info board_info; nominal_core_mv = tegra_dvfs_rail_get_nominal_millivolts(tegra_core_rail); if (nominal_core_mv) { tegra_sdhci_platform_data0.nominal_vcore_mv = nominal_core_mv; tegra_sdhci_platform_data2.nominal_vcore_mv = nominal_core_mv; tegra_sdhci_platform_data3.nominal_vcore_mv = nominal_core_mv; } min_vcore_override_mv = tegra_dvfs_rail_get_override_floor(tegra_core_rail); if (min_vcore_override_mv) { tegra_sdhci_platform_data0.min_vcore_override_mv = min_vcore_override_mv; tegra_sdhci_platform_data2.min_vcore_override_mv = min_vcore_override_mv; tegra_sdhci_platform_data3.min_vcore_override_mv = min_vcore_override_mv; } boot_vcore_mv = tegra_dvfs_rail_get_boot_level(tegra_core_rail); if (boot_vcore_mv) { tegra_sdhci_platform_data0.boot_vcore_mv = boot_vcore_mv; tegra_sdhci_platform_data2.boot_vcore_mv = boot_vcore_mv; tegra_sdhci_platform_data3.boot_vcore_mv = boot_vcore_mv; } if (of_machine_is_compatible("nvidia,laguna")) tegra_sdhci_platform_data2.wp_gpio = ARDBEG_SD_WP; tegra_get_board_info(&board_info); if (board_info.board_id == BOARD_E1780) { tegra_sdhci_platform_data3.max_clk_limit = 200000000; tegra_sdhci_platform_data2.max_clk_limit = 204000000; tegra_sdhci_platform_data0.max_clk_limit = 204000000; } else { tegra_sdhci_platform_data3.uhs_mask = MMC_MASK_HS200; } if (board_info.board_id == BOARD_PM374 || board_info.board_id == BOARD_PM358 || board_info.board_id == BOARD_PM363 || board_info.board_id == BOARD_PM359) tegra_sdhci_platform_data0.disable_clock_gate = 1; platform_device_register(&tegra_sdhci_device3); platform_device_register(&tegra_sdhci_device2); if (board_info.board_id != BOARD_PM359 && board_info.board_id != BOARD_PM375 && board_info.board_id != BOARD_PM377) { platform_device_register(&tegra_sdhci_device0); ardbeg_wifi_init(); } return 0; }
static int mt8173_cpufreq_driver_init(void) { struct platform_device *pdev; int err; if (!of_machine_is_compatible("mediatek,mt8173")) return -ENODEV; err = platform_driver_register(&mt8173_cpufreq_platdrv); if (err) return err; /* * Since there's no place to hold device registration code and no * device tree based way to match cpufreq driver yet, both the driver * and the device registration codes are put here to handle defer * probing. */ pdev = platform_device_register_simple("mt8173-cpufreq", -1, NULL, 0); if (IS_ERR(pdev)) { pr_err("failed to register mtk-cpufreq platform device\n"); return PTR_ERR(pdev); } return 0; }
static int realq7_device_init(void) { if (!of_machine_is_compatible("dmo,imx6q-edmqmx6")) return 0; gpio_direction_output(IMX_GPIO_NR(2, 22), 1); gpio_direction_output(IMX_GPIO_NR(2, 21), 1); switch (bootsource_get()) { case BOOTSOURCE_MMC: switch (bootsource_get_instance()) { case 2: of_device_enable_path("/chosen/environment-sd"); break; case 3: of_device_enable_path("/chosen/environment-emmc"); break; } break; default: case BOOTSOURCE_SPI: of_device_enable_path("/chosen/environment-spi"); break; } return 0; }
static int __init nsa310_pci_init(void) { if (of_machine_is_compatible("zyxel,nsa310")) kirkwood_pcie_init(KW_PCIE0); return 0; }
static int e9_devices_init(void) { int ret; char *environment_path; if (!of_machine_is_compatible("embedsky,e9")) return 0; armlinux_set_architecture(3980); environment_path = basprintf("/chosen/environment-mmc%d", bootsource_get_instance()); ret = of_device_enable_path(environment_path); if (ret < 0) pr_warn("Failed to enable environment partition '%s' (%d)\n", environment_path, ret); free(environment_path); defaultenv_append_directory(defaultenv_e9); imx6_bbu_internal_mmc_register_handler("sd", "/dev/mmc1", BBU_HANDLER_FLAG_DEFAULT); imx6_bbu_internal_mmc_register_handler("emmc", "/dev/mmc3", BBU_HANDLER_FLAG_DEFAULT); return 0; }
/* * Called very early, device-tree isn't unflattened * * This function is called to determine whether the BSP is compatible with the * supplied device-tree, which is assumed to be the correct one for the actual * board. It is expected thati, in the future, a kernel may support multiple * boards. */ static int __init gef_ppc9a_probe(void) { if (of_machine_is_compatible("gef,ppc9a")) return 1; return 0; }
static int beaglebone_devices_init(void) { int black; if (!of_machine_is_compatible("ti,am335x-bone")) return 0; if (bootsource_get() == BOOTSOURCE_MMC) { if (bootsource_get_instance() == 0) omap_set_bootmmc_devname("mmc0"); else omap_set_bootmmc_devname("mmc1"); } black = is_beaglebone_black(); defaultenv_append_directory(defaultenv_beaglebone); globalvar_add_simple("board.variant", black ? "boneblack" : "bone"); printf("detected 'BeagleBone %s'\n", black ? "Black" : "White"); armlinux_set_architecture(MACH_TYPE_BEAGLEBONE); /* Register update handler */ am33xx_bbu_emmc_mlo_register_handler("MLO.emmc", "/dev/mmc1"); if (IS_ENABLED(CONFIG_SHELL_NONE)) return am33xx_of_register_bootdevice(); return 0; }
static int __cpuinit mvebu_cortex_a9_boot_secondary(unsigned int cpu, struct task_struct *idle) { int ret, hw_cpu; pr_info("Booting CPU %d\n", cpu); /* * Write the address of secondary startup into the system-wide * flags register. The boot monitor waits until it receives a * soft interrupt, and then the secondary CPU branches to this * address. */ hw_cpu = cpu_logical_map(cpu); if (of_machine_is_compatible("marvell,armada375")) mvebu_system_controller_set_cpu_boot_addr(mvebu_cortex_a9_secondary_startup); else mvebu_pmsu_set_cpu_boot_addr(hw_cpu, mvebu_cortex_a9_secondary_startup); smp_wmb(); /* * Doing this before deasserting the CPUs is needed to wake up CPUs * in the offline state after using CPU hotplug. */ arch_send_wakeup_ipi_mask(cpumask_of(cpu)); ret = mvebu_cpu_reset_deassert(hw_cpu); if (ret) { pr_err("Could not start the secondary CPU: %d\n", ret); return ret; } return 0; }
static int beaglebone_devices_init(void) { int black; if (!of_machine_is_compatible("ti,am335x-bone")) return 0; if (bootsource_get() == BOOTSOURCE_MMC) { if (bootsource_get_instance() == 0) omap_set_bootmmc_devname("mmc0"); else omap_set_bootmmc_devname("mmc1"); } black = is_beaglebone_black(); defaultenv_append_directory(defaultenv_beaglebone); globalvar_add_simple("board.variant", black ? "boneblack" : "bone"); printf("detected 'BeagleBone %s'\n", black ? "Black" : "White"); armlinux_set_architecture(MACH_TYPE_BEAGLEBONE); return 0; }
static void __init orion5x_dt_init(void) { char *dev_name; u32 dev, rev; orion5x_id(&dev, &rev, &dev_name); printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); BUG_ON(mvebu_mbus_dt_init(false)); /* * Setup Orion address map */ orion5x_setup_wins(); /* * Don't issue "Wait for Interrupt" instruction if we are * running on D0 5281 silicon. */ if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) { printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n"); cpu_idle_poll_ctrl(true); } if (of_machine_is_compatible("maxtor,shared-storage-2")) mss2_init(); of_platform_populate(NULL, of_default_bus_match_table, orion5x_auxdata_lookup, NULL); }
static __init int efika_fabric_init(void) { struct platform_device *pdev; int rc; if (!of_machine_is_compatible("bplan,efika")) return -ENODEV; card.platform = &mpc5200_audio_dma_platform; card.name = "Efika"; card.dai_link = efika_fabric_dai; card.num_links = ARRAY_SIZE(efika_fabric_dai); device.card = &card; device.codec_dev = &soc_codec_dev_stac9766; pdev = platform_device_alloc("soc-audio", 1); if (!pdev) { pr_err("efika_fabric_init: platform_device_alloc() failed\n"); return -ENODEV; } platform_set_drvdata(pdev, &device); device.dev = &pdev->dev; rc = platform_device_add(pdev); if (rc) { pr_err("efika_fabric_init: platform_device_add() failed\n"); return -ENODEV; } return 0; }
static int __init wf_pm112_init(void) { struct device_node *cpu; if (!of_machine_is_compatible("PowerMac11,2")) return -ENODEV; /* Count the number of CPU cores */ nr_cores = 0; for (cpu = NULL; (cpu = of_find_node_by_type(cpu, "cpu")) != NULL; ) ++nr_cores; ; #ifdef MODULE request_module("windfarm_smu_controls"); request_module("windfarm_smu_sensors"); request_module("windfarm_smu_sat"); request_module("windfarm_lm75_sensor"); request_module("windfarm_max6690_sensor"); request_module("windfarm_cpufreq_clamp"); #endif /* MODULE */ platform_driver_register(&wf_pm112_driver); return 0; }