static int mpc8xxx_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct mpc8xxx_gpio_chip *mpc8xxx_gc;
struct of_mm_gpio_chip *mm_gc;
struct gpio_chip *gc;
const struct of_device_id *id;
int ret;
mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
if (!mpc8xxx_gc)
return -ENOMEM;
platform_set_drvdata(pdev, mpc8xxx_gc);
spin_lock_init(&mpc8xxx_gc->lock);
mm_gc = &mpc8xxx_gc->mm_gc;
gc = &mm_gc->gc;
mm_gc->save_regs = mpc8xxx_gpio_save_regs;
gc->ngpio = MPC8XXX_GPIO_PINS;
gc->direction_input = mpc8xxx_gpio_dir_in;
gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ?
mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out;
gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ?
mpc8572_gpio_get : mpc8xxx_gpio_get;
gc->set = mpc8xxx_gpio_set;
gc->set_multiple = mpc8xxx_gpio_set_multiple;
gc->to_irq = mpc8xxx_gpio_to_irq;
ret = of_mm_gpiochip_add(np, mm_gc);
if (ret)
return ret;
mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
if (mpc8xxx_gc->irqn == NO_IRQ)
return 0;
mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
&mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
if (!mpc8xxx_gc->irq)
return 0;
id = of_match_node(mpc8xxx_gpio_ids, np);
if (id)
mpc8xxx_gc->of_dev_id_data = id->data;
/* ack and mask all irqs */
out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
out_be32(mm_gc->regs + GPIO_IMR, 0);
irq_set_handler_data(mpc8xxx_gc->irqn, mpc8xxx_gc);
irq_set_chained_handler(mpc8xxx_gc->irqn, mpc8xxx_gpio_irq_cascade);
return 0;
}
static int __devinit milkymist_gpio_probe(struct platform_device *ofdev)
{
struct device_node *np = ofdev->dev.of_node;
struct milkymist_gpio_chip *chip;
int ret;
const unsigned int *num_gpi, *num_gpo;
num_gpi = of_get_property(np, "num-gpi", NULL);
if (!num_gpi) {
dev_err(&ofdev->dev, "no num-gpi property set\n");
return -ENODEV;
}
num_gpo = of_get_property(np, "num-gpo", NULL);
if (!num_gpi) {
dev_err(&ofdev->dev, "no num-gpo property set\n");
return -ENODEV;
}
if (*num_gpi == 0 && *num_gpo == 0) {
dev_err(&ofdev->dev, "invalid number of gpios\n");
return -ENODEV;
}
chip = kzalloc(sizeof(*chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
chip->mm_gc.gc.direction_input = milkymist_gpio_direction_input;
chip->mm_gc.gc.direction_output = milkymist_gpio_direction_output;
chip->mm_gc.gc.get = milkymist_gpio_get;
chip->mm_gc.gc.set = milkymist_gpio_set;
chip->mm_gc.gc.ngpio = *num_gpi + *num_gpo;
chip->num_gpi = *num_gpi;
chip->num_gpo = *num_gpo;
ret = of_mm_gpiochip_add(np, &chip->mm_gc);
if (ret) {
dev_err(&ofdev->dev, "error in probe function with status %d\n",
ret);
goto err;
}
platform_set_drvdata(ofdev, chip);
dev_info(&ofdev->dev, "registered\n");
return 0;
err:
kfree(chip);
return ret;
}
static void __init mpc8xxx_add_controller(struct device_node *np)
{
struct mpc8xxx_gpio_chip *mpc8xxx_gc;
struct of_mm_gpio_chip *mm_gc;
struct of_gpio_chip *of_gc;
struct gpio_chip *gc;
int ret;
mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
if (!mpc8xxx_gc) {
ret = -ENOMEM;
goto err;
}
spin_lock_init(&mpc8xxx_gc->lock);
mm_gc = &mpc8xxx_gc->mm_gc;
of_gc = &mm_gc->of_gc;
gc = &of_gc->gc;
mm_gc->save_regs = mpc8xxx_gpio_save_regs;
of_gc->gpio_cells = 2;
gc->ngpio = MPC8XXX_GPIO_PINS;
gc->direction_input = mpc8xxx_gpio_dir_in;
gc->direction_output = mpc8xxx_gpio_dir_out;
if (of_device_is_compatible(np, "fsl,mpc8572-gpio"))
gc->get = mpc8572_gpio_get;
else
gc->get = mpc8xxx_gpio_get;
gc->set = mpc8xxx_gpio_set;
ret = of_mm_gpiochip_add(np, mm_gc);
if (ret)
goto err;
return;
err:
pr_err("%s: registration failed with status %d\n",
np->full_name, ret);
kfree(mpc8xxx_gc);
return;
}
static int __init gef_gpio_probe(struct platform_device *pdev)
{
const struct of_device_id *of_id =
of_match_device(gef_gpio_ids, &pdev->dev);
struct of_mm_gpio_chip *mmchip;
mmchip = devm_kzalloc(&pdev->dev, sizeof(*mmchip), GFP_KERNEL);
if (!mmchip)
return -ENOMEM;
/* Setup pointers to chip functions */
mmchip->gc.ngpio = (u16)(uintptr_t)of_id->data;
mmchip->gc.of_gpio_n_cells = 2;
mmchip->gc.direction_input = gef_gpio_dir_in;
mmchip->gc.direction_output = gef_gpio_dir_out;
mmchip->gc.get = gef_gpio_get;
mmchip->gc.set = gef_gpio_set;
/* This function adds a memory mapped GPIO chip */
return of_mm_gpiochip_add(pdev->dev.of_node, mmchip);
};
static void __init mpc8xxx_add_controller(struct device_node *np)
{
struct mpc8xxx_gpio_chip *mpc8xxx_gc;
struct of_mm_gpio_chip *mm_gc;
struct gpio_chip *gc;
const struct of_device_id *id;
unsigned hwirq;
int ret;
mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
if (!mpc8xxx_gc) {
ret = -ENOMEM;
goto err;
}
spin_lock_init(&mpc8xxx_gc->lock);
mm_gc = &mpc8xxx_gc->mm_gc;
gc = &mm_gc->gc;
mm_gc->save_regs = mpc8xxx_gpio_save_regs;
gc->ngpio = MPC8XXX_GPIO_PINS;
gc->direction_input = mpc8xxx_gpio_dir_in;
gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ?
mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out;
gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ?
mpc8572_gpio_get : mpc8xxx_gpio_get;
gc->set = mpc8xxx_gpio_set;
gc->to_irq = mpc8xxx_gpio_to_irq;
ret = of_mm_gpiochip_add(np, mm_gc);
if (ret)
goto err;
hwirq = irq_of_parse_and_map(np, 0);
if (hwirq == NO_IRQ)
goto skip_irq;
mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
&mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
if (!mpc8xxx_gc->irq)
goto skip_irq;
id = of_match_node(mpc8xxx_gpio_ids, np);
if (id)
mpc8xxx_gc->of_dev_id_data = id->data;
/* ack and mask all irqs */
out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
out_be32(mm_gc->regs + GPIO_IMR, 0);
irq_set_handler_data(hwirq, mpc8xxx_gc);
irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
skip_irq:
return;
err:
pr_err("%s: registration failed with status %d\n",
np->full_name, ret);
kfree(mpc8xxx_gc);
return;
}
/**
* xgpio_of_probe - Probe method for the GPIO device.
* @pdev: pointer to the platform device
*
* Return:
* It returns 0, if the driver is bound to the GPIO device, or
* a negative value if there is an error.
*/
static int xgpio_probe(struct platform_device *pdev)
{
struct xgpio_instance *chip;
int status = 0;
struct device_node *np = pdev->dev.of_node;
u32 is_dual;
chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
platform_set_drvdata(pdev, chip);
/* Update GPIO state shadow register with default value */
of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state[0]);
/* Update GPIO direction shadow register with default value */
if (of_property_read_u32(np, "xlnx,tri-default", &chip->gpio_dir[0]))
chip->gpio_dir[0] = 0xFFFFFFFF;
/*
* Check device node and parent device node for device width
* and assume default width of 32
*/
if (of_property_read_u32(np, "xlnx,gpio-width", &chip->gpio_width[0]))
chip->gpio_width[0] = 32;
spin_lock_init(&chip->gpio_lock[0]);
if (of_property_read_u32(np, "xlnx,is-dual", &is_dual))
is_dual = 0;
if (is_dual) {
/* Update GPIO state shadow register with default value */
of_property_read_u32(np, "xlnx,dout-default-2",
&chip->gpio_state[1]);
/* Update GPIO direction shadow register with default value */
if (of_property_read_u32(np, "xlnx,tri-default-2",
&chip->gpio_dir[1]))
chip->gpio_dir[1] = 0xFFFFFFFF;
/*
* Check device node and parent device node for device width
* and assume default width of 32
*/
if (of_property_read_u32(np, "xlnx,gpio2-width",
&chip->gpio_width[1]))
chip->gpio_width[1] = 32;
spin_lock_init(&chip->gpio_lock[1]);
}
chip->mmchip.gc.ngpio = chip->gpio_width[0] + chip->gpio_width[1];
chip->mmchip.gc.parent = &pdev->dev;
chip->mmchip.gc.direction_input = xgpio_dir_in;
chip->mmchip.gc.direction_output = xgpio_dir_out;
chip->mmchip.gc.get = xgpio_get;
chip->mmchip.gc.set = xgpio_set;
chip->mmchip.save_regs = xgpio_save_regs;
/* Call the OF gpio helper to setup and register the GPIO device */
status = of_mm_gpiochip_add(np, &chip->mmchip);
if (status) {
pr_err("%s: error in probe function with status %d\n",
np->full_name, status);
return status;
}
return 0;
}
int __devinit altera_gpio_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
int id, reg, ret;
struct altera_gpio_chip *altera_gc = devm_kzalloc(&pdev->dev,
sizeof(*altera_gc), GFP_KERNEL);
if (altera_gc == NULL) {
ret = -ENOMEM;
pr_err("%s: registration failed with status %d\n",
node->full_name, ret);
return ret;
}
altera_gc->irq = 0;
spin_lock_init(&altera_gc->gpio_lock);
id = pdev->id;
if (of_property_read_u32(node, "width", ®))
/*By default assume full GPIO controller*/
altera_gc->mmchip.gc.ngpio = 32;
else
altera_gc->mmchip.gc.ngpio = reg;
if (altera_gc->mmchip.gc.ngpio > 32) {
pr_warn("%s: ngpio is greater than 32, defaulting to 32\n",
node->full_name);
altera_gc->mmchip.gc.ngpio = 32;
}
altera_gc->mmchip.gc.direction_input = altera_gpio_direction_input;
altera_gc->mmchip.gc.direction_output = altera_gpio_direction_output;
altera_gc->mmchip.gc.get = altera_gpio_get;
altera_gc->mmchip.gc.set = altera_gpio_set;
altera_gc->mmchip.gc.to_irq = altera_gpio_to_irq;
altera_gc->mmchip.gc.owner = THIS_MODULE;
ret = of_mm_gpiochip_add(node, &altera_gc->mmchip);
if (ret)
goto err;
platform_set_drvdata(pdev, altera_gc);
if (of_get_property(node, "interrupts", ®) == NULL)
goto skip_irq;
altera_gc->hwirq = irq_of_parse_and_map(node, 0);
if (altera_gc->hwirq == NO_IRQ)
goto skip_irq;
altera_gc->irq = irq_domain_add_linear(node, altera_gc->mmchip.gc.ngpio,
&altera_gpio_irq_ops, altera_gc);
if (!altera_gc->irq) {
ret = -ENODEV;
goto dispose_irq;
}
if (of_property_read_u32(node, "level_trigger", ®)) {
ret = -EINVAL;
pr_err("%s: level_trigger value not set in device tree\n",
node->full_name);
goto teardown;
}
altera_gc->level_trigger = reg;
irq_set_handler_data(altera_gc->hwirq, altera_gc);
irq_set_chained_handler(altera_gc->hwirq, altera_gpio_irq_handler);
return 0;
teardown:
irq_domain_remove(altera_gc->irq);
dispose_irq:
irq_dispose_mapping(altera_gc->hwirq);
WARN_ON(gpiochip_remove(&altera_gc->mmchip.gc) < 0);
err:
pr_err("%s: registration failed with status %d\n",
node->full_name, ret);
devm_kfree(&pdev->dev, altera_gc);
return ret;
skip_irq:
return 0;
}
