void
ofw_cacheclean_init(void)
{
/*
* Get the physical address of the clean area.
*/
if ((arm32_cache_clean_addr = ofw_getcleaninfo()) == -1)
panic("ofw_paging_init: Could not get clean info");
arm32_cache_clean_size = 0x4000;
/*
* Create an ofw equiv mapping for it. It must be cacheable or
* bufferable, which is what makes it the "clean" space.
*/
ofw_physmap(arm32_cache_clean_addr, arm32_cache_clean_size, 0);
DPRINTF("VIRT->PHYS: "
"virt:0x%x phys:0x%x size:0x%x\n",
arm32_cache_clean_addr, arm32_cache_clean_addr,
arm32_cache_clean_size);
}
u_int
initarm(void *arg)
{
ofw_handle_t ofw_handle = arg;
paddr_t pclean;
vaddr_t isa_io_virtaddr, isa_mem_virtaddr;
paddr_t isadmaphysbufs;
extern char shark_fiq[], shark_fiq_end[];
/* Don't want to get hit with interrupts 'til we're ready. */
(void)disable_interrupts(I32_bit | F32_bit);
set_cpufuncs();
/* XXX - set these somewhere else? -JJK */
boothowto = 0;
/* Init the OFW interface. */
/* MUST do this before invoking any OFW client services! */
ofw_init(ofw_handle);
/* Configure ISA stuff: must be done before consinit */
ofw_configisa(&isa_io_physaddr, &isa_mem_physaddr);
/* Map-in ISA I/O and memory space. */
/* XXX - this should be done in the isa-bus attach routine! -JJK */
isa_mem_virtaddr = ofw_map(isa_mem_physaddr, L1_S_SIZE, 0);
isa_io_virtaddr = ofw_map(isa_io_physaddr, L1_S_SIZE, 0);
/* Set-up the ISA system: must be done before consinit */
isa_init(isa_io_virtaddr, isa_mem_virtaddr);
/* Initialize the console (which will call into OFW). */
/* This will allow us to see panic messages and other printf output. */
consinit();
/* Get boot info and process it. */
ofw_getbootinfo(&boot_file, &boot_args);
process_kernel_args();
ofw_configisadma(&isadmaphysbufs);
#if (NISADMA > 0)
isa_dma_init();
#endif
/* allocate a cache clean space */
if ((pclean = ofw_getcleaninfo()) != -1) {
sa1_cache_clean_addr = ofw_map(pclean, 0x4000 * 2,
L2_B | L2_C);
sa1_cache_clean_size = 0x4000;
}
/* Configure memory. */
ofw_configmem();
/*
* Set-up stacks.
* The kernel stack for SVC mode will be updated on return
* from this routine.
*/
set_stackptr(PSR_IRQ32_MODE, irqstack.pv_va + PAGE_SIZE);
set_stackptr(PSR_UND32_MODE, undstack.pv_va + PAGE_SIZE);
set_stackptr(PSR_ABT32_MODE, abtstack.pv_va + PAGE_SIZE);
/* Set-up exception handlers. */
/*
* Take control of selected vectors from OFW.
* We take: undefined, swi, pre-fetch abort, data abort, addrexc,
* irq, fiq
* OFW retains: reset
*/
arm32_vector_init(ARM_VECTORS_LOW, ARM_VEC_ALL & ~ARM_VEC_RESET);
data_abort_handler_address = (u_int)data_abort_handler;
prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
undefined_handler_address =
(u_int)undefinedinstruction_bounce; /* why is this needed? -JJK */
/* Initialise the undefined instruction handlers. */
undefined_init();
/* Now for the SHARK-specific part of the FIQ set-up */
shark_fiqhandler.fh_func = shark_fiq;
shark_fiqhandler.fh_size = shark_fiq_end - shark_fiq;
shark_fiqhandler.fh_flags = 0;
shark_fiqhandler.fh_regs = &shark_fiqregs;
shark_fiqregs.fr_r8 = isa_io_virtaddr;
shark_fiqregs.fr_r9 = 0; /* no routine right now */
shark_fiqregs.fr_r10 = 0; /* no arg right now */
shark_fiqregs.fr_r11 = 0; /* scratch */
shark_fiqregs.fr_r12 = 0; /* scratch */
shark_fiqregs.fr_r13 = 0; /* must set a stack when r9 is set! */
if (fiq_claim(&shark_fiqhandler))
panic("Cannot claim FIQ vector.");
#if NKSYMS || defined(DDB) || defined(MODULAR)
#ifndef __ELF__
{
struct exec *kernexec = (struct exec *)KERNEL_TEXT_BASE;
extern int end;
extern char *esym;
ksyms_addsyms_elf(kernexec->a_syms, &end, esym);
}
#endif /* __ELF__ */
#endif /* NKSYMS || defined(DDB) || defined(MODULAR) */
#ifdef DDB
db_machine_init();
if (boothowto & RB_KDB)
Debugger();
#endif
/* Return the new stackbase. */
return(kernelstack.pv_va + USPACE_SVC_STACK_TOP);
}
