int omap2_dflt_clk_enable(struct clk *clk) { u32 v; if (unlikely(clk->enable_reg == NULL)) { pr_err("clock.c: Enable for %s without enable code\n", clk->name); return 0; /* REVISIT: -EINVAL */ } #if 0 if (clk->enable_reg == OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN)) { printk("%s:%d regval %08x bit %d\n", __FUNCTION__, __LINE__, __raw_readl(clk->enable_reg), clk->enable_bit); if (clk->enable_bit == OMAP3430_EN_MCBSP2_SHIFT) dump_stack(); } #endif v = __raw_readl(clk->enable_reg); if (clk->flags & INVERT_ENABLE) v &= ~(1 << clk->enable_bit); else v |= (1 << clk->enable_bit); __raw_writel(v, clk->enable_reg); v = __raw_readl(clk->enable_reg); /* OCP barrier */ if (clk->ops->find_idlest) omap2_module_wait_ready(clk); return 0; }
int omap2_dflt_clk_enable(struct clk *clk) { u32 v; if (unlikely(clk->enable_reg == NULL)) { pr_err("clock.c: Enable for %s without enable code\n", clk->name); return 0; } v = __raw_readl(clk->enable_reg); if (clk->flags & INVERT_ENABLE) v &= ~(1 << clk->enable_bit); else v |= (1 << clk->enable_bit); __raw_writel(v, clk->enable_reg); v = __raw_readl(clk->enable_reg); if (clk->ops->find_idlest) omap2_module_wait_ready(clk); return 0; }