/** * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider * @clk: struct clk * of DPLL to set * @rate: rounded target rate * * Program the DPLL M2 divider with the rounded target rate. Returns * -EINVAL upon error, or 0 upon success. */ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) { u32 new_div = 0; unsigned long validrate, sdrcrate; struct omap_sdrc_params *sp; if (!clk || !rate) return -EINVAL; if (clk != &dpll3_m2_ck) return -EINVAL; if (rate == clk->rate) return 0; validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); if (validrate != rate) return -EINVAL; sdrcrate = sdrc_ick.rate; if (rate > clk->rate) sdrcrate <<= ((rate / clk->rate) - 1); else sdrcrate >>= ((clk->rate / rate) - 1); sp = omap2_sdrc_get_params(sdrcrate); if (!sp) return -EINVAL; pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, validrate); pr_info("clock: SDRC timing params used: %08x %08x %08x\n", sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb); /* REVISIT: SRAM code doesn't support other M2 divisors yet */ WARN_ON(new_div != 1 && new_div != 2); /* REVISIT: Add SDRC_MR changing to this code also */ omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb, new_div); return 0; }
return -EINVAL; if (clk != &dpll3_m2_ck) return -EINVAL; validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); if (validrate != rate) return -EINVAL; sdrcrate = sdrc_ick.rate; if (rate > clk->rate) sdrcrate <<= ((rate / clk->rate) >> 1); else sdrcrate >>= ((clk->rate / rate) >> 1); ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1); if (ret) return -EINVAL; if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) { pr_debug("clock: will unlock SDRC DLL\n"); unlock_dll = 1; } /* * XXX This only needs to be done when the CPU frequency changes */ mpurate = arm_fck.rate / CYCLES_PER_MHZ; c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; c += 1; /* for safety */ c *= SDRC_MPURATE_LOOPS;
return -EINVAL; if (clk != &dpll3_m2_ck) return -EINVAL; validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); if (validrate != rate) return -EINVAL; sdrcrate = sdrc_ick.rate; if (rate > clk->rate) sdrcrate <<= ((rate / clk->rate) >> 1); else sdrcrate >>= ((clk->rate / rate) >> 1); sp = omap2_sdrc_get_params(sdrcrate); if (!sp) return -EINVAL; if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) { pr_debug("clock: will unlock SDRC DLL\n"); unlock_dll = 1; } /* * XXX This only needs to be done when the CPU frequency changes */ mpurate = arm_fck.rate / CYCLES_PER_MHZ; c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; c += 1; /* for safety */ c *= SDRC_MPURATE_LOOPS;