/* * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC. * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2) * * Used by the clock framework during CORE DPLL changes */ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force) { u32 dll_ctrl, m_type; u32 prev = curr_perf_level; unsigned long flags; if ((curr_perf_level == level) && !force) return prev; if (level == CORE_CLK_SRC_DPLL) dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl(); else if (level == CORE_CLK_SRC_DPLL_X2) dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl(); else return prev; m_type = omap2xxx_sdrc_get_type(); local_irq_save(flags); /* * XXX These calls should be abstracted out through a * prm2xxx.c function */ if (cpu_is_omap2420()) __raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP); else __raw_writel(0xffff, OMAP2430_PRCM_VOLTSETUP); omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type); curr_perf_level = level; local_irq_restore(flags); return prev; }
/* * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC. * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2) * * Used by the clock framework during CORE DPLL changes */ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force) { u32 dll_ctrl, m_type; u32 prev = curr_perf_level; unsigned long flags; if ((curr_perf_level == level) && !force) return prev; if (level == CORE_CLK_SRC_DPLL) dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl(); else if (level == CORE_CLK_SRC_DPLL_X2) dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl(); else return prev; m_type = omap2xxx_sdrc_get_type(); local_irq_save(flags); __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP); omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type); curr_perf_level = level; local_irq_restore(flags); return prev; }