static long hist_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) { struct ispstat *stat = v4l2_get_subdevdata(sd); switch (cmd) { case VIDIOC_OMAP3ISP_HIST_CFG: return omap3isp_stat_config(stat, arg); case VIDIOC_OMAP3ISP_STAT_REQ: return omap3isp_stat_request_statistics(stat, arg); case VIDIOC_OMAP3ISP_STAT_EN: { int *en = arg; return omap3isp_stat_enable(stat, !!*en); } } return -ENOIOCTLCMD; }
int omap3isp_stat_s_stream(struct v4l2_subdev *subdev, int enable) { struct ispstat *stat = v4l2_get_subdevdata(subdev); if (enable) { /* * Only set enable PCR bit if the module was previously * enabled through ioct. */ isp_stat_try_enable(stat); } else { unsigned long flags; /* Disable PCR bit and config enable field */ omap3isp_stat_enable(stat, 0); spin_lock_irqsave(&stat->isp->stat_lock, flags); stat->ops->enable(stat, 0); spin_unlock_irqrestore(&stat->isp->stat_lock, flags); /* * If module isn't busy, a new interrupt may come or not to * set the state to DISABLED. As Histogram needs to read its * internal memory to clear it, let interrupt handler * responsible of changing state to DISABLED. If the last * interrupt is coming, it's still safe as the handler will * ignore the second time when state is already set to DISABLED. * It's necessary to synchronize Histogram with streamoff, once * the module may be considered idle before last SDMA transfer * starts if we return here. */ if (!omap3isp_stat_pcr_busy(stat)) omap3isp_stat_isr(stat); dev_dbg(stat->isp->dev, "%s: module is being disabled\n", stat->subdev.name); } return 0; }
int omap3isp_stat_s_stream(struct v4l2_subdev *subdev, int enable) { struct ispstat *stat = v4l2_get_subdevdata(subdev); if (enable) { isp_stat_try_enable(stat); } else { unsigned long flags; omap3isp_stat_enable(stat, 0); spin_lock_irqsave(&stat->isp->stat_lock, flags); stat->ops->enable(stat, 0); spin_unlock_irqrestore(&stat->isp->stat_lock, flags); if (!omap3isp_stat_pcr_busy(stat)) omap3isp_stat_isr(stat); dev_dbg(stat->isp->dev, "%s: module is being disabled\n", stat->subdev.name); } return 0; }