static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, int power_on, int vdd) { u32 reg; unsigned long timeout; if (power_on) { reg = omap4_ctrl_pad_readl(control_pbias_offset); reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK; if ((1 << vdd) <= MMC_VDD_165_195) reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK; else reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK; reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | OMAP4_MMC1_PWRDNZ_MASK); omap4_ctrl_pad_writel(reg, control_pbias_offset); timeout = jiffies + msecs_to_jiffies(5); do { reg = omap4_ctrl_pad_readl(control_pbias_offset); if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK)) break; usleep_range(100, 200); } while (!time_after(jiffies, timeout)); if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) { pr_err("Pbias Voltage is not same as LDO\n"); /* Caution : On VMODE_ERROR Power Down MMC IO */ reg &= ~(OMAP4_MMC1_PWRDNZ_MASK); omap4_ctrl_pad_writel(reg, control_pbias_offset); } } }
static void tsp_set_power_gpio(bool on) { u32 r; if (on) { pr_info("tsp: power on.\n"); gpio_set_value(tsp_gpios[GPIO_TOUCH_EN].gpio, 1); r = omap4_ctrl_pad_readl( OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0); r &= ~OMAP4_I2C3_SDA_PULLUPRESX_MASK; r &= ~OMAP4_I2C3_SCL_PULLUPRESX_MASK; omap4_ctrl_pad_writel(r, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0); omap_mux_set_gpio(OMAP_PIN_INPUT | OMAP_MUX_MODE3, tsp_gpios[GPIO_TOUCH_nINT].gpio); } else { pr_info("tsp: power off.\n"); gpio_set_value(tsp_gpios[GPIO_TOUCH_EN].gpio, 0); /* Below register settings needed by prevent current leakage. */ r = omap4_ctrl_pad_readl( OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0); r |= OMAP4_I2C3_SDA_PULLUPRESX_MASK; r |= OMAP4_I2C3_SCL_PULLUPRESX_MASK; omap4_ctrl_pad_writel(r, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0); omap_mux_set_gpio(OMAP_PIN_INPUT | OMAP_MUX_MODE3, tsp_gpios[GPIO_TOUCH_nINT].gpio); } return; }
static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, int power_on, int vdd) { u32 reg; if (power_on) { reg = omap4_ctrl_pad_readl(control_pbias_offset); reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK; if ((1 << vdd) <= MMC_VDD_165_195) reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK; else reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK; reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | OMAP4_MMC1_PWRDNZ_MASK | OMAP4_USBC1_ICUSB_PWRDNZ_MASK); omap4_ctrl_pad_writel(reg, control_pbias_offset); /* 4 microsec delay for comparator to generate an error*/ udelay(4); reg = omap4_ctrl_pad_readl(control_pbias_offset); if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) { pr_err("Pbias Voltage is not same as LDO\n"); /* Caution : On VMODE_ERROR Power Down MMC IO */ reg &= ~(OMAP4_MMC1_PWRDNZ_MASK | OMAP4_USBC1_ICUSB_PWRDNZ_MASK); omap4_ctrl_pad_writel(reg, control_pbias_offset); } } else { reg = omap4_ctrl_pad_readl(control_pbias_offset); reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | OMAP4_MMC1_PWRDNZ_MASK | OMAP4_MMC1_PBIASLITE_VMODE_MASK | OMAP4_USBC1_ICUSB_PWRDNZ_MASK); omap4_ctrl_pad_writel(reg, control_pbias_offset); } }
static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, int power_on, int vdd) { u32 reg; unsigned long timeout; if (power_on) { int use_3_volt_mode = !((1 << vdd) <= MMC_VDD_165_195); int dont_try_again = 0; try_again: reg = omap4_ctrl_pad_readl(control_pbias_offset); reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK; if (!use_3_volt_mode) reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK; else reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK; reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | OMAP4_MMC1_PWRDNZ_MASK); omap4_ctrl_pad_writel(reg, control_pbias_offset); timeout = jiffies + msecs_to_jiffies(5); do { reg = omap4_ctrl_pad_readl(control_pbias_offset); /* If we detect an error, stop immediately to handle it. * Otherwise, keep going to make sure that no error * shows up within our timeout */ if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) break; usleep_range(100, 200); } while (!time_after(jiffies, timeout)); if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) { /* Caution : On VMODE_ERROR Power Down MMC IO */ reg &= ~(OMAP4_MMC1_PWRDNZ_MASK); omap4_ctrl_pad_writel(reg, control_pbias_offset); if (!dont_try_again) { use_3_volt_mode = !use_3_volt_mode; pr_warn("Pbias Voltage is not the same as LDO," "reconfiguring for %sv mode.\n", use_3_volt_mode ? "3" : "1.8"); usleep_range(100, 200); dont_try_again = 1; goto try_again; } else { pr_err("Pbias Voltage is still not the same as" " LDO. Forcing shutdown\n"); } } } }
static struct omap_hwmod_mux_info * setup_4430ehci_io_mux(const enum usbhs_omap_port_mode *port_mode) { struct omap_device_pad *pads; int pads_cnt; u32 val = 0; switch (port_mode[0]) { case OMAP_EHCI_PORT_MODE_PHY: pads = port1_phy_pads; pads_cnt = ARRAY_SIZE(port1_phy_pads); break; case OMAP_EHCI_PORT_MODE_TLL: pads = port1_tll_pads; pads_cnt = ARRAY_SIZE(port1_tll_pads); /* Errata i687: set I/O drive strength to 1 */ if (cpu_is_omap443x()) { val = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_2); val |= OMAP4_USBB1_DR0_DS_MASK; omap4_ctrl_pad_writel(val, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_2); } break; case OMAP_USBHS_PORT_MODE_UNUSED: default: break; } switch (port_mode[1]) { case OMAP_EHCI_PORT_MODE_PHY: pads = port2_phy_pads; pads_cnt = ARRAY_SIZE(port2_phy_pads); break; case OMAP_EHCI_PORT_MODE_TLL: pads = port2_tll_pads; pads_cnt = ARRAY_SIZE(port2_tll_pads); /* Errata i687: set I/O drive strength to 1 */ if (cpu_is_omap443x()) { val = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_2); val |= OMAP4_USBB2_DR0_DS_MASK; omap4_ctrl_pad_writel(val, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_2); } break; case OMAP_USBHS_PORT_MODE_UNUSED: default: break; } return omap_hwmod_mux_init(pads, pads_cnt); }
static void __init kona_i2c_init(void) { u32 r; omap_i2c_hwspinlock_init(1, 0, &kona_i2c_1_bus_pdata); omap_i2c_hwspinlock_init(2, 1, &kona_i2c_2_bus_pdata); omap_i2c_hwspinlock_init(3, 2, &kona_i2c_3_bus_pdata); omap_i2c_hwspinlock_init(4, 3, &kona_i2c_4_bus_pdata); omap_register_i2c_bus_board_data(1, &kona_i2c_1_bus_pdata); omap_register_i2c_bus_board_data(2, &kona_i2c_2_bus_pdata); omap_register_i2c_bus_board_data(3, &kona_i2c_3_bus_pdata); omap_register_i2c_bus_board_data(4, &kona_i2c_4_bus_pdata); /* * Phoenix Audio IC needs I2C1 to * start with 400 KHz or less */ omap_register_i2c_bus(1, 400, NULL, 0); omap_register_i2c_bus(2, 400, kona_i2c_board_info, ARRAY_SIZE(kona_i2c_board_info)); omap_register_i2c_bus(3, 400, NULL, 0); omap_register_i2c_bus(4, 400, NULL, 0); r = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0); r |= (1 << OMAP4_I2C3_SDA_PULLUPRESX_SHIFT); r |= (1 << OMAP4_I2C3_SCL_PULLUPRESX_SHIFT); omap4_ctrl_pad_writel(r, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0); }
static void omap4_tuna_init_hw_rev(void) { int ret; int i; u32 r; /* Disable weak driver pulldown on usbb2_hsic_strobe */ r = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC); r &= ~OMAP4_USBB2_HSIC_STROBE_WD_MASK; omap4_ctrl_pad_writel(r, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC); ret = gpio_request_array(tuna_hw_rev_gpios, ARRAY_SIZE(tuna_hw_rev_gpios)); BUG_ON(ret); for (i = 0; i < ARRAY_SIZE(tuna_hw_rev_gpios); i++) tuna_hw_rev |= gpio_get_value(tuna_hw_rev_gpios[i].gpio) << i; snprintf(omap4_tuna_bd_info_string, ARRAY_SIZE(omap4_tuna_bd_info_string), "Tuna HW revision: %02x (%s), cpu %s ES%d.%d ", tuna_hw_rev, omap4_tuna_hw_rev_name(), cpu_is_omap443x() ? "OMAP4430" : "OMAP4460", (GET_OMAP_REVISION() >> 4) & 0xf, GET_OMAP_REVISION() & 0xf); pr_info("%s\n", omap4_tuna_bd_info_string); mach_panic_string = omap4_tuna_bd_info_string; }
static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot, int power_on, int vdd) { u32 reg; //printk(">>> omap4_hsmmc1_before_set_reg, slot: %d, power_on: %d, vdd: %d\n", slot, power_on, vdd); /* * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the * card with Vcc regulator (from twl4030 or whatever). OMAP has both * 1.8V and 3.0V modes, controlled by the PBIAS register. * * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which * is most naturally TWL VSIM; those pins also use PBIAS. * * FIXME handle VMMC1A as needed ... */ reg = omap4_ctrl_pad_readl(control_pbias_offset); reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | OMAP4_MMC1_PWRDNZ_MASK | OMAP4_USBC1_ICUSB_PWRDNZ_MASK); omap4_ctrl_pad_writel(reg, control_pbias_offset); //printk("<<< omap4_hsmmc1_before_set_reg\n"); }
static void sdp4430_lcd_init(void) { u32 reg; int status; /* Enable 3 lanes in DSI1 module, disable pull down */ reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); reg &= ~OMAP4_DSI1_LANEENABLE_MASK; reg |= 0x7 << OMAP4_DSI1_LANEENABLE_SHIFT; reg &= ~OMAP4_DSI1_PIPD_MASK; reg |= 0x7 << OMAP4_DSI1_PIPD_SHIFT; omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); /* Panel Taal reset and backlight GPIO init */ status = gpio_request_one(dsi1_panel.reset_gpio, GPIOF_DIR_OUT, "lcd_reset_gpio"); if (status) pr_err("%s: Could not get lcd_reset_gpio\n", __func__); if (dsi1_panel.use_ext_te) { status = omap_mux_init_signal("gpmc_ncs4.gpio_101", OMAP_PIN_INPUT_PULLUP); if (status) pr_err("%s: Could not get ext_te gpio\n", __func__); } status = gpio_request_one(LCD_BL_GPIO, GPIOF_DIR_OUT, "lcd_bl_gpio"); if (status) pr_err("%s: Could not get lcd_bl_gpio\n", __func__); gpio_set_value(LCD_BL_GPIO, 0); }
void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) { u32 reg; if (!cpu_is_omap44xx()) { if (cpu_is_omap2430()) { control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; } else { control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; } } else { control_pbias_offset = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; reg = omap4_ctrl_pad_readl(control_mmc1); reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK| OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); omap4_ctrl_pad_writel(reg, control_mmc1); } for (; controllers->mmc; controllers++) omap_init_hsmmc(controllers, controllers->mmc); }
static void __init t1_i2c_init(void) { u32 reg_val; /* Disable internal pull ups for i2c 1 and 2 and enable for i2c 3 and 4 */ reg_val = omap4_ctrl_pad_readl( OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0); PULLUP_DISABLE(reg_val, SCL, I2C1); PULLUP_DISABLE(reg_val, SDA, I2C1); PULLUP_DISABLE(reg_val, SCL, I2C2); PULLUP_DISABLE(reg_val, SDA, I2C2); PULLUP_ENABLE(reg_val, SCL, I2C3); PULLUP_ENABLE(reg_val, SDA, I2C3); PULLUP_ENABLE(reg_val, SCL, I2C4); PULLUP_ENABLE(reg_val, SDA, I2C4); SET_LOAD(reg_val, SCL, I2C3, LOAD_860_OHM); SET_LOAD(reg_val, SDA, I2C3, LOAD_860_OHM); SET_LOAD(reg_val, SCL, I2C4, LOAD_860_OHM); SET_LOAD(reg_val, SDA, I2C4, LOAD_860_OHM); omap4_ctrl_pad_writel(reg_val, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0); /* 860 k, SR Enable Internal Pull up */ reg_val = omap4_ctrl_wk_pad_readl( OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2); PULLUP_ENABLE(reg_val, SCL, SR); PULLUP_ENABLE(reg_val, SDA, SR); SET_LOAD(reg_val, SCL, SR, LOAD_860_OHM); SET_LOAD(reg_val, SDA, SR, LOAD_860_OHM); omap4_ctrl_wk_pad_writel(reg_val, OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2); omap_i2c_hwspinlock_init(1, 0, &t1_i2c1_bus_pdata); omap_i2c_hwspinlock_init(2, 1, &t1_i2c2_bus_pdata); omap_i2c_hwspinlock_init(3, 2, &t1_i2c3_bus_pdata); omap_i2c_hwspinlock_init(4, 3, &t1_i2c4_bus_pdata); omap_register_i2c_bus_board_data(1, &t1_i2c1_bus_pdata); omap_register_i2c_bus_board_data(2, &t1_i2c2_bus_pdata); omap_register_i2c_bus_board_data(3, &t1_i2c3_bus_pdata); omap_register_i2c_bus_board_data(4, &t1_i2c4_bus_pdata); /* * Phoenix Audio IC needs I2C1 to * start with 400 KHz or less */ #ifdef CONFIG_REGULATOR_TPS6130X omap_register_i2c_bus(1, 400, t1_i2c1_board_info, ARRAY_SIZE(t1_i2c_board_info)); #else omap_register_i2c_bus(1, 400, NULL, 0); #endif omap_register_i2c_bus(2, 400, t1_i2c_board_info, ARRAY_SIZE(t1_i2c_board_info)); omap_register_i2c_bus(3, 400, NULL, 0); omap_register_i2c_bus(4, 400, NULL, 0); }
/** * omap2_i2c_pullup - setup pull-up resistors for I2C bus * @bus_id: bus id counting from number 1 * @sda_pullup: Pull-up resistor for SDA and SCL pins * */ void omap2_i2c_pullup(int bus_id, enum omap_i2c_pullup_values pullup) { u32 val = 0; if (bus_id < 1 || bus_id > omap_i2c_nr_ports() || pullup > I2C_PULLUP_STD_NA_FAST_300_OM) { pr_err("%s:Wrong pullup (%d) or use wrong I2C port (%d)\n", __func__, pullup, bus_id); return; } val = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0); switch (bus_id) { case 1: /* Setup PULL-UP resistor for I2C-1 */ val &= ~(OMAP4_I2C1_SDA_LOAD_BITS_MASK | OMAP4_I2C1_SCL_LOAD_BITS_MASK | OMAP4_I2C1_SDA_PULLUPRESX_MASK | OMAP4_I2C1_SCL_PULLUPRESX_MASK); val |= ((pullup << OMAP4_I2C1_SDA_LOAD_BITS_SHIFT) | (pullup << OMAP4_I2C1_SCL_LOAD_BITS_SHIFT)); break; case 2: /* Setup PULL-UP resistor for I2C-2 */ val &= ~(OMAP4_I2C2_SDA_LOAD_BITS_MASK | OMAP4_I2C2_SCL_LOAD_BITS_MASK | OMAP4_I2C2_SDA_PULLUPRESX_MASK | OMAP4_I2C2_SCL_PULLUPRESX_MASK); val |= ((pullup << OMAP4_I2C2_SDA_LOAD_BITS_SHIFT) | (pullup << OMAP4_I2C2_SCL_LOAD_BITS_SHIFT)); break; case 3: /* Setup PULL-UP resistor for I2C-3 */ val &= ~(OMAP4_I2C3_SDA_LOAD_BITS_MASK | OMAP4_I2C3_SCL_LOAD_BITS_MASK | OMAP4_I2C3_SDA_PULLUPRESX_MASK | OMAP4_I2C3_SCL_PULLUPRESX_MASK); val |= ((pullup << OMAP4_I2C3_SDA_LOAD_BITS_SHIFT) | (pullup << OMAP4_I2C3_SCL_LOAD_BITS_SHIFT)); break; case 4: /* Setup PULL-UP resistor for I2C-4 */ val &= ~(OMAP4_I2C4_SDA_LOAD_BITS_MASK | OMAP4_I2C4_SCL_LOAD_BITS_MASK | OMAP4_I2C4_SDA_PULLUPRESX_MASK | OMAP4_I2C4_SCL_PULLUPRESX_MASK); val |= ((pullup << OMAP4_I2C4_SDA_LOAD_BITS_SHIFT) | (pullup << OMAP4_I2C4_SCL_LOAD_BITS_SHIFT)); break; default: return; } omap4_ctrl_pad_writel(val, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0); }
static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot, int power_on, int vdd) { u32 reg; reg = omap4_ctrl_pad_readl(control_pbias_offset); reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | OMAP4_MMC1_PWRDNZ_MASK | OMAP4_MMC1_PBIASLITE_VMODE_MASK); omap4_ctrl_pad_writel(reg, control_pbias_offset); }
/* OMAP5 ES2.0 PBIAS setting procedure */ static void omap5_es2_before_set_reg(struct device *dev, int slot, int power_on, int vdd) { u32 reg; reg = omap4_ctrl_pad_readl(control_pbias_offset); reg &= ~(OMAP5_ES20_CONTROL_PBIAS_SDCARD_IO_PWRRDNZ); omap4_ctrl_pad_writel(reg, control_pbias_offset); udelay(10); reg &= ~(OMAP5_ES20_CONTROL_PBIAS_SDCARD_BIAS_PWRDNZ); omap4_ctrl_pad_writel(reg, control_pbias_offset); }
static void iff_lcd_dsi_phy_init(void) { u32 reg; /* Enable 5 lanes (0 ~ 4) in DSI1 */ /* Disable pull down */ reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); reg &= ~OMAP4_DSI1_LANEENABLE_MASK; reg |= 0x1F << OMAP4_DSI1_LANEENABLE_SHIFT; reg &= ~OMAP4_DSI1_PIPD_MASK; reg |= 0x1F << OMAP4_DSI1_PIPD_SHIFT; omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); }
static int __init panda_camera_init(void) { if (!machine_is_omap4_panda()) return 0; panda_cam_aux_clk = clk_get(NULL, "auxclk1_ck"); if (IS_ERR(panda_cam_aux_clk)) { printk(KERN_ERR "Unable to get auxclk1_ck\n"); return -ENODEV; } if (clk_set_rate(panda_cam_aux_clk, clk_round_rate(panda_cam_aux_clk, 24000000))) return -EINVAL; /* * CSI2 1(A): * LANEENABLE[4:0] = 00111(0x7) - Lanes 0, 1 & 2 enabled * CTRLCLKEN = 1 - Active high enable for CTRLCLK * CAMMODE = 0 - DPHY mode */ omap4_ctrl_pad_writel((omap4_ctrl_pad_readl( OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX) & ~(OMAP4_CAMERARX_CSI21_LANEENABLE_MASK | OMAP4_CAMERARX_CSI21_CAMMODE_MASK)) | (0x7 << OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT) | OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX); /* Select GPIO 45 */ omap_mux_init_gpio(PANDA_GPIO_CAM_PWRDN, OMAP_PIN_OUTPUT); /* Select GPIO 83 */ omap_mux_init_gpio(PANDA_GPIO_CAM_RESET, OMAP_PIN_OUTPUT); /* Init FREF_CLK1_OUT */ omap_mux_init_signal("fref_clk1_out", OMAP_PIN_OUTPUT); if (gpio_request_one(PANDA_GPIO_CAM_PWRDN, GPIOF_OUT_INIT_HIGH, "CAM_PWRDN")) printk(KERN_WARNING "Cannot request GPIO %d\n", PANDA_GPIO_CAM_PWRDN); if (gpio_request_one(PANDA_GPIO_CAM_RESET, GPIOF_OUT_INIT_HIGH, "CAM_RESET")) printk(KERN_WARNING "Cannot request GPIO %d\n", PANDA_GPIO_CAM_RESET); omap4_init_camera(&panda_iss_platform_data, &omap4iss_data); return 0; }
static void omap5_es2_after_set_reg(struct device *dev, int slot, int power_on, int vdd) { u32 reg; if (power_on) { reg = omap4_ctrl_pad_readl(control_pbias_offset); reg |= OMAP5_ES20_CONTROL_PBIAS_SDCARD_BIAS_PWRDNZ; omap4_ctrl_pad_writel(reg, control_pbias_offset); udelay(150); reg |= OMAP5_ES20_CONTROL_PBIAS_SDCARD_IO_PWRRDNZ; omap4_ctrl_pad_writel(reg, control_pbias_offset); udelay(150); } }
static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot, int power_on, int vdd) { u32 reg; /* * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the * card with Vcc regulator (from twl4030 or whatever). OMAP has both * 1.8V and 3.0V modes, controlled by the PBIAS register. */ reg = omap4_ctrl_pad_readl(control_pbias_offset); reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | OMAP4_MMC1_PWRDNZ_MASK | OMAP4_MMC1_PBIASLITE_VMODE_MASK); omap4_ctrl_pad_writel(reg, control_pbias_offset); }
static void tablet_lcd_init(void) { u32 reg; int status; /* Enable 3 lanes in DSI1 module, disable pull down */ reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); reg &= ~OMAP4_DSI1_LANEENABLE_MASK; reg |= 0x1f << OMAP4_DSI1_LANEENABLE_SHIFT; reg &= ~OMAP4_DSI1_PIPD_MASK; reg |= 0x1f << OMAP4_DSI1_PIPD_SHIFT; omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); status = gpio_request_one(tablet_dsi_panel.reset_gpio, GPIOF_OUT_INIT_LOW, "lcd_reset_gpio"); if (status) pr_err("%s: Could not get lcd_reset_gpio\n", __func__); }
static void __init tablet_camera_mux_init(void) { u32 r = 0; /* Enable CSI22 pads for 4460 and 4470*/ if ((cpu_is_omap446x() || cpu_is_omap447x()) && (omap_get_board_version() >= OMAP4_TABLET_2_0)) { r = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX); r |= (0x7 << OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT); omap4_ctrl_pad_writel(r, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX); omap_mux_init_signal("csi22_dx2.csi22_dx2", OMAP_PIN_INPUT | OMAP_MUX_MODE0); omap_mux_init_signal("csi22_dy2.csi22_dy2", OMAP_PIN_INPUT | OMAP_MUX_MODE0); } }
static int __init tuna_i2c_init(void) { u32 r; omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_WAKEUP_EN); omap_mux_init_signal("i2c1_scl.i2c1_scl", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("i2c1_sda.i2c1_sda", OMAP_PIN_INPUT_PULLUP); /* * This will allow unused regulator to be shutdown. This flag * should be set in the board file. Before regulators are registered. */ regulator_has_full_constraints(); /* * Phoenix Audio IC needs I2C1 to * start with 400 KHz or less */ omap_register_i2c_bus(1, 400, tuna_i2c1_boardinfo, ARRAY_SIZE(tuna_i2c1_boardinfo)); omap_register_i2c_bus(2, 400, tuna_i2c2_boardinfo, ARRAY_SIZE(tuna_i2c2_boardinfo)); omap_register_i2c_bus(3, 400, NULL, 0); /* Disable internal pullup on i2c.4 line: * as external 2.2K is already present */ r = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0); r |= (1 << OMAP4_I2C4_SDA_PULLUPRESX_SHIFT); omap4_ctrl_pad_writel(r, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0); omap_register_i2c_bus(4, 400, NULL, 0); /* * Drive MSECURE high for TWL6030 write access. */ omap_mux_init_signal("fref_clk0_out.gpio_wk6", OMAP_PIN_OUTPUT); gpio_request(6, "msecure"); gpio_direction_output(6, 1); return 0; }
static void __init gokey_tsp_gpio_init(void) { int i; u32 r; for (i = 0; i < ARRAY_SIZE(tsp_gpios); i++) tsp_gpios[i].gpio = omap_muxtbl_get_gpio_by_name(tsp_gpios[i].label); gpio_request_array(tsp_gpios, ARRAY_SIZE(tsp_gpios)); gokey_i2c3_boardinfo[0].irq = gpio_to_irq(tsp_gpios[GPIO_TOUCH_nINT].gpio); /* i2c3 line using external pullup */ r = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0); r |= (1 << OMAP4_I2C3_SDA_PULLUPRESX_SHIFT); r |= (1 << OMAP4_I2C3_SCL_PULLUPRESX_SHIFT); omap4_ctrl_pad_writel(r, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0); omap_mux_set_gpio(OMAP_PIN_INPUT | OMAP_PIN_OFF_WAKEUPENABLE | OMAP_MUX_MODE3, tsp_gpios[GPIO_TOUCH_nINT].gpio); }
static void __init t1_i2c_init(void) { u32 reg_val; /* Disable internal pull ups for i2c 1 and 2 and enable for i2c 3 and 4 */ reg_val = omap4_ctrl_pad_readl( OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0); PULLUP_DISABLE(reg_val, SCL, I2C1); PULLUP_DISABLE(reg_val, SDA, I2C1); PULLUP_DISABLE(reg_val, SCL, I2C2); PULLUP_DISABLE(reg_val, SDA, I2C2); PULLUP_ENABLE(reg_val, SCL, I2C3); PULLUP_ENABLE(reg_val, SDA, I2C3); PULLUP_ENABLE(reg_val, SCL, I2C4); PULLUP_ENABLE(reg_val, SDA, I2C4); SET_LOAD(reg_val, SCL, I2C3, LOAD_860_OHM); SET_LOAD(reg_val, SDA, I2C3, LOAD_860_OHM); SET_LOAD(reg_val, SCL, I2C4, LOAD_860_OHM); SET_LOAD(reg_val, SDA, I2C4, LOAD_860_OHM); omap4_ctrl_pad_writel(reg_val, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0); /* 860 k, SR Enable Internal Pull up */ reg_val = omap4_ctrl_wk_pad_readl( OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2); PULLUP_ENABLE(reg_val, SCL, SR); PULLUP_ENABLE(reg_val, SDA, SR); SET_LOAD(reg_val, SCL, SR, LOAD_860_OHM); SET_LOAD(reg_val, SDA, SR, LOAD_860_OHM); omap4_ctrl_wk_pad_writel(reg_val, OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2); /* * Phoenix Audio IC needs I2C1 to * start with 400 KHz or less */ omap_register_i2c_bus(1, 400, NULL, 0); omap_register_i2c_bus(2, 400, t1_i2c_board_info, ARRAY_SIZE(t1_i2c_board_info)); omap_register_i2c_bus(3, 400, NULL, 0); omap_register_i2c_bus(4, 400, NULL, 0); }
void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) { u32 reg; if (!cpu_is_omap44xx()) { if (cpu_is_omap2430()) { control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; } else { control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; } } else { control_pbias_offset = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; reg = omap4_ctrl_pad_readl(control_mmc1); reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK| OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); omap4_ctrl_pad_writel(reg, control_mmc1); } // from GB MMC0 and MMC1 was swapping. [START] #ifdef TI_FS_MMC for (; controllers->mmc; controllers++) omap_init_hsmmc(controllers, controllers->mmc); #else omap_init_hsmmc(&controllers[1], controllers[1].mmc); omap_init_hsmmc(&controllers[0], controllers[0].mmc); omap_init_hsmmc(&controllers[2], controllers[2].mmc); #endif // TI_FS_MMC // from GB MMC0 and MMC1 was swapping. [END] sd_ldo_init(); }
void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) { u32 reg; if (!cpu_is_omap44xx()) { if (cpu_is_omap2430()) { control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; } else { control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; } if (machine_is_omap3_pandora()) { /* needed for gpio_126 - gpio_129 to work correctly */ reg = omap_ctrl_readl(control_pbias_offset); reg &= ~OMAP343X_PBIASLITEVMODE1; omap_ctrl_writel(reg, control_pbias_offset); } } else { control_pbias_offset = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; reg = omap4_ctrl_pad_readl(control_mmc1); reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK | OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); omap4_ctrl_pad_writel(reg, control_mmc1); } for (; controllers->mmc; controllers++) omap_init_hsmmc(controllers, controllers->mmc); }
static void cosmo_dsi_phy_init(void) { u32 reg; /* Enable 3 lanes (0 ~ 2) in DSI2 */ /* Disable pull down */ reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); reg &= ~OMAP4_DSI2_LANEENABLE_MASK; reg |= 0x1F << OMAP4_DSI2_LANEENABLE_SHIFT; reg &= ~OMAP4_DSI2_PIPD_MASK; reg |= 0x1F << OMAP4_DSI2_PIPD_SHIFT; omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); #ifdef CONFIG_MACH_LGE_COSMO //mo2sanghyun.lee gpio_request(HDMI_GPIO_60 , "hdmi_gpio_60"); gpio_request(HDMI_GPIO_41 , "hdmi_gpio_41"); gpio_direction_output(HDMI_GPIO_60, 1); gpio_direction_output(HDMI_GPIO_41, 0); #endif #if defined(CONFIG_DSI_CMD_MODE) omap_mux_init_signal("gpmc_ncs6.dsi2_te0", OMAP_PIN_INPUT); #endif }
void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) { struct omap2_hsmmc_info *c; int nr_hsmmc = ARRAY_SIZE(hsmmc_data); int i; u32 reg; if (!cpu_is_omap44xx()) { if (cpu_is_omap2430()) { control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; } else { control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; } } else { control_pbias_offset = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; reg = omap4_ctrl_pad_readl(control_mmc1); reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK| OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); omap4_ctrl_pad_writel(reg, control_mmc1); } for (c = controllers; c->mmc; c++) { struct hsmmc_controller *hc = hsmmc + c->mmc - 1; struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; if (!c->mmc || c->mmc > nr_hsmmc) { pr_debug("MMC%d: no such controller\n", c->mmc); continue; } if (mmc) { pr_debug("MMC%d: already configured\n", c->mmc); continue; } mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL); if (!mmc) { pr_err("Cannot allocate memory for mmc device!\n"); goto done; } if (cpu_is_ti816x()) mmc->version = MMC_CTRL_VERSION_2; if (c->name) strncpy(hc->name, c->name, HSMMC_NAME_LEN); else snprintf(hc->name, ARRAY_SIZE(hc->name), "mmc%islot%i", c->mmc, 1); mmc->slots[0].name = hc->name; mmc->nr_slots = 1; mmc->slots[0].caps = c->caps; mmc->slots[0].internal_clock = !c->ext_clock; mmc->dma_mask = 0xffffffff; if (cpu_is_omap44xx()) mmc->reg_offset = OMAP4_MMC_REG_OFFSET; else mmc->reg_offset = 0; mmc->get_context_loss_count = hsmmc_get_context_loss; mmc->slots[0].switch_pin = c->gpio_cd; mmc->slots[0].gpio_wp = c->gpio_wp; mmc->slots[0].remux = c->remux; mmc->slots[0].init_card = c->init_card; if (c->cover_only) mmc->slots[0].cover = 1; if (c->nonremovable) mmc->slots[0].nonremovable = 1; if (c->power_saving) mmc->slots[0].power_saving = 1; if (c->no_off) mmc->slots[0].no_off = 1; if (c->vcc_aux_disable_is_sleep) mmc->slots[0].vcc_aux_disable_is_sleep = 1; /* NOTE: MMC slots should have a Vcc regulator set up. * This may be from a TWL4030-family chip, another * controllable regulator, or a fixed supply. * * temporary HACK: ocr_mask instead of fixed supply */ if (cpu_is_omap3505() || cpu_is_omap3517()) mmc->slots[0].ocr_mask = MMC_VDD_165_195 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32; else mmc->slots[0].ocr_mask = c->ocr_mask; if (cpu_is_omap3517() || cpu_is_omap3505() || cpu_is_ti81xx()) mmc->slots[0].set_power = nop_mmc_set_power; else mmc->slots[0].features |= HSMMC_HAS_PBIAS; if ((cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) || cpu_is_ti814x()) mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET; switch (c->mmc) { case 1: if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { /* on-chip level shifting via PBIAS0/PBIAS1 */ if (cpu_is_omap44xx()) { mmc->slots[0].before_set_reg = omap4_hsmmc1_before_set_reg; mmc->slots[0].after_set_reg = omap4_hsmmc1_after_set_reg; } else { mmc->slots[0].before_set_reg = omap_hsmmc1_before_set_reg; mmc->slots[0].after_set_reg = omap_hsmmc1_after_set_reg; } } /* Omap3630 HSMMC1 supports only 4-bit */ if (cpu_is_omap3630() && (c->caps & MMC_CAP_8_BIT_DATA)) { c->caps &= ~MMC_CAP_8_BIT_DATA; c->caps |= MMC_CAP_4_BIT_DATA; mmc->slots[0].caps = c->caps; } break; case 2: if (c->ext_clock) c->transceiver = 1; if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) { c->caps &= ~MMC_CAP_8_BIT_DATA; c->caps |= MMC_CAP_4_BIT_DATA; } /* FALLTHROUGH */ case 3: if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { /* off-chip level shifting, or none */ mmc->slots[0].before_set_reg = hsmmc23_before_set_reg; mmc->slots[0].after_set_reg = NULL; } break; default: pr_err("MMC%d configuration not supported!\n", c->mmc); kfree(mmc); continue; } hsmmc_data[c->mmc - 1] = mmc; } if (!cpu_is_ti81xx()) omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC); else omap2_init_mmc(hsmmc_data, TI81XX_NR_MMC); /* pass the device nodes back to board setup code */ for (c = controllers; c->mmc; c++) { struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; if (!c->mmc || c->mmc > nr_hsmmc) continue; c->dev = mmc->dev; } done: for (i = 0; i < nr_hsmmc; i++) kfree(hsmmc_data[i]); }
static struct omap_hwmod_mux_info * __init setup_4430_usbhs_io_mux(struct platform_device *pdev, const enum usbhs_omap_port_mode *port_mode) { const struct omap_device_pad *pads[OMAP3_HS_USB_PORTS]; int pads_cnt[OMAP3_HS_USB_PORTS]; switch (port_mode[0]) { case OMAP_EHCI_PORT_MODE_PHY: pads[0] = port1_phy_pads; pads_cnt[0] = ARRAY_SIZE(port1_phy_pads); break; case OMAP_EHCI_PORT_MODE_TLL: pads[0] = port1_tll_pads; pads_cnt[0] = ARRAY_SIZE(port1_tll_pads); /* Errata i687: set I/O drive strength to 1 */ if (cpu_is_omap443x()) { u32 val; val = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_2); val |= OMAP4_USBB1_DR0_DS_MASK; omap4_ctrl_pad_writel(val, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_2); } break; case OMAP_EHCI_PORT_MODE_HSIC: pads[0] = port1_hsic_pads; pads_cnt[0] = ARRAY_SIZE(port1_hsic_pads); break; case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: pads[0] = port1_6pin_pads; pads_cnt[0] = ARRAY_SIZE(port1_6pin_pads); break; case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: pads[0] = port1_4pin_pads; pads_cnt[0] = ARRAY_SIZE(port1_4pin_pads); break; case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: pads[0] = port1_3pin_pads; pads_cnt[0] = ARRAY_SIZE(port1_3pin_pads); break; case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: pads[0] = port1_2pin_pads; pads_cnt[0] = ARRAY_SIZE(port1_2pin_pads); break; case OMAP_USBHS_PORT_MODE_UNUSED: default: pads_cnt[0] = 0; break; } switch (port_mode[1]) { case OMAP_EHCI_PORT_MODE_PHY: pads[1] = port2_phy_pads; pads_cnt[1] = ARRAY_SIZE(port2_phy_pads); break; case OMAP_EHCI_PORT_MODE_TLL: pads[1] = port2_tll_pads; pads_cnt[1] = ARRAY_SIZE(port2_tll_pads); /* Errata i687: set I/O drive strength to 1 */ if (cpu_is_omap443x()) { u32 val; val = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_2); val |= OMAP4_USBB2_DR0_DS_MASK; omap4_ctrl_pad_writel(val, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_2); } break; case OMAP_EHCI_PORT_MODE_HSIC: pads[1] = port2_hsic_pads; pads_cnt[1] = ARRAY_SIZE(port2_hsic_pads); break; case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: pads[1] = port2_6pin_pads; pads_cnt[1] = ARRAY_SIZE(port2_6pin_pads); break; case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: pads[1] = port2_4pin_pads; pads_cnt[1] = ARRAY_SIZE(port2_4pin_pads); break; case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: pads[1] = port2_3pin_pads; pads_cnt[1] = ARRAY_SIZE(port2_3pin_pads); break; case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: pads[1] = port2_2pin_pads; pads_cnt[1] = ARRAY_SIZE(port2_3pin_pads); break; case OMAP_USBHS_PORT_MODE_UNUSED: default: pads_cnt[1] = 0; break; } switch (port_mode[2]) { case OMAP_EHCI_PORT_MODE_HSIC: pads[2] = port3_hsic_pads; pads_cnt[2] = ARRAY_SIZE(port3_hsic_pads); break; case OMAP_USBHS_PORT_MODE_UNUSED: default: pads_cnt[2] = 0; break; } return omap_hwmod_mux_array_init(pdev, pads, pads_cnt, port_mode); }
void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) { struct omap2_hsmmc_info *c; int nr_hsmmc = ARRAY_SIZE(hsmmc_data); int i; u32 reg; int controller_cnt = 0; printk(">>> omap2_hsmmc_init\n"); if (!cpu_is_omap44xx()) { if (cpu_is_omap2430()) { control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; } else { control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; } } else { control_pbias_offset = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; reg = omap4_ctrl_pad_readl(control_mmc1); reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK| OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); omap4_ctrl_pad_writel(reg, control_mmc1); } for (c = controllers; c->mmc; c++) { struct hsmmc_controller *hc = hsmmc + controller_cnt; struct omap_mmc_platform_data *mmc = hsmmc_data[controller_cnt]; if (!c->mmc || c->mmc > nr_hsmmc) { printk("MMC%d: no such controller\n", c->mmc); continue; } if (mmc) { printk("MMC%d: already configured\n", c->mmc); continue; } mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL); if (!mmc) { pr_err("Cannot allocate memory for mmc device!\n"); goto done; } if (c->name) strncpy(hc->name, c->name, HSMMC_NAME_LEN); else snprintf(hc->name, ARRAY_SIZE(hc->name), "mmc%islot%i", c->mmc, 1); #ifdef CONFIG_TIWLAN_SDIO if (c->mmc == CONFIG_TIWLAN_MMC_CONTROLLER) { mmc->slots[0].embedded_sdio = &omap_wifi_emb_data; mmc->slots[0].register_status_notify = &omap_wifi_status_register; mmc->slots[0].card_detect = &omap_wifi_status; } #endif mmc->slots[0].name = hc->name; mmc->nr_slots = 1; mmc->slots[0].caps = c->caps; mmc->slots[0].internal_clock = !c->ext_clock; mmc->dma_mask = 0xffffffff; /* Register offset Mapping */ if (cpu_is_omap44xx()) mmc->regs_map = (u16 *) omap4_mmc_reg_map; else mmc->regs_map = (u16 *) omap3_mmc_reg_map; if (!cpu_is_omap44xx()) mmc->get_context_loss_count = hsmmc_get_context_loss; //&*&*&*SJ1_20110607, Add SIM card detection. #if defined (CONFIG_SIM_CARD_DETECTION) && defined (CONFIG_CHANGE_INAND_MMC_SCAN_INDEX) mmc->slots[0].sim_switch_pin = c->gpio_sim_cd; #endif //&*&*&*SJ2_20110607, Add SIM card detection. mmc->slots[0].switch_pin = c->gpio_cd; mmc->slots[0].cd_active_high = c->cd_active_high; mmc->slots[0].gpio_wp = c->gpio_wp; mmc->slots[0].remux = c->remux; if (c->cover_only) mmc->slots[0].cover = 1; if (c->nonremovable) mmc->slots[0].nonremovable = 1; if (c->power_saving) mmc->slots[0].power_saving = 1; if (c->no_off) mmc->slots[0].no_off = 1; if (c->vcc_aux_disable_is_sleep) mmc->slots[0].vcc_aux_disable_is_sleep = 1; /* NOTE: MMC slots should have a Vcc regulator set up. * This may be from a TWL4030-family chip, another * controllable regulator, or a fixed supply. * * temporary HACK: ocr_mask instead of fixed supply */ mmc->slots[0].ocr_mask = c->ocr_mask; if (cpu_is_omap3517() || cpu_is_omap3505()) mmc->slots[0].set_power = nop_mmc_set_power; else mmc->slots[0].features |= HSMMC_HAS_PBIAS; if (cpu_is_omap44xx()) { if (omap_rev() > OMAP4430_REV_ES1_0) mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET; mmc->slots[0].features |= HSMMC_DVFS_24MHZ_CONST; if (c->mmc >= 3 && c->mmc <= 5) { mmc->slots[0].features |= HSMMC_HAS_48MHZ_MASTER_CLK; mmc->get_context_loss_count = hsmmc_get_context_loss; } } switch (c->mmc) { case 1: if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { /* on-chip level shifting via PBIAS0/PBIAS1 */ if (cpu_is_omap44xx()) { mmc->slots[0].before_set_reg = omap4_hsmmc1_before_set_reg; mmc->slots[0].after_set_reg = omap4_hsmmc1_after_set_reg; } else { mmc->slots[0].before_set_reg = omap_hsmmc1_before_set_reg; mmc->slots[0].after_set_reg = omap_hsmmc1_after_set_reg; } } /* Omap3630 HSMMC1 supports only 4-bit */ if (cpu_is_omap3630() && (c->caps & MMC_CAP_8_BIT_DATA)) { c->caps &= ~MMC_CAP_8_BIT_DATA; c->caps |= MMC_CAP_4_BIT_DATA; mmc->slots[0].caps = c->caps; } break; case 2: if (c->ext_clock) c->transceiver = 1; if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) { c->caps &= ~MMC_CAP_8_BIT_DATA; c->caps |= MMC_CAP_4_BIT_DATA; } /* FALLTHROUGH */ case 3: if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { /* off-chip level shifting, or none */ mmc->slots[0].before_set_reg = hsmmc23_before_set_reg; mmc->slots[0].after_set_reg = NULL; } #ifdef CONFIG_TIWLAN_SDIO mmc->slots[0].ocr_mask = MMC_VDD_165_195; #endif break; case 4: case 5: /* TODO Update required */ mmc->slots[0].before_set_reg = NULL; mmc->slots[0].after_set_reg = NULL; #ifdef CONFIG_TIWLAN_SDIO mmc->slots[0].ocr_mask = MMC_VDD_165_195; #endif break; default: pr_err("MMC%d configuration not supported!\n", c->mmc); kfree(mmc); continue; } hsmmc_data[controller_cnt] = mmc; omap2_init_mmc(hsmmc_data[controller_cnt], c->mmc); controller_cnt++; } /* pass the device nodes back to board setup code */ controller_cnt = 0; for (c = controllers; c->mmc; c++) { struct omap_mmc_platform_data *mmc = hsmmc_data[controller_cnt]; if (!c->mmc || c->mmc > nr_hsmmc) continue; c->dev = mmc->dev; controller_cnt++; } done: for (i = 0; i < controller_cnt; i++) kfree(hsmmc_data[i]); printk("<<< omap2_hsmmc_init\n"); }
int omap_uart_cts_wakeup(int uart_no, int state) { struct uart_omap_port *up = ui[uart_no]; struct omap_uart_port_info *omap_up_info = up->pdev->dev.platform_data; u16 offset = 0; /* 32-bit align */ u32 v; /* No CTS based Wake-ups are enabled. If enabled this would * hold the CTS Pad Conf Register offset. */ if (!omap_up_info->cts_padconf) { dev_dbg(up->port.dev, "No CTS wake-up for UART %d\n", uart_no); return -EPERM; } if (state) { /* * Enable the CTS for io pad wakeup */ dev_dbg(up->port.dev, "Enable CTS wakeup for UART %d", uart_no); offset = omap_up_info->cts_padconf & ~0x3; /* 32-bit align */ if (cpu_is_omap44xx()) v = omap4_ctrl_pad_readl(offset); else v = omap_ctrl_readl(offset); if (omap_up_info->cts_padconf & 0x2) { omap_up_info->cts_padvalue = 0xFFFF0000 & v; v |= (((OMAP_WAKEUP_EN | OMAP_OFF_PULL_EN | OMAP_OFF_PULL_UP | OMAP_OFFOUT_EN | OMAP_OFF_EN | OMAP_PULL_UP)) << 16); } else { omap_up_info->cts_padvalue = 0x0000FFFF & v; v |= ((OMAP_WAKEUP_EN | OMAP_OFF_PULL_EN | OMAP_OFF_PULL_UP | OMAP_OFFOUT_EN | OMAP_OFF_EN | OMAP_PULL_UP)); } if (cpu_is_omap44xx()) omap4_ctrl_pad_writel(v, offset); else omap_ctrl_writel(v, offset); /* * Enable the CTS for module level wakeup */ serial_out(up, UART_OMAP_WER, serial_in(up, UART_OMAP_WER) | 0x1); } else { dev_dbg(up->port.dev, "Disable CTS wakeup for UART%d\n", uart_no); /* * Disable the CTS capability for io pad wakeup */ offset = omap_up_info->cts_padconf & ~0x3; /* 32-bit align */ if (cpu_is_omap44xx()) v = omap4_ctrl_pad_readl(offset); else v = omap_ctrl_readl(offset); v = ((omap_up_info->cts_padconf & 0x2 ? 0x0000FFFF : 0xFFFF0000) & v) | omap_up_info->cts_padvalue; if (cpu_is_omap44xx()) omap4_ctrl_pad_writel(v, offset); else omap_ctrl_writel(v, offset); } return 0; }