static void tuna_audio_init(void)
{
unsigned int aud_pwron;
/* twl6040 naudint */
omap_mux_init_signal("sys_nirq2.sys_nirq2", \
OMAP_PIN_INPUT_PULLUP);
/* aud_pwron */
if (omap4_tuna_get_type() == TUNA_TYPE_TORO &&
omap4_tuna_get_revision() >= 1)
aud_pwron = GPIO_AUD_PWRON_TORO_V1;
else
aud_pwron = GPIO_AUD_PWRON;
omap_mux_init_gpio(aud_pwron, OMAP_PIN_OUTPUT);
twl6040_codec.audpwron_gpio = aud_pwron;
omap_mux_init_signal("gpmc_a24.gpio_48", OMAP_PIN_OUTPUT | OMAP_MUX_MODE3);
omap_mux_init_signal("kpd_col3.gpio_171", OMAP_PIN_OUTPUT | OMAP_MUX_MODE3);
}
static const char *omap4_tuna_hw_rev_name(void) {
const char *ret;
const char **names;
int num;
int rev;
if (omap4_tuna_get_type() == TUNA_TYPE_MAGURO) {
names = omap4_tuna_hw_name_maguro;
num = ARRAY_SIZE(omap4_tuna_hw_name_maguro);
ret = "Maguro unknown";
} else {
names = omap4_tuna_hw_name_toro;
num = ARRAY_SIZE(omap4_tuna_hw_name_toro);
ret = "Toro unknown";
}
rev = omap4_tuna_get_revision();
if (rev >= num || !names[rev])
return ret;
return names[rev];
}
void __init omap4_tuna_display_init(void)
{
struct panel_s6e8aa0_data *panel;
if (omap4_tuna_get_revision() ==
(omap4_tuna_get_type() == TUNA_TYPE_MAGURO ? 2 : 1)) {
/*
* Older devices were not calibrated the same way as newer
* devices. These values are probably not correct, but the older
* devices tested look closer to the newer devices with these
* values than they do using the same register values as the
* newer devices.
*/
tuna_oled_data_m3.factory_info = &tuna_oled_factory_info_m2t1;
} else if (omap4_tuna_get_revision() <= 1) {
tuna_oled_data_m3.factory_info = &tuna_oled_factory_info_old;
}
if (panel_id == SM2)
panel = &tuna_oled_data_sm2;
else
panel = &tuna_oled_data_m3;
tuna_oled_device.data = panel;
omap4_ctrl_pad_writel(0x1FF80000,
OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
omap_mux_init_gpio(panel->reset_gpio, OMAP_PIN_OUTPUT);
pr_info("Using %ps\n", panel->factory_info);
omap_vram_set_sdram_vram(TUNA_FB_RAM_SIZE, 0);
omapfb_set_platform_data(&tuna_fb_pdata);
tuna_hdmi_mux_init();
omap_display_init(&tuna_dss_data);
}
/*
* Interrupt Handler for L3 error detection.
* 1) Identify the L3 clockdomain partition to which the error belongs to.
* 2) Identify the slave where the error information is logged
* 3) Print the logged information.
* 4) Add dump stack to provide kernel trace.
*
* Two Types of errors :
* 1) Custom errors in L3 :
* Target like DMM/FW/EMIF generates SRESP=ERR error
* 2) Standard L3 error:
* - Unsupported CMD.
* L3 tries to access target while it is idle
* - OCP disconnect.
* - Address hole error:
* If DSS/ISS/FDIF/USBHOSTFS access a target where they
* do not have connectivity, the error is logged in
* their default target which is DMM2.
*
* On High Secure devices, firewall errors are possible and those
* can be trapped as well. But the trapping is implemented as part
* secure software and hence need not be implemented here.
*/
static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
{
struct omap4_l3 *l3 = _l3;
int inttype, i, j, k;
int err_src = 0;
u32 std_err_main_addr, std_err_main, err_reg;
u32 base, slave_addr, clear, regoffset, masterid;
char *source_name;
/* Get the Type of interrupt */
inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
for (i = 0; i < L3_MODULES; i++) {
/*
* Read the regerr register of the clock domain
* to determine the source
*/
base = (u32)l3->l3_base[i];
err_reg = readl(base + l3_flagmux[i] + (inttype << 3));
/* Get the corresponding error and analyse */
if (err_reg) {
/* Identify the source from control status register */
for (j = 0; !(err_reg & (1 << j)); j++)
;
err_src = j;
/* Read the stderrlog_main_source from clk domain */
std_err_main_addr = base + *(l3_targ[i] + err_src);
std_err_main = readl(std_err_main_addr);
switch (std_err_main & CUSTOM_ERROR) {
case STANDARD_ERROR:
source_name =
l3_targ_stderrlog_main_name[i][err_src];
regoffset = targ_reg_offset[i][err_src];
slave_addr = std_err_main_addr +
L3_SLAVE_ADDRESS_OFFSET;
WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n",
source_name, readl(slave_addr));
#ifdef CONFIG_MACH_TUNA
/* Disable ABE L3 Interrupt on LTE boards */
if ((readl(base + regoffset + L3_MSTADDR) == 0xc0) &&
(readl(base + regoffset + L3_SLVADDR) == 0x3) &&
(omap4_tuna_get_type() == TUNA_TYPE_TORO)) {
pr_err("** Disabling ABE L3 interrupt for now....\n");
writel(0x1, base + regoffset + L3_MAINCTLREG);
writel(0x0, base + regoffset + L3_SVRTSTDLVL);
writel(0x0, base + regoffset + L3_SVRTCUSTOMLVL);
writel(0x0, base + regoffset + L3_MAIN);
writel(0x1F, base + regoffset + L3_ADDRSPACESIZELOG);
}
#endif
l3_dump_targ_context(base + regoffset);
/* clear the std error log*/
clear = std_err_main | CLEAR_STDERR_LOG;
writel(clear, std_err_main_addr);
break;
case CUSTOM_ERROR:
source_name =
l3_targ_stderrlog_main_name[i][err_src];
regoffset = targ_reg_offset[i][err_src];
WARN(true, "CUSTOM SRESP error with SOURCE:%s\n",
source_name);
masterid = readl(base + regoffset +
L3_CUSTOMINFO_MSTADDR);
for (k = 0;
k < NUM_OF_L3_MASTERS;
k++) {
if (masterid == l3_masters[k].id) {
pr_err("Master 0x%x %10s\n",
masterid,
l3_masters[k].name);
pr_err("%s OPCODE 0x%08x\n",
source_name,
readl(base + regoffset +
L3_CUSTOMINFO_OPCODE));
break;
}
}
/* clear the std error log*/
clear = std_err_main | CLEAR_STDERR_LOG;
writel(clear, std_err_main_addr);
break;
default:
/* Nothing to be handled here as of now */
break;
}
/* Error found so break the for loop */
break;
}
}
return IRQ_HANDLED;
}
static int sdp4430_modem_mcbsp_configure(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, int flag)
{
int ret = 0;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_pcm_substream *modem_substream[2];
struct snd_soc_pcm_runtime *modem_rtd;
int channels;
if (flag) {
modem_substream[substream->stream] =
snd_soc_get_dai_substream(rtd->card,
OMAP_ABE_BE_MM_EXT1,
substream->stream);
if (unlikely(modem_substream[substream->stream] == NULL))
return -ENODEV;
modem_rtd =
modem_substream[substream->stream]->private_data;
if (!mcbsp_cfg) {
if (omap4_tuna_get_type() == TUNA_TYPE_TORO) {
/* Set cpu DAI configuration */
ret = snd_soc_dai_set_fmt(modem_rtd->cpu_dai,
SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS);
if (unlikely(ret < 0)) {
printk(KERN_ERR "can't set Modem cpu DAI format\n");
goto exit;
}
/* McBSP2 fclk reparented to ABE_24M_FCLK */
ret = snd_soc_dai_set_sysclk(modem_rtd->cpu_dai,
OMAP_MCBSP_SYSCLK_CLKS_FCLK,
32 * 96 * params_rate(params),
SND_SOC_CLOCK_IN);
if (unlikely(ret < 0)) {
printk(KERN_ERR "can't set Modem cpu DAI sysclk\n");
goto exit;
}
/* assuming McBSP2 is S16_LE stereo */
ret = snd_soc_dai_set_clkdiv(modem_rtd->cpu_dai, 0, 96);
if (unlikely(ret < 0)) {
printk(KERN_ERR "can't set Modem cpu DAI clkdiv\n");
goto exit;
}
} else {
/* Set cpu DAI configuration */
ret = snd_soc_dai_set_fmt(modem_rtd->cpu_dai,
SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBM_CFM);
if (unlikely(ret < 0)) {
printk(KERN_ERR "can't set Modem cpu DAI configuration\n");
goto exit;
}
}
mcbsp_cfg = 1;
}
if (params != NULL) {
/* Configure McBSP internal buffer usage */
/* this need to be done for playback and/or record */
channels = params_channels(params);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
omap_mcbsp_set_rx_threshold(
modem_rtd->cpu_dai->id, channels);
else
omap_mcbsp_set_tx_threshold(
modem_rtd->cpu_dai->id, channels);
}
} else {
mcbsp_cfg = 0;
}
exit:
return ret;
}
