static void omap_pwm_led_power_on(struct omap_pwm_led *led) { pr_debug("%s%s: \n", PASS1,__func__); printk("!!!!!!!!!!%s the brightness is %d \n",__func__, led->brightness); if (led->powered){ printk("!!!!!!!!!!LED powered, returning \n"); return; } led->powered = 1; /* Select clock */ omap_dm_timer_enable(led->intensity_timer); omap_dm_timer_set_source(led->intensity_timer, OMAP_TIMER_SRC_SYS_CLK); omap_dm_timer_set_prescaler(led->intensity_timer, 0); /* Turn voltage on */ if (led->pdata->set_power != NULL) { printk("!!!!!!!!!!Turn voltage on \n"); led->pdata->set_power(led->pdata, 1); } /* Enable PWM timers */ if (led->blink_timer != NULL) { printk("!!!!!!!!!!Enable PWM timers \n"); omap_dm_timer_enable(led->blink_timer); omap_dm_timer_set_source(led->blink_timer, OMAP_TIMER_SRC_32_KHZ); omap_pwm_led_set_blink(led); } omap_dm_timer_set_load(led->intensity_timer, 1, 0xffffff00); }
static void omap_pwm_led_power_on(struct omap_pwm_led *led) { if (led->powered) return; led->powered = 1; pr_debug("%s: brightness: %i\n", __func__, led->brightness); /* Select clock */ omap_dm_timer_set_source(led->intensity_timer, OMAP_TIMER_SRC_SYS_CLK); /* Turn voltage on */ if (led->pdata->set_power != NULL) led->pdata->set_power(led->pdata, 1); /* explicitly enable the timer, saves some SAR later */ omap_dm_timer_enable(led->intensity_timer); /* Enable PWM timers */ if (led->blink_timer != NULL) { omap_dm_timer_set_source(led->blink_timer, OMAP_TIMER_SRC_32_KHZ); omap_pwm_led_set_blink(led); } }
static void __init omap2_gp_clockevent_init(void) { u32 tick_rate; gptimer = omap_dm_timer_request_specific(1); BUG_ON(gptimer == NULL); #if defined(CONFIG_OMAP_32K_TIMER) omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ); #else omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK); #endif tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer)); omap2_gp_timer_irq.dev_id = (void *)gptimer; setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq); omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW); clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC, clockevent_gpt.shift); clockevent_gpt.max_delta_ns = clockevent_delta2ns(0xffffffff, &clockevent_gpt); clockevent_gpt.min_delta_ns = clockevent_delta2ns(1, &clockevent_gpt); clockevent_gpt.cpumask = cpumask_of(0); clockevents_register_device(&clockevent_gpt); }
static void omap_pwm_led_power_on(struct omap_pwm_led *led) { if (led->powered) return; led->powered = 1; /* Select clock */ omap_dm_timer_enable(led->intensity_timer); omap_dm_timer_set_source(led->intensity_timer, OMAP_TIMER_SRC_32_KHZ); /* Turn voltage on */ if (led->pdata->set_power != NULL) led->pdata->set_power(led->pdata, 1); /* Enable PWM timers */ if (led->blink_timer != NULL) { omap_dm_timer_enable(led->blink_timer); omap_dm_timer_set_source(led->blink_timer, OMAP_TIMER_SRC_32_KHZ); omap_pwm_led_set_blink(led); } omap_dm_timer_write_counter(led->intensity_timer, 0xffffffff); omap_dm_timer_set_load(led->intensity_timer, 1, 0xffffff00); }
static int __init gptimer_request_init(void) { struct clk *gt_fclk; uint32_t gt_rate; /*Requesting for any available timer*/ timer_ptr = omap_dm_timer_request(); if (timer_ptr == NULL) { /*Timers are not available*/ printk(KERN_ERR "GPtimers are not available\n"); return -1; } switch (clock_type) { case 1: /*Set the clock source to 32Khz Clock*/ printk(KERN_INFO "Using OMAP_TIMER_SRC_32_KHZ source\n"); omap_dm_timer_set_source(timer_ptr, OMAP_TIMER_SRC_32_KHZ); break; case 2: /*Set the clock source to System Clock*/ printk(KERN_INFO "Using OMAP_TIMER_SRC_SYS_CLK source\n"); omap_dm_timer_set_source(timer_ptr, OMAP_TIMER_SRC_SYS_CLK); break; case 3: /*Set the clock source to System Clock*/ printk(KERN_INFO "Using OMAP_TIMER_SRC_EXT_CLK source\n"); omap_dm_timer_set_source(timer_ptr, OMAP_TIMER_SRC_EXT_CLK); break; default: printk(KERN_ERR "Invalid clock_type value. Use 1, 2 or 3\n"); return -1; } /*Figure out what IRQ our timer triggers*/ timer_irq = omap_dm_timer_get_irq(timer_ptr); /*Get clock rate in Hz*/ gt_fclk = omap_dm_timer_get_fclk(timer_ptr); gt_rate = clk_get_rate(gt_fclk); /*Start the timer!*/ omap_dm_timer_start(timer_ptr); printk(KERN_INFO "GP Timer initialized and started (%lu Hz, IRQ %d)\n", (long unsigned)gt_rate, timer_irq); return 0; }
int __init panel_cpt_wvga_48_init(struct omap_dss_platform_data *disp_data) { const struct archos_display_config *disp_cfg; int ret = -ENODEV; disp_cfg = omap_get_config( ARCHOS_TAG_DISPLAY, struct archos_display_config ); if (disp_cfg == NULL) return ret; if ( hardware_rev >= disp_cfg->nrev ) { printk(KERN_DEBUG "archos_display_init: hardware_rev (%i) >= nrev (%i)\n", hardware_rev, disp_cfg->nrev); return ret; } display_gpio = disp_cfg->rev[hardware_rev]; /* * Backlight configuration, * TODO: retrieve GPT id and mux through omap_get_config() */ GPIO_INIT_OUTPUT(display_gpio.bkl_pwon); bkl_pwm = omap_dm_timer_request_specific(display_gpio.bkl_pwm.timer); if (bkl_pwm) { omap_dm_timer_set_source(bkl_pwm, OMAP_TIMER_SRC_SYS_CLK); omap_cfg_reg(display_gpio.bkl_pwm.mux_cfg); } else pr_err("panel_cpt_wvga_48_init: no backlight PWM\n"); /* * Vcom configuration, */ vcom_pwm = omap_dm_timer_request_specific(display_gpio.vcom_pwm.timer); if (vcom_pwm) { omap_dm_timer_set_source(vcom_pwm, OMAP_TIMER_SRC_SYS_CLK); omap_cfg_reg(display_gpio.vcom_pwm.mux_cfg); } else pr_err("panel_cpt_wvga_48_init: no vcom PWM\n"); panel_init(&cpt_wvga_48_panel); #if defined(CONFIG_FB_OMAP_BOOTLOADER_INIT) panel_set_backlight_level(NULL, 255); #endif disp_data->displays[disp_data->num_displays] = &cpt_wvga_48_panel; disp_data->num_displays++; return 0; }
static PVRSRV_ERROR AcquireGPTimer(SYS_SPECIFIC_DATA *psSysSpecData) { PVR_ASSERT(psSysSpecData->psGPTimer == NULL); psSysSpecData->psGPTimer = omap_dm_timer_request_specific(GPTIMER_TO_USE); if (psSysSpecData->psGPTimer == NULL) { PVR_DPF((PVR_DBG_WARNING, "%s: omap_dm_timer_request_specific failed", __FUNCTION__)); return PVRSRV_ERROR_CLOCK_REQUEST_FAILED; } omap_dm_timer_set_source(psSysSpecData->psGPTimer, OMAP_TIMER_SRC_SYS_CLK); omap_dm_timer_enable(psSysSpecData->psGPTimer); omap_dm_timer_set_load_start(psSysSpecData->psGPTimer, 1, 0); omap_dm_timer_start(psSysSpecData->psGPTimer); psSysSpecData->sTimerRegPhysBase.uiAddr = SYS_OMAP3_GPTIMER_REGS_SYS_PHYS_BASE; return PVRSRV_OK; }
static int gptimer_start(void) { int err; u32 count = counter_config[0].count; BUG_ON(gptimer != NULL); /* First try to request timers from CORE power domain for OMAP3 */ if (cpu_is_omap34xx()) { gptimer = omap_dm_timer_request_specific(10); if (gptimer == NULL) gptimer = omap_dm_timer_request_specific(11); } /* Just any timer would be fine */ if (gptimer == NULL) gptimer = omap_dm_timer_request(); if (gptimer == NULL) return -ENODEV; omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ); err = request_irq(omap_dm_timer_get_irq(gptimer), gptimer_interrupt, IRQF_DISABLED, "oprofile gptimer", NULL); if (err) { omap_dm_timer_free(gptimer); gptimer = NULL; printk(KERN_ERR "oprofile: unable to request gptimer IRQ\n"); return err; } if (count < 1) count = 1; omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - count); omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW); return 0; }
static PVRSRV_ERROR AcquireGPTimer(SYS_SPECIFIC_DATA *psSysSpecData) { PVR_ASSERT(psSysSpecData->psGPTimer == NULL); /* * This code could try requesting registers 9, 10, and 11, * stopping at the first succesful request. We'll stick with * 11 for now, as it avoids having to hard code yet more * physical addresses into the code. */ psSysSpecData->psGPTimer = omap_dm_timer_request_specific(GPTIMER_TO_USE); if (psSysSpecData->psGPTimer == NULL) { PVR_DPF((PVR_DBG_WARNING, "%s: omap_dm_timer_request_specific failed", __FUNCTION__)); return PVRSRV_ERROR_CLOCK_REQUEST_FAILED; } /* Set timer source to system clock */ omap_dm_timer_set_source(psSysSpecData->psGPTimer, OMAP_TIMER_SRC_SYS_CLK); omap_dm_timer_enable(psSysSpecData->psGPTimer); /* Set autoreload, and start value of 0 */ omap_dm_timer_set_load_start(psSysSpecData->psGPTimer, 1, 0); omap_dm_timer_start(psSysSpecData->psGPTimer); /* * The DM timer API doesn't have a mechansim for obtaining the * physical address of the counter register. */ psSysSpecData->sTimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_REGS_SYS_PHYS_BASE; return PVRSRV_OK; }
static int __devinit cloudsurfer_wakeup_probe(struct platform_device *pdev) { struct cloudsurfer_wakeup_struct *wkup; struct input_dev *wkup_in; u32 tick_rate, cycles; int err; /* Data structure allocation */ wkup = kzalloc(sizeof(struct cloudsurfer_wakeup_struct), GFP_KERNEL); wkup_in = input_allocate_device(); if (!wkup_in) { printk("CLOUDSURFER - Can't allocate wakeup timer input\n"); err = -ENOMEM; goto error_input_dev; } /* Timer allocation and setup */ if ( (wkup->timer=omap_dm_timer_request_specific(1)) == NULL ) { printk("CLOUDSURFER - can't allocate wakeup timer\n"); err = -ENODEV; goto error_timer; } wkup->irq = omap_dm_timer_get_irq(wkup->timer); omap_dm_timer_set_source(wkup->timer,OMAP_TIMER_SRC_32_KHZ); tick_rate = clk_get_rate(omap_dm_timer_get_fclk(wkup->timer)); cycles = tick_rate * wakeup_seconds; omap_dm_timer_stop(wkup->timer); input_set_capability(wkup_in,EV_MSC,1); input_set_capability(wkup_in,EV_MSC,2); wkup_in->name = "cloudsurfer-wakeup"; wkup_in->phys = "cloudsurfer-wakeup/input0"; wkup_in->dev.parent = &pdev->dev; cloudsurfer_irq_data.dev_id = wkup_in; setup_irq(wkup->irq,&cloudsurfer_irq_data); input_set_drvdata(wkup_in, wkup); err = input_register_device(wkup_in); if (err) { printk("CLOUDSURFER -Can't register wakeup timer: %d\n", err); goto error_register; } omap_dm_timer_set_int_enable(wkup->timer,OMAP_TIMER_INT_OVERFLOW); omap_dm_timer_set_load_start(wkup->timer, 1, 0xffffffff - cycles); platform_set_drvdata(pdev, wkup_in); return 0; error_register: free_irq(wkup->irq, NULL); error_timer: input_free_device(wkup_in); error_input_dev: kfree(wkup); return err; }
static int backlight_gptimer_init(struct omap_dss_device *dssdev) { struct ltn101al03 *lcd = dev_get_drvdata(&dssdev->dev); int ret; pr_info("(%s): called (@%d)\n", __func__, __LINE__); if (lcd->pdata->set_gptimer_idle) lcd->pdata->set_gptimer_idle(); lcd->gptimer = omap_dm_timer_request_specific(lcd->pdata->backlight_gptimer_num); if (lcd->gptimer == NULL) { pr_err("failed to request pwm timer\n"); ret = -ENODEV; goto err_dm_timer_request; } ret = omap_dm_timer_set_source(lcd->gptimer, OMAP_TIMER_SRC_SYS_CLK); if (ret < 0) goto err_dm_timer_src; return ret; err_dm_timer_src: omap_dm_timer_free(lcd->gptimer); lcd->gptimer = NULL; err_dm_timer_request: return ret; }
/* * For requesting the "GPtimer#" also for setting the default value in registers */ static int vibtonz_ReqGPTimer(void) { int ret; // printk("[VIBRATOR] %s \n",__func__); gptimer=omap_dm_timer_request_specific(VIBE_GPTIMER_NUM); if (gptimer == NULL) { // printk("failed to request pwm timer\n"); ret = -ENODEV; } // omap_dm_timer_enable(gptimer); omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK); omap_dm_timer_disable(gptimer); // omap_dm_timer_set_load(gptimer, 1, 0xffffff00); /* Change for Interrupt */ // omap2_gp_timer_irq.dev_id=(void *)gptimer; // setup_irq(omap_dm_timer_get_irq(gptimer),&omap2_gp_timer_irq); /* Request for interrupt Number */ // omap_dm_timer_set_int_enable(gptimer,OMAP_TIMER_INT_OVERFLOW); // omap_dm_timer_set_int_enable(gptimer,OMAP_TIMER_INT_MATCH); // omap_dm_timer_stop(gptimer); // omap_dm_timer_disable(gptimer); return 0; }
static int __init archos_irblaster_pwn_init(void) { int ret; const struct archos_irblaster_config *irblaster_cfg; irblaster_cfg = omap_get_config( ARCHOS_TAG_IRBLASTER, struct archos_irblaster_config ); if (irblaster_cfg == NULL) { printk(KERN_DEBUG "archos_irblaster_pwn_init: no board configuration found\n"); return -ENODEV; } if ( hardware_rev >= irblaster_cfg->nrev ) { printk(KERN_DEBUG "archos_irblaster_pwn_init: hardware_rev (%i) >= nrev (%i)\n", hardware_rev, irblaster_cfg->nrev); return -ENODEV; } irblaster_pwm = irblaster_cfg->rev[hardware_rev].irblaster_pwm; irb_pwm_timer = omap_dm_timer_request_specific(irblaster_pwm.timer); if (irb_pwm_timer) { omap_dm_timer_set_source(irb_pwm_timer, OMAP_TIMER_SRC_SYS_CLK); omap_cfg_reg(irblaster_pwm.mux_cfg); } else pr_err("archos_irblaster_pwn_init: no irblaster PWM\n"); ret = platform_device_register(&irblaster_pwm_device); if (!ret) { device_create_file(&irblaster_pwm_device.dev, &dev_attr_frequency); device_create_file(&irblaster_pwm_device.dev, &dev_attr_duty_cycle); } return ret; }
/* Setup free-running counter for clocksource */ static void __init omap2_gp_clocksource_init(void) { static struct omap_dm_timer *gpt; u32 tick_rate, tick_period; static char err1[] __initdata = KERN_ERR "%s: failed to request dm-timer\n"; static char err2[] __initdata = KERN_ERR "%s: can't register clocksource!\n"; gpt = omap_dm_timer_request(); if (!gpt) printk(err1, clocksource_gpt.name); gpt_clocksource = gpt; omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK); tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt)); tick_period = (tick_rate / HZ) - 1; omap_dm_timer_set_load_start(gpt, 1, 0); clocksource_gpt.mult = clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift); if (clocksource_register(&clocksource_gpt)) printk(err2, clocksource_gpt.name); }
static inline int proc44x_start(struct device *dev, u32 start_addr) { struct platform_device *pdev = to_platform_device(dev); struct omap_rproc *obj = (struct omap_rproc *)platform_get_drvdata( to_platform_device(dev)); int ret = 0; /* Enable the Timer that would be used by co-processor */ if (obj->timer_id >= 0) { obj->dmtimer = omap_dm_timer_request_specific(obj->timer_id); if (!obj->dmtimer) { ret = -EBUSY; goto err_start; } omap_dm_timer_set_int_enable(obj->dmtimer, OMAP_TIMER_INT_OVERFLOW); omap_dm_timer_set_source(obj->dmtimer, OMAP_TIMER_SRC_SYS_CLK); } ret = omap_device_enable(pdev); if (ret) goto err_start; obj->state = OMAP_RPROC_RUNNING; return 0; err_start: dev_err(dev, "%s error 0x%x\n", __func__, ret); return ret; }
static int lirc_rx51_init_port(struct lirc_rx51 *lirc_rx51) { struct clk *clk_fclk; int retval, pwm_timer = lirc_rx51->pwm_timer_num; lirc_rx51->pwm_timer = omap_dm_timer_request_specific(pwm_timer); if (lirc_rx51->pwm_timer == NULL) { dev_err(lirc_rx51->dev, ": Error requesting GPT%d timer\n", pwm_timer); return -EBUSY; } lirc_rx51->pulse_timer = omap_dm_timer_request(); if (lirc_rx51->pulse_timer == NULL) { dev_err(lirc_rx51->dev, ": Error requesting pulse timer\n"); retval = -EBUSY; goto err1; } omap_dm_timer_set_source(lirc_rx51->pwm_timer, OMAP_TIMER_SRC_SYS_CLK); omap_dm_timer_set_source(lirc_rx51->pulse_timer, OMAP_TIMER_SRC_SYS_CLK); omap_dm_timer_enable(lirc_rx51->pwm_timer); omap_dm_timer_enable(lirc_rx51->pulse_timer); lirc_rx51->irq_num = omap_dm_timer_get_irq(lirc_rx51->pulse_timer); retval = request_irq(lirc_rx51->irq_num, lirc_rx51_interrupt_handler, IRQF_DISABLED | IRQF_SHARED, "lirc_pulse_timer", lirc_rx51); if (retval) { dev_err(lirc_rx51->dev, ": Failed to request interrupt line\n"); goto err2; } clk_fclk = omap_dm_timer_get_fclk(lirc_rx51->pwm_timer); lirc_rx51->fclk_khz = clk_fclk->rate / 1000; return 0; err2: omap_dm_timer_free(lirc_rx51->pulse_timer); err1: omap_dm_timer_free(lirc_rx51->pwm_timer); return retval; }
static inline int omap_rproc_start(struct rproc *rproc, u64 bootaddr) { struct device *dev = rproc->dev; struct platform_device *pdev = to_platform_device(dev); struct omap_rproc_pdata *pdata = dev->platform_data; struct omap_rproc_timers_info *timers = pdata->timers; struct omap_rproc_priv *rpp = rproc->priv; int i; int ret = 0; if (rproc->secure_mode) { rproc->secure_reset = true; ret = rproc_drm_invoke_service(rproc->secure_mode); if (ret) { dev_err(rproc->dev, "rproc_drm_invoke_service failed " "for secure_enable ret = 0x%x\n", ret); return -ENXIO; } } #ifdef CONFIG_REMOTE_PROC_AUTOSUSPEND ret = _init_pm_flags(rproc); if (ret) return ret; #endif for (i = 0; i < pdata->timers_cnt; i++) { timers[i].odt = omap_dm_timer_request_specific(timers[i].id); if (!timers[i].odt) { ret = -EBUSY; goto out; } omap_dm_timer_set_source(timers[i].odt, OMAP_TIMER_SRC_SYS_CLK); #ifdef CONFIG_REMOTEPROC_WATCHDOG /* GPT 9 & 11 (ipu); GPT 6 (dsp) are used as watchdog timers */ if ((!strcmp(rproc->name, "dsp") && timers[i].id == 6) || (!strcmp(rproc->name, "ipu") && (timers[i].id == DUCATI_WDT_TIMER_1 || timers[i].id == DUCATI_WDT_TIMER_2))) { ret = request_irq(omap_dm_timer_get_irq(timers[i].odt), omap_rproc_watchdog_isr, IRQF_DISABLED, "rproc-wdt", rproc); /* Clean counter, remoteproc proc will set the value */ omap_dm_timer_set_load(timers[i].odt, 0, 0); } #endif } rpp->bootaddr = bootaddr; ret = omap_device_enable(pdev); out: if (ret) { while (i--) { omap_dm_timer_free(timers[i].odt); timers[i].odt = NULL; } } return ret; }
// Initialize the kernel module static int __init gptimer_test_init(void) { int ret = 0; struct clk *gt_fclk; uint32_t gt_rate; printk("gptimer test: starting moudle init\n"); // request a timer (we are asking for ANY open timer, see dmtimer.c for details on how this works) timer_ptr = omap_dm_timer_request(); if(timer_ptr == NULL){ // oops, no timers available printk("gptimer test: No more gp timers available, bailing out\n"); return -1; } // set the clock source to system clock omap_dm_timer_set_source(timer_ptr, OMAP_TIMER_SRC_SYS_CLK); // set prescalar to 1:1 omap_dm_timer_set_prescaler(timer_ptr, 32); // figure out what IRQ our timer triggers timer_irq = omap_dm_timer_get_irq(timer_ptr); // install our IRQ handler for our timer ret = request_irq(timer_irq, timer_irq_handler, IRQF_DISABLED | IRQF_TIMER , "gptimer test", timer_irq_handler); if(ret){ printk("gptimer test: request_irq failed (on irq %d), bailing out\n", timer_irq); return ret; } // get clock rate in Hz gt_fclk = omap_dm_timer_get_fclk(timer_ptr); gt_rate = clk_get_rate(gt_fclk); // set preload, and autoreload // we set it to the clock rate in order to get 1 overflow every second omap_dm_timer_set_load(timer_ptr, 1, 0xFFFFFFFF - gt_rate); // setup timer to trigger our IRQ on the overflow event omap_dm_timer_set_int_enable(timer_ptr, OMAP_TIMER_INT_OVERFLOW); // start the timer! omap_dm_timer_start(timer_ptr); // done! printk("gptimer test: GP Timer initialized and started (%lu Hz, IRQ %d)\n", (long unsigned)gt_rate, timer_irq); // return sucsess return 0; }
static void __init omap2_gp_clockevent_init(void) { u32 tick_rate; int src; u32* time_base = ioremap(0x4A318000, SZ_4K); inited = 1; gptimer = omap_dm_timer_request_specific(gptimer_id); BUG_ON(gptimer == NULL); gptimer_wakeup = gptimer; #if defined(CONFIG_OMAP_32K_TIMER) src = OMAP_TIMER_SRC_32_KHZ; #else src = OMAP_TIMER_SRC_SYS_CLK; WARN(gptimer_id == 12, "WARNING: GPTIMER12 can only use the " "secure 32KiHz clock source\n"); #endif if (gptimer_id != 12) WARN(IS_ERR_VALUE(omap_dm_timer_set_source(gptimer, src)), "timer-gp: omap_dm_timer_set_source() failed\n"); tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer)); pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n", gptimer_id, tick_rate); print_timer(time_base); omap2_gp_timer_irq.dev_id = (void *)gptimer; //TODO: slow for safety omap_dm_timer_set_load_start(gptimer, 1, 0); print_timer(time_base); setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq); clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC, clockevent_gpt.shift); clockevent_gpt.max_delta_ns = clockevent_delta2ns(0xffffffff, &clockevent_gpt); clockevent_gpt.min_delta_ns = clockevent_delta2ns(3, &clockevent_gpt); /* Timer internal resynch latency. */ clockevent_gpt.cpumask = cpumask_of(0); clockevents_register_device(&clockevent_gpt); omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW); print_timer(time_base); }
static void __init omap2_gp_timer_init(void) { u32 tick_period; omap_dm_timer_init(); gptimer = omap_dm_timer_request_specific(1); BUG_ON(gptimer == NULL); omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK); tick_period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / 100; tick_period -= 1; setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq); omap2_gp_timer_start(tick_period); }
/* * Driver Initialization */ static int __init hello_init(void) { int ret; /* Request dynamic allocation of a device major number */ if (alloc_chrdev_region(&my_dev_number, 0, 1, DEVICE_NAME) < 0) { printk(KERN_DEBUG "Can't register device\n"); return -1; } /* Populate sysfs entries */ my_dev_class = class_create(THIS_MODULE, DEVICE_NAME); /* Allocate memory for the per-device structure */ hrt_devp = kmalloc(sizeof(struct HRT_dev), GFP_KERNEL); /* Allocate memory for the timer */ timer = kmalloc(sizeof(struct omap_dm_timer), GFP_KERNEL); /* Request a timer */ timer = omap_dm_timer_request(); /* Set timer source */ omap_dm_timer_set_source(timer,OMAP_TIMER_SRC_SYS_CLK); /* enable the timer */ omap_dm_timer_enable(timer); /* Request I/O region */ sprintf(hrt_devp->name, DEVICE_NAME); /* Connect the file operations with the cdev */ cdev_init(&hrt_devp->cdev, &My_fops); hrt_devp->cdev.owner = THIS_MODULE; /* Connect the major/minor number to the cdev */ ret = cdev_add(&hrt_devp->cdev, (my_dev_number), 1); if (ret) { printk("Bad cdev\n"); return ret; } /* Send uevents to udev, so it'll create /dev nodes */ device_create(my_dev_class, NULL, MKDEV(MAJOR(my_dev_number), 0), NULL, DEVICE_NAME); printk("HRT Driver Initialized.\n"); return 0; }
static void __init omap2_gp_clockevent_init(void) { u32 tick_rate; int src; inited = 1; gptimer = omap_dm_timer_request_specific(gptimer_id); BUG_ON(gptimer == NULL); #if defined(CONFIG_OMAP_32K_TIMER) src = OMAP_TIMER_SRC_32_KHZ; #else src = OMAP_TIMER_SRC_SYS_CLK; WARN(gptimer_id == 12, "WARNING: GPTIMER12 can only use the " "secure 32KiHz clock source\n"); #endif if (gptimer_id != 12) WARN(IS_ERR_VALUE(omap_dm_timer_set_source(gptimer, src)), "timer-gp: omap_dm_timer_set_source() failed\n"); tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer)); if (cpu_is_omap44xx()) /* Assuming 32kHz clk is driving GPT1 */ tick_rate = 32768; /* FIXME: */ pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n", gptimer_id, tick_rate); omap2_gp_timer_irq.dev_id = (void *)gptimer; setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq); omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW); clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC, clockevent_gpt.shift); clockevent_gpt.max_delta_ns = clockevent_delta2ns(0xffffffff, &clockevent_gpt); clockevent_gpt.min_delta_ns = clockevent_delta2ns(3, &clockevent_gpt); /* Timer internal resynch latency. */ clockevent_gpt.cpumask = cpumask_of(0); clockevents_register_device(&clockevent_gpt); }
/*! ****************************************************************************** @Function AcquireGPTimer @Description Acquire a GP timer @Return PVRSRV_ERROR ******************************************************************************/ static PVRSRV_ERROR AcquireGPTimer(SYS_SPECIFIC_DATA *psSysSpecData) { PVR_ASSERT(psSysSpecData->psGPTimer == NULL); /* * This code has problems on module reload for OMAP5 running Linux * 3.4.10, due to omap2_dm_timer_set_src (called by * omap_dm_timer_request_specific), being unable to set the parent * clock to OMAP_TIMER_SRC_32_KHZ. * Not calling omap_dm_timer_set_source doesn't help. */ #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) || !defined(MODULE) /* * This code could try requesting registers 9, 10, and 11, * stopping at the first succesful request. We'll stick with * 11 for now, as it avoids having to hard code yet more * physical addresses into the code. */ psSysSpecData->psGPTimer = omap_dm_timer_request_specific(GPTIMER_TO_USE); if (psSysSpecData->psGPTimer == NULL) { PVR_DPF((PVR_DBG_WARNING, "%s: omap_dm_timer_request_specific failed", __FUNCTION__)); return PVRSRV_ERROR_CLOCK_REQUEST_FAILED; } omap_dm_timer_set_source(psSysSpecData->psGPTimer, OMAP_TIMER_SRC_SYS_CLK); omap_dm_timer_enable(psSysSpecData->psGPTimer); /* Set autoreload, and start value of 0 */ omap_dm_timer_set_load_start(psSysSpecData->psGPTimer, 1, 0); omap_dm_timer_start(psSysSpecData->psGPTimer); /* * The DM timer API doesn't have a mechanism for obtaining the * physical address of the counter register. */ psSysSpecData->sTimerRegPhysBase.uiAddr = SYS_OMAP3430_GP11TIMER_REGS_SYS_PHYS_BASE; #else /* (LINUX_VERSION_CODE <= KERNEL_VERSION(3,4,0)) || !defined(MODULE) */ (void)psSysSpecData; #endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(3,4,0)) || !defined(MODULE) */ return PVRSRV_OK; }
int init_gptimer12 ( void ) { gptimer12_count = 0; memset( &timer_manager, 0, sizeof( timer_manager ) ); battery_timer = omap_dm_timer_request_specific(12); BUG_ON( battery_timer == NULL ); omap_dm_timer_set_source( battery_timer, OMAP_TIMER_SRC_32_KHZ ); //battery_timer_irq.dev_id = (void *)battery_timer; //setup_irq(omap_dm_timer_get_irq(battery_timer), &battery_timer_irq); //omap_dm_timer_set_int_enable(battery_timer, OMAP_TIMER_INT_OVERFLOW); //omap_dm_timer_set_prescaler(battery_timer, GP_TIMER12_PRESCALAR); omap_dm_timer_write_status( battery_timer, OMAP_TIMER_INT_OVERFLOW | OMAP_TIMER_INT_CAPTURE | OMAP_TIMER_INT_MATCH ); omap_dm_timer_disable( battery_timer ); return 0; }
static int __init omap4_setup_gpt2(void) { /* Set up GPT2 for the WA */ gptimer2 = omap_dm_timer_request_specific(2); BUG_ON(gptimer2 == NULL); printk(KERN_INFO "Enabling AXI2OCP errata Fix \n"); omap_dm_timer_set_source(gptimer2, OMAP_TIMER_SRC_32_KHZ); gpt2_timer_irq.dev_id = (void *)gptimer2; setup_irq(omap_dm_timer_get_irq(gptimer2), &gpt2_timer_irq); omap_dm_timer_set_int_enable(gptimer2, OMAP_TIMER_INT_OVERFLOW); /* * Timer reload value is used based on mpu @ 600 MHz * And hence bridge is at 300 MHz. 65K cycle = 216 uS * 6 * 1/32 kHz => ~187 us */ omap_dm_timer_set_load_start(gptimer2, 1, 0xffffff06); return 0; }
static int sholest_lvibrator_initialization(void) { unsigned long load_reg, cmp_reg; uint32_t timer_rate = 0; int ret = 0; vib_pwm_timer = omap_dm_timer_request_specific(11); if (vib_pwm_timer == NULL) ret = -ENODEV; timer_rate = clk_get_rate(omap_dm_timer_get_fclk(vib_pwm_timer)); load_reg = timer_rate * SHOLEST_LVIBRATOR_PERIOD / 1000000; cmp_reg = timer_rate * (SHOLEST_LVIBRATOR_PERIOD - SHOLEST_LVIBRATOR_DUTY) / 1000000; omap_dm_timer_set_source(vib_pwm_timer, OMAP_TIMER_SRC_32_KHZ); omap_dm_timer_set_load(vib_pwm_timer, 1, -load_reg); omap_dm_timer_set_match(vib_pwm_timer, 1, -cmp_reg); omap_dm_timer_set_pwm(vib_pwm_timer, 0, 1, OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE); omap_dm_timer_write_counter(vib_pwm_timer, -2); return 0; }
/* * Request dmtimer * TESTED */ struct omap_dm_timer *HRTDriver_reserve_timer(void) { //Get device private data //struct HRT_dev *hrt_devp = file->private_data; struct omap_dm_timer *timer; timer = omap_dm_timer_request(); omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_SYS_CLK); omap_dm_timer_enable(timer); if (!timer) printk("\nTimer not reserved!\n"); else printk("\nTimer succesfully reserved!\n"); //setting the load enables the timer //omap_dm_timer_set_load_start(hrt_devp->gptimer, 0, 0); omap_dm_timer_start(timer); return timer; }
/* Setup free-running counter for clocksource */ static void __init omap2_gp_clocksource_init(void) { static struct omap_dm_timer *gpt; u32 tick_rate; static char err1[] __initdata = KERN_ERR "%s: failed to request dm-timer\n"; static char err2[] __initdata = KERN_ERR "%s: can't register clocksource!\n"; gpt = omap_dm_timer_request(); if (!gpt) printk(err1, clocksource_gpt.name); gpt_clocksource = gpt; omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK); tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt)); omap_dm_timer_set_load_start(gpt, 1, 0); init_sched_clock(&cd, dmtimer_update_sched_clock, 32, tick_rate); if (clocksource_register_hz(&clocksource_gpt, tick_rate)) printk(err2, clocksource_gpt.name); }
static int _init_gpt(void) { int irqno; int ret = 0; if ((gpt_pwm_list[IRBLASTER_PWM].timer = omap_dm_timer_request_specific(gpt_pwm_list[IRBLASTER_PWM].no)) == NULL) { printk(KERN_ERR "%s: failed to request dm-timer (%d)\n", gpt_pwm_list[IRBLASTER_PWM].name, gpt_pwm_list[IRBLASTER_PWM].no); return -ENODEV; } omap_dm_timer_set_source(gpt_pwm_list[IRBLASTER_PWM].timer, gpt_pwm_list[IRBLASTER_PWM].source); gpt_pwm_list[IRBLASTER_PWM].rate = clk_get_rate(omap_dm_timer_get_fclk(gpt_pwm_list[IRBLASTER_PWM].timer)); printk(KERN_DEBUG "%s (%d) timer rate is: %d\n", gpt_pwm_list[IRBLASTER_PWM].name, gpt_pwm_list[IRBLASTER_PWM].no, gpt_pwm_list[IRBLASTER_PWM].rate); if ((gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer = omap_dm_timer_request_specific(gpt_pwm_list[IRBLASTER_TIMER_CTRL].no)) == NULL) { printk(KERN_ERR "%s: failed to request dm-timer (%d)\n", gpt_pwm_list[IRBLASTER_TIMER_CTRL].name, gpt_pwm_list[IRBLASTER_TIMER_CTRL].no); omap_dm_timer_free(gpt_pwm_list[IRBLASTER_PWM].timer); return -ENODEV; } omap_dm_timer_set_source(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer, gpt_pwm_list[IRBLASTER_TIMER_CTRL].source); gpt_pwm_list[IRBLASTER_TIMER_CTRL].rate = clk_get_rate(omap_dm_timer_get_fclk(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer)); printk(KERN_DEBUG "%s (%d) timer rate is: %d\n", gpt_pwm_list[IRBLASTER_TIMER_CTRL].name, gpt_pwm_list[IRBLASTER_TIMER_CTRL].no, gpt_pwm_list[IRBLASTER_TIMER_CTRL].rate); /* select irblaster configuration */ _select_irb_config(); /* enable timer clock */ omap_dm_timer_enable(gpt_pwm_list[IRBLASTER_PWM].timer); omap_dm_timer_enable(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer); /* set modulation mod */ /* trigger on overflow and match */ omap_dm_timer_set_pwm(gpt_pwm_list[IRBLASTER_PWM].timer,0,1,2); omap_dm_timer_set_pwm(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer, 0, 1, 2); //if ( gpt_pwm_list[IRBLASTER_TIMER_CTRL].mux_config ) // omap_cfg_reg(gpt_pwm_list[IRBLASTER_TIMER_CTRL].mux_config); irqno = omap_dm_timer_get_irq(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer); if (request_irq(irqno, omap2_irblaster_timer_interrupt, IRQF_DISABLED, "gp timer", NULL)) { ret = -EBUSY; goto failed_request_irq; } omap_dm_timer_set_int_enable(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer, IRBLASTER_TIMER_CTRL_IT_TYPE); /* disable timer clocks after init */ omap_dm_timer_disable(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer); omap_dm_timer_disable(gpt_pwm_list[IRBLASTER_PWM].timer); init_waitqueue_head(&irb_wait); _gio_debug_init(); return 0; failed_request_irq: omap_dm_timer_free(gpt_pwm_list[IRBLASTER_PWM].timer); omap_dm_timer_free(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer); return ret; }
static int __init pwm_start(void) { int ret = 0; struct clk *timer_fclk; uint32_t gt_rate; printk(KERN_INFO "Loading PWM Module... \n"); // request any timer timer_ptr = omap_dm_timer_request(); if(timer_ptr == NULL){ // no timers available printk("pwm module: No more gp timers available, bailing out\n"); return -1; } // set the clock source to the system clock ret = omap_dm_timer_set_source(timer_ptr, OMAP_TIMER_SRC_SYS_CLK); if(ret) { printk("pwm module: could not set source\n"); return -1; } // set prescalar to 1:1 omap_dm_timer_set_prescaler(timer_ptr, 0); // figure out what IRQ our timer triggers timer_irq = omap_dm_timer_get_irq(timer_ptr); // install our IRQ handler for our timer ret = request_irq(timer_irq, timer_irq_handler, IRQF_DISABLED | IRQF_TIMER , "pwm", timer_irq_handler); if(ret){ printk("pwm module: request_irq failed (on irq %d), bailing out\n", timer_irq); return ret; } // get clock rate in Hz and add it to struct timer_fclk = omap_dm_timer_get_fclk(timer_ptr); gt_rate = clk_get_rate(timer_fclk); pwm_data_ptr.timer_rate = gt_rate; // set preload, and autoreload // we set it to a default of 1kHz set_pwm_freq(1000); // setup timer to trigger IRQ on the overflow omap_dm_timer_set_int_enable(timer_ptr, OMAP_TIMER_INT_OVERFLOW); // start the timer omap_dm_timer_start(timer_ptr); // done! printk("pwm module: GP Timer initialized and started (%lu Hz, IRQ %d)\n", (long unsigned)gt_rate, timer_irq); // setup a GPIO pwm_setup_pin(38); pwm_data_ptr.pin = 38; set_pwm_dutycycle(1,150); // return success return 0; }