int send_mbox_callback(void *arg)
{
struct wmd_dev_context *dev_context;
struct cfg_hostres *resources;
u32 temp;
struct dspbridge_platform_data *pdata =
omap_dspbridge_dev->dev.platform_data;
dev_get_wmd_context(dev_get_first(), &dev_context);
if (!dev_context || !dev_context->resources)
return -EFAULT;
resources = dev_context->resources;
if (dev_context->dw_brd_state == BRD_DSP_HIBERNATION ||
dev_context->dw_brd_state == BRD_HIBERNATION) {
/* Restart the peripheral clocks */
dsp_peripheral_clocks_enable(dev_context, NULL);
#ifdef CONFIG_BRIDGE_WDT3
dsp_wdt_enable(true);
#endif
/*
* 2:0 AUTO_IVA2_DPLL - Enabling IVA2 DPLL auto control
* in CM_AUTOIDLE_PLL_IVA2 register
*/
(*pdata->dsp_cm_write)(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL);
/*
* 7:4 IVA2_DPLL_FREQSEL - IVA2 internal frq set to
* 0.75 MHz - 1.0 MHz
* 2:0 EN_IVA2_DPLL - Enable IVA2 DPLL in lock mode
*/
(*pdata->dsp_cm_rmw_bits)(OMAP3430_IVA2_DPLL_FREQSEL_MASK |
OMAP3430_EN_IVA2_DPLL_MASK,
0x3 << OMAP3430_IVA2_DPLL_FREQSEL_SHIFT |
0x7 << OMAP3430_EN_IVA2_DPLL_SHIFT,
OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
/* Restore mailbox settings */
omap_mbox_restore_ctx(dev_context->mbox);
/* Access MMU SYS CONFIG register to generate a short wakeup */
temp = *(reg_uword32 *) (resources->dw_dmmu_base + 0x10);
dev_context->dw_brd_state = BRD_RUNNING;
} else if (dev_context->dw_brd_state == BRD_RETENTION) {
/* Restart the peripheral clocks */
dsp_peripheral_clocks_enable(dev_context, NULL);
dev_context->dw_brd_state = BRD_RUNNING;
}
return 0;
}
int sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val)
{
#ifdef CONFIG_TIDSPBRIDGE_DVFS
u32 opplevel = 0;
#endif
struct omap_dsp_platform_data *pdata =
omap_dspbridge_dev->dev.platform_data;
struct cfg_hostres *resources = dev_context->resources;
int status = 0;
u32 temp;
if (!dev_context->mbox)
return 0;
if (!resources)
return -EPERM;
if (dev_context->brd_state == BRD_DSP_HIBERNATION ||
dev_context->brd_state == BRD_HIBERNATION) {
#ifdef CONFIG_TIDSPBRIDGE_DVFS
if (pdata->dsp_get_opp)
opplevel = (*pdata->dsp_get_opp) ();
if (opplevel == VDD1_OPP1) {
if (pdata->dsp_set_min_opp)
(*pdata->dsp_set_min_opp) (VDD1_OPP2);
}
#endif
/* Restart the peripheral clocks */
dsp_clock_enable_all(dev_context->dsp_per_clks);
dsp_wdt_enable(true);
/*
* 2:0 AUTO_IVA2_DPLL - Enabling IVA2 DPLL auto control
* in CM_AUTOIDLE_PLL_IVA2 register
*/
(*pdata->dsp_cm_write)(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL);
/*
* 7:4 IVA2_DPLL_FREQSEL - IVA2 internal frq set to
* 0.75 MHz - 1.0 MHz
* 2:0 EN_IVA2_DPLL - Enable IVA2 DPLL in lock mode
*/
(*pdata->dsp_cm_rmw_bits)(OMAP3430_IVA2_DPLL_FREQSEL_MASK |
OMAP3430_EN_IVA2_DPLL_MASK,
0x3 << OMAP3430_IVA2_DPLL_FREQSEL_SHIFT |
0x7 << OMAP3430_EN_IVA2_DPLL_SHIFT,
OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
/* Restore mailbox settings */
omap_mbox_restore_ctx(dev_context->mbox);
/* Access MMU SYS CONFIG register to generate a short wakeup */
temp = readl(resources->dmmu_base + 0x10);
dev_context->brd_state = BRD_RUNNING;
} else if (dev_context->brd_state == BRD_RETENTION) {
/* Restart the peripheral clocks */
dsp_clock_enable_all(dev_context->dsp_per_clks);
}
status = mbox_send_message(dev_context->mbox, (void *)((u32)mb_val));
if (status < 0) {
pr_err("mbox_send_message failed, status = %d\n", status);
status = -EPERM;
}
return 0;
}
int sm_interrupt_dsp(struct wmd_dev_context *dev_context, u16 mb_val)
{
int status = 0;
struct cfg_hostres *resources;
u32 temp;
struct dspbridge_platform_data *pdata =
omap_dspbridge_dev->dev.platform_data;
if (!dev_context || !dev_context->resources)
return -EFAULT;
if (!dev_context->mbox)
return status;
resources = dev_context->resources;
if (dev_context->dw_brd_state == BRD_DSP_HIBERNATION ||
dev_context->dw_brd_state == BRD_HIBERNATION) {
/* Restart the peripheral clocks */
dsp_peripheral_clocks_enable(dev_context, NULL);
#ifdef CONFIG_BRIDGE_WDT3
dsp_wdt_enable(true);
#endif
/*
* 2:0 AUTO_IVA2_DPLL - Enabling IVA2 DPLL auto control
* in CM_AUTOIDLE_PLL_IVA2 register
*/
(*pdata->dsp_cm_write)(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL);
/*
* 7:4 IVA2_DPLL_FREQSEL - IVA2 internal frq set to
* 0.75 MHz - 1.0 MHz
* 2:0 EN_IVA2_DPLL - Enable IVA2 DPLL in lock mode
*/
(*pdata->dsp_cm_rmw_bits)(OMAP3430_IVA2_DPLL_FREQSEL_MASK |
OMAP3430_EN_IVA2_DPLL_MASK,
0x3 << OMAP3430_IVA2_DPLL_FREQSEL_SHIFT |
0x7 << OMAP3430_EN_IVA2_DPLL_SHIFT,
OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
/* Restore mailbox settings */
omap_mbox_restore_ctx(dev_context->mbox);
/* Access MMU SYS CONFIG register to generate a short wakeup */
temp = *(reg_uword32 *) (resources->dw_dmmu_base + 0x10);
dev_context->dw_brd_state = BRD_RUNNING;
} else if (dev_context->dw_brd_state == BRD_RETENTION) {
/* Restart the peripheral clocks */
dsp_peripheral_clocks_enable(dev_context, NULL);
dev_context->dw_brd_state = BRD_RUNNING;
}
status = omap_mbox_msg_send(dev_context->mbox, mb_val);
if (status) {
pr_err("omap_mbox_msg_send Fail and status = %d\n", status);
status = -EPERM;
}
dev_dbg(bridge, "MBX: writing %x to Mailbox\n", mb_val);
return status;
}
int send_mbox_callback(void *arg)
{
struct WMD_DEV_CONTEXT *dev_ctxt = (struct WMD_DEV_CONTEXT *)arg;
u32 temp;
unsigned long flags;
DEFINE_SPINLOCK(irq_lock);
if (!dev_ctxt)
return -EFAULT;
if (dev_ctxt->dwBrdState == BRD_DSP_HIBERNATION ||
dev_ctxt->dwBrdState == BRD_HIBERNATION) {
/* Restart the peripheral clocks */
DSP_PeripheralClocks_Enable(dev_ctxt, NULL);
#ifdef CONFIG_BRIDGE_WDT3
dsp_wdt_enable(true);
#endif
spin_lock_irqsave(&irq_lock, flags);
/* Enabling Dpll in lock mode*/
temp = (u32) *((REG_UWORD32 *)
((u32) (dev_ctxt->cmbase) + 0x34));
temp = (temp & 0xFFFFFFFE) | 0x1;
*((REG_UWORD32 *) ((u32) (dev_ctxt->cmbase) + 0x34)) =
(u32) temp;
temp = (u32) *((REG_UWORD32 *)
((u32) (dev_ctxt->cmbase) + 0x4));
temp = (temp & 0xFFFFF08) | 0x37;
*((REG_UWORD32 *) ((u32) (dev_ctxt->cmbase) + 0x4)) =
(u32) temp;
/* Restore mailbox settings */
omap_mbox_restore_ctx(dev_ctxt->mbox);
/*
* Short wake up source is any read access to an MMU
* registers. Making a MMU flush or accessing any other MMU
* register before getting to this point will have the IVA in
* ON state or Retention if the DSP has moved to that state,
* having the Short Wakeup again is redundant and brings
* issues when accessing the MMU after the DSP has started
* its restore sequence. We will access only if the DSP
* is not in RET or ON.
*/
HW_PWRST_IVA2RegGet(dev_ctxt->prmbase, &temp);
if (!(temp & HW_PWR_STATE_RET) && !(temp & HW_PWR_STATE_ON))
/*
* Flush the TLBs, this will generate the
* shortwakeup. Also wait for the DSP to restore.
*/
tlb_flush_all(dev_ctxt->dwDSPMmuBase);
udelay(10);
spin_unlock_irqrestore(&irq_lock, flags);
dev_ctxt->dwBrdState = BRD_RUNNING;
} else if (dev_ctxt->dwBrdState == BRD_RETENTION) {
/* Restart the peripheral clocks */
DSP_PeripheralClocks_Enable(dev_ctxt, NULL);
dev_ctxt->dwBrdState = BRD_RUNNING;
}
return 0;
}
int sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val)
{
#ifdef CONFIG_TIDSPBRIDGE_DVFS
u32 opplevel = 0;
#endif
struct omap_dsp_platform_data *pdata =
omap_dspbridge_dev->dev.platform_data;
struct cfg_hostres *resources = dev_context->resources;
int status = 0;
u32 temp;
if (!dev_context->mbox)
return 0;
if (!resources)
return -EPERM;
if (dev_context->brd_state == BRD_DSP_HIBERNATION ||
dev_context->brd_state == BRD_HIBERNATION) {
#ifdef CONFIG_TIDSPBRIDGE_DVFS
if (pdata->dsp_get_opp)
opplevel = (*pdata->dsp_get_opp) ();
if (opplevel == VDD1_OPP1) {
if (pdata->dsp_set_min_opp)
(*pdata->dsp_set_min_opp) (VDD1_OPP2);
}
#endif
dsp_clock_enable_all(dev_context->dsp_per_clks);
dsp_wdt_enable(true);
(*pdata->dsp_cm_write)(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL);
(*pdata->dsp_cm_rmw_bits)(OMAP3430_IVA2_DPLL_FREQSEL_MASK |
OMAP3430_EN_IVA2_DPLL_MASK,
0x3 << OMAP3430_IVA2_DPLL_FREQSEL_SHIFT |
0x7 << OMAP3430_EN_IVA2_DPLL_SHIFT,
OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
omap_mbox_restore_ctx(dev_context->mbox);
temp = readl(resources->dmmu_base + 0x10);
dev_context->brd_state = BRD_RUNNING;
} else if (dev_context->brd_state == BRD_RETENTION) {
dsp_clock_enable_all(dev_context->dsp_per_clks);
}
status = omap_mbox_msg_send(dev_context->mbox, mb_val);
if (status) {
pr_err("omap_mbox_msg_send Fail and status = %d\n", status);
status = -EPERM;
}
return 0;
}
