static void test_can_receive(void)
{
const uint64_t tx_bd_num = _ETHOC_DESC_SIZE_/2;
uint64_t desc;
hwaddr desc_addr;
/* setup rx DMA buffer */
uint8_t rx_packet[2];
memset(rx_packet, 0, sizeof(rx_packet));
OpenEthState *s = OPEN_ETH_STATE(nc);
/* reset MAC and MII */
open_eth_reg_write(s, open_eth_reg(MODER), MODER_RST);
assert(tx_bd_num == open_eth_reg_read(s, open_eth_reg(TX_BD_NUM)));
assert(tx_bd_num == s->regs[TX_BD_NUM]);
/* setup MAC address */
open_eth_reg_write(s, open_eth_reg(MAC_ADDR0), 0x56789ABC);
open_eth_reg_write(s, open_eth_reg(MAC_ADDR1), 0x1234);
/* enable IRQ for incoming packets */
open_eth_reg_write(s, open_eth_reg(INT_MASK), INT_MASK_RXF_M);
/* calculate lowest rx buffer descriptor address */
desc_addr = tx_bd_num * 8;
/* setup rx buffer descriptor for DMA on rx_packet */
desc = (uint32_t) (uintptr_t) rx_packet;
desc <<= 32;
desc |= RXD_E | RXD_IRQ;
open_eth_desc_write(s, desc_addr, desc);
assert(s->desc[tx_bd_num].len_flags & (RXD_E | RXD_IRQ));
/* enable receiver and unmask BUSY interrupt */
open_eth_reg_write(s, open_eth_reg(MODER), MODER_RXEN);
assert(tx_bd_num == s->regs[TX_BD_NUM]);
assert(s->rx_desc == s->regs[TX_BD_NUM]);
assert(s->desc[tx_bd_num].len_flags & (RXD_E | RXD_IRQ));
assert(open_eth_can_receive(s));
}
static int nc_open_eth_can_receive(NetClientState *nc)
{
return open_eth_can_receive(OPEN_ETH_STATE(nc));
}
