error_t sam9263EthInit(NetInterface *interface)
{
error_t error;
volatile uint32_t status;
//Debug message
TRACE_INFO("Initializing SAM9263 Ethernet MAC...\r\n");
//Enable EMAC peripheral clock
AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_EMAC);
//GPIO configuration
sam9263EthInitGpio(interface);
//Configure MDC clock speed
AT91C_BASE_EMAC->EMAC_NCFGR = AT91C_EMAC_CLK_HCLK_64;
//Enable management port (MDC and MDIO)
AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
//PHY transceiver initialization
error = interface->phyDriver->init(interface);
//Failed to initialize PHY transceiver?
if(error) return error;
//Set the MAC address
AT91C_BASE_EMAC->EMAC_SA1L = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
AT91C_BASE_EMAC->EMAC_SA1H = interface->macAddr.w[2];
//Configure the receive filter
AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_UNI | AT91C_EMAC_MTI;
//Initialize hash table
AT91C_BASE_EMAC->EMAC_HRB = 0;
AT91C_BASE_EMAC->EMAC_HRT = 0;
//Initialize buffer descriptors
sam9263EthInitBufferDesc(interface);
//Clear transmit status register
AT91C_BASE_EMAC->EMAC_TSR = AT91C_EMAC_UND | AT91C_EMAC_COMP | AT91C_EMAC_BEX |
AT91C_EMAC_TGO | AT91C_EMAC_RLES | AT91C_EMAC_COL | AT91C_EMAC_UBR;
//Clear receive status register
AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA;
//First disable all EMAC interrupts
AT91C_BASE_EMAC->EMAC_IDR = 0xFFFFFFFF;
//Only the desired ones are enabled
AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_ROVR | AT91C_EMAC_TCOMP | AT91C_EMAC_TXERR |
AT91C_EMAC_RLEX | AT91C_EMAC_TUNDR | AT91C_EMAC_RXUBR | AT91C_EMAC_RCOMP;
//Read EMAC ISR register to clear any pending interrupt
status = AT91C_BASE_EMAC->EMAC_ISR;
//Configure interrupt controller
AT91C_BASE_AIC->AIC_SMR[AT91C_ID_EMAC] = AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | AT91C_AIC_PRIOR_LOWEST;
AT91C_BASE_AIC->AIC_SVR[AT91C_ID_EMAC] = (uint32_t) emacIrqWrapper;
//Clear EMAC interrupt flag
AT91C_BASE_AIC->AIC_ICCR = (1 << AT91C_ID_EMAC);
//Enable the EMAC to transmit and receive data
AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TE | AT91C_EMAC_RE;
//Force the TCP/IP stack to check the link state
osSetEvent(&interface->nicRxEvent);
//SAM9263 Ethernet MAC is now ready to send
osSetEvent(&interface->nicTxEvent);
//Successful initialization
return NO_ERROR;
}
error_t rx63nEthInit(NetInterface *interface)
{
error_t error;
//Debug message
TRACE_INFO("Initializing RX63N Ethernet MAC...\r\n");
//Disable protection
SYSTEM.PRCR.WORD = 0xA50B;
//Cancel EDMAC module stop state
MSTP(EDMAC) = 0;
//Enable protection
SYSTEM.PRCR.WORD = 0xA500;
//GPIO configuration
rx63nEthInitGpio(interface);
//Reset EMAC module
EDMAC.EDMR.BIT.SWR = 1;
sleep(10);
//PHY transceiver initialization
error = interface->phyDriver->init(interface);
//Failed to initialize PHY transceiver?
if(error) return error;
//Initialize DMA descriptor lists
rx63nEthInitDmaDesc(interface);
//Maximum frame length that can be accepted
ETHERC.RFLR.LONG = 1518;
//Set default inter packet gap (96-bit time)
ETHERC.IPGR.LONG = 0x14;
//Set the upper 32 bits of the MAC address
ETHERC.MAHR = (interface->macAddr.b[0] << 24) | (interface->macAddr.b[1] << 16) |
(interface->macAddr.b[2] << 8) | interface->macAddr.b[3];
//Set the lower 16 bits of the MAC address
ETHERC.MALR.BIT.MA = (interface->macAddr.b[4] << 8) | interface->macAddr.b[5];
//Set descriptor length (16 bytes)
EDMAC.EDMR.BIT.DL = 0;
//Select little endian mode
EDMAC.EDMR.BIT.DE = 1;
//Use store and forward mode
EDMAC.TFTR.BIT.TFT = 0;
//Set transmit FIFO size (2048 bytes)
EDMAC.FDR.BIT.TFD = 7;
//Set receive FIFO size (2048 bytes)
EDMAC.FDR.BIT.RFD = 7;
//Enable continuous reception of multiple frames
EDMAC.RMCR.BIT.RNR = 1;
//Accept transmit interrupt notifications
EDMAC.TRIMD.BIT.TIM = 0;
EDMAC.TRIMD.BIT.TIS = 1;
//Disable all EDMAC interrupts
EDMAC.EESIPR.LONG = 0;
//Enable only the desired EDMAC interrupts
EDMAC.EESIPR.BIT.TWBIP = 1;
EDMAC.EESIPR.BIT.FRIP = 1;
//Configure EDMAC interrupt priority
IPR(ETHER, EINT) = RX63N_ETH_IRQ_PRIORITY;
//Enable transmission and reception
ETHERC.ECMR.BIT.TE = 1;
ETHERC.ECMR.BIT.RE = 1;
//Instruct the DMA to poll the receive descriptor list
EDMAC.EDRRR.BIT.RR = 1;
//Force the TCP/IP stack to check the link state
osSetEvent(&interface->nicRxEvent);
//RX63N Ethernet MAC is now ready to send
osSetEvent(&interface->nicTxEvent);
//Successful initialization
return NO_ERROR;
}
error_t avr32EthInit(NetInterface *interface)
{
error_t error;
volatile uint32_t status;
//Debug message
TRACE_INFO("Initializing AVR32 Ethernet MAC...\r\n");
//Save underlying network interface
nicDriverInterface = interface;
//GPIO configuration
avr32EthInitGpio(interface);
//Configure MDC clock speed
AVR32_MACB.ncfgr = AVR32_MACB_NCFGR_CLK_DIV64;
//Enable management port (MDC and MDIO)
AVR32_MACB.ncr |= AVR32_MACB_NCR_MPE_MASK;
//PHY transceiver initialization
error = interface->phyDriver->init(interface);
//Failed to initialize PHY transceiver?
if(error) return error;
//Set the MAC address
AVR32_MACB.sa1b = interface->macAddr.b[0] |
(interface->macAddr.b[1] << 8) |
(interface->macAddr.b[2] << 16) |
(interface->macAddr.b[3] << 24);
AVR32_MACB.sa1t = interface->macAddr.b[4] |
(interface->macAddr.b[5] << 8);
//Configure the receive filter
AVR32_MACB.ncfgr |= AVR32_MACB_NCFGR_UNI_MASK | AVR32_MACB_NCFGR_MTI_MASK;
//Initialize hash table
AVR32_MACB.hrb = 0;
AVR32_MACB.hrt = 0;
//Initialize buffer descriptors
avr32EthInitBufferDesc(interface);
//Clear transmit status register
AVR32_MACB.tsr = AVR32_MACB_TSR_UND_MASK | AVR32_MACB_TSR_COMP_MASK | AVR32_MACB_TSR_BEX_MASK |
AVR32_MACB_TSR_TGO_MASK | AVR32_MACB_TSR_RLE_MASK | AVR32_MACB_TSR_COL_MASK | AVR32_MACB_TSR_UBR_MASK;
//Clear receive status register
AVR32_MACB.rsr = AVR32_MACB_RSR_OVR_MASK | AVR32_MACB_RSR_REC_MASK | AVR32_MACB_RSR_BNA_MASK;
//First disable all EMAC interrupts
AVR32_MACB.idr = 0xFFFFFFFF;
//Only the desired ones are enabled
AVR32_MACB.ier = AVR32_MACB_IER_ROVR_MASK | AVR32_MACB_IER_TCOMP_MASK | AVR32_MACB_IER_TXERR_MASK |
AVR32_MACB_IER_RLE_MASK | AVR32_MACB_IER_TUND_MASK | AVR32_MACB_IER_RXUBR_MASK | AVR32_MACB_IER_RCOMP_MASK;
//Read EMAC ISR register to clear any pending interrupt
status = AVR32_MACB.isr;
//Register interrupt handler
INTC_register_interrupt(avr32EthIrqWrapper, AVR32_MACB_IRQ, AVR32_ETH_IRQ_PRIORITY);
//Enable the EMAC to transmit and receive data
AVR32_MACB.ncr |= AVR32_MACB_NCR_TE_MASK | AVR32_MACB_NCR_RE_MASK;
//Force the TCP/IP stack to check the link state
osSetEvent(&interface->nicRxEvent);
//AVR32 Ethernet MAC is now ready to send
osSetEvent(&interface->nicTxEvent);
//Successful initialization
return NO_ERROR;
}
error_t rza1EthInit(NetInterface *interface)
{
error_t error;
//Debug message
TRACE_INFO("Initializing RZ/A1 Ethernet MAC...\r\n");
//Enable Ethernet peripheral clock
CPG.STBCR7 &= ~CPG_STBCR7_MSTP74;
//GPIO configuration
rza1EthInitGpio(interface);
//Perform software reset
ETHER.ARSTR = ETHER_ARSTR_ARST;
//Wait for the reset to complete
sleep(10);
//Start EDMAC transmitting and receiving units
ETHER.EDSR0 = ETHER_EDSR0_ENT | ETHER_EDSR0_ENR;
//To execute a software reset with this register, 1 must be
//written to both the SWRT and SWRR bits simultaneously
ETHER.EDMR0 = ETHER_EDMR0_SWRT | ETHER_EDMR0_SWRR;
//Wait for the reset to complete
while(ETHER.EDMR0 & (ETHER_EDMR0_SWRT | ETHER_EDMR0_SWRR));
//PHY transceiver initialization
error = interface->phyDriver->init(interface);
//Failed to initialize PHY transceiver?
if(error) return error;
//Initialize DMA descriptor lists
rza1EthInitDmaDesc(interface);
//Select little endian mode and set descriptor length (16 bytes)
ETHER.EDMR0 = ETHER_EDMR0_DE | ETHER_EDMR0_DL_16;
//Error masks
ETHER.TRSCER0 = 0;
//Use store and forward mode
ETHER.TFTR0 = 0;
//Set transmit FIFO size and receive FIFO size (2048 bytes)
ETHER.FDR0 = ETHER_FDR0_TFD_2048 | ETHER_FDR0_RFD_2048;
//Enable continuous reception of multiple frames
ETHER.RMCR0 = ETHER_RMCR0_RNC;
//No padding insertion into receive data
ETHER.RPADIR0 = 0;
//Receive FIFO threshold (8 frames or 2048-64 bytes)
ETHER.FCFTR0 = ETHER_FCFTR0_RFF_8 | ETHER_FCFTR0_RFD_2048;
//Intelligent checksum operation mode
ETHER.CSMR = 0;
//Enable multicast address filtering
ETHER.ECMR0 |= ETH_ECMR0_MCT;
//Set the upper 32 bits of the MAC address
ETHER.MAHR0 = (interface->macAddr.b[0] << 24) | (interface->macAddr.b[1] << 16) |
(interface->macAddr.b[2] << 8) | interface->macAddr.b[3];
//Set the lower 16 bits of the MAC address
ETHER.MALR0 = (interface->macAddr.b[4] << 8) | interface->macAddr.b[5];
//Maximum frame length that can be accepted
ETHER.RFLR0 = 1518;
//Automatic pause frame
ETHER.APR0 = 0;
//Manual pause frame
ETHER.MPR0 = 0;
//Automatic pause frame retransmit count
ETHER.TPAUSER0 = 0;
//Disable all EMAC interrupts
ETHER.ECSIPR0 = 0;
//Enable the desired EDMAC interrupts
ETHER.EESIPR0 = ETHER_EESIPR0_TWBIP | ETHER_EESIPR0_FRIP;
//Register interrupt handler
R_INTC_Regist_Int_Func(INTC_ID_ETHERI, rza1EthIrqHandler);
//Configure interrupt priority
R_INTC_Set_Priority(INTC_ID_ETHERI, RZA1_ETH_IRQ_PRIORITY);
//Enable EDMAC transmission and reception
ETHER.ECMR0 |= ETH_ECMR0_RE | ETH_ECMR0_TE;
//Instruct the DMA to poll the receive descriptor list
ETHER.EDRRR0 = ETHER_EDRRR0_RR;
//Force the TCP/IP stack to check the link state
osSetEvent(&interface->nicRxEvent);
//RZ/A1 Ethernet MAC is now ready to send
osSetEvent(&interface->nicTxEvent);
//Successful initialization
return NO_ERROR;
}
error_t wilc1000Init(NetInterface *interface)
{
int8_t status;
tstrWifiInitParam param;
//STA or AP mode?
if(interface->nicDriver == &wilc1000StaDriver)
{
//Debug message
TRACE_INFO("Initializing WILC1000 (STA mode)...\r\n");
}
else
{
//Debug message
TRACE_INFO("Initializing WILC1000 (AP mode)...\r\n");
}
//Start of exception handling block
do
{
//Initialization sequence is performed once at startup
if(wilc1000StaInterface == NULL && wilc1000ApInterface == NULL)
{
//Low-level initialization
status = nm_bsp_init();
//Check status code
if(status != M2M_SUCCESS)
break;
//Set default parameters
memset(¶m, 0, sizeof(param));
//Register callback functions
param.pfAppWifiCb = wilc1000AppWifiEvent;
param.pfAppMonCb = NULL;
param.strEthInitParam.pfAppWifiCb = NULL;
param.strEthInitParam.pfAppEthCb = wilc1000AppEthEvent;
//Set receive buffer
param.strEthInitParam.au8ethRcvBuf = rxBuffer;
param.strEthInitParam.u16ethRcvBufSize = WILC1000_RX_BUFFER_SIZE - ETH_CRC_SIZE;
//Initialize WILC1000 controller
status = m2m_wifi_init(¶m);
//Check status code
if(status != M2M_SUCCESS)
break;
//Optionally set the station MAC address
if(macCompAddr(&interface->macAddr, &MAC_UNSPECIFIED_ADDR))
{
//Use the factory preprogrammed station address
status = m2m_wifi_get_mac_address(interface->macAddr.b);
//Check status code
if(status != M2M_SUCCESS)
break;
//Generate the 64-bit interface identifier
macAddrToEui64(&interface->macAddr, &interface->eui64);
}
else
{
//Override the factory preprogrammed address
status = m2m_wifi_set_mac_address(interface->macAddr.b);
//Check status code
if(status != M2M_SUCCESS)
break;
}
}
else
{
//Initialization was already done
status = M2M_SUCCESS;
}
//STA or AP mode?
if(interface->nicDriver == &wilc1000StaDriver)
{
//Save underlying network interface (STA mode)
wilc1000StaInterface = interface;
if(wilc1000ApInterface != NULL)
{
wilc1000StaInterface->macAddr = wilc1000ApInterface->macAddr;
wilc1000StaInterface->eui64 = wilc1000ApInterface->eui64;
}
}
else
{
//Save underlying network interface (AP mode)
wilc1000ApInterface = interface;
if(wilc1000StaInterface != NULL)
{
wilc1000ApInterface->macAddr = wilc1000StaInterface->macAddr;
wilc1000ApInterface->eui64 = wilc1000StaInterface->eui64;
}
}
//End of exception handling block
} while(0);
//WILC1000 is now ready to send
osSetEvent(&interface->nicTxEvent);
//Return status code
if(status == M2M_SUCCESS)
return NO_ERROR;
else
return ERROR_FAILURE;
}
void httpListenerTask(void *param)
{
uint_t i;
uint_t counter;
uint16_t clientPort;
IpAddr clientIpAddr;
HttpServerContext *context;
HttpConnection* connection;
Socket *socket;
//Retrieve the HTTP server context
context = (HttpServerContext *) param;
//Process incoming connections to the server
for(counter = 1; ; counter++)
{
//Debug message
TRACE_INFO("Ready to accept a new connection...\r\n");
//Limit the number of simultaneous connections to the HTTP server
osWaitForSemaphore(&context->semaphore, INFINITE_DELAY);
//Loop through available client connections
for(i = 0; i < context->settings.maxConnections; i++)
{
//Point to the current connection
connection = &context->connections[i];
//Ready to service the client request?
if(!connection->running)
{
//Accept an incoming connection
socket = socketAccept(context->socket, &clientIpAddr, &clientPort);
//Make sure the socket handle is valid
if(socket != NULL)
{
//Debug message
TRACE_INFO("Connection #%u established with client %s port %" PRIu16 "...\r\n",
counter, ipAddrToString(&clientIpAddr, NULL), clientPort);
//Reference to the HTTP server settings
connection->settings = &context->settings;
//Reference to the HTTP server context
connection->serverContext = context;
//Reference to the new socket
connection->socket = socket;
//Set timeout for blocking functions
socketSetTimeout(connection->socket, HTTP_SERVER_TIMEOUT);
//The client connection task is now running...
connection->running = TRUE;
//Service the current connection request
osSetEvent(&connection->startEvent);
//We are done
break;
}
}
}
}
}
error_t sam4eEthInit(NetInterface *interface)
{
error_t error;
volatile uint32_t status;
//Debug message
TRACE_INFO("Initializing SAM4E Ethernet MAC...\r\n");
//Enable GMAC peripheral clock
PMC->PMC_PCER1 = (1 << (ID_GMAC - 32));
//GPIO configuration
sam4eEthInitGpio(interface);
//Configure MDC clock speed
GMAC->GMAC_NCFGR = GMAC_NCFGR_CLK_MCK_96;
//Enable management port (MDC and MDIO)
GMAC->GMAC_NCR |= GMAC_NCR_MPE;
//PHY transceiver initialization
error = interface->phyDriver->init(interface);
//Failed to initialize PHY transceiver?
if(error) return error;
//Set the MAC address
GMAC->GMAC_SA[0].GMAC_SAB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
GMAC->GMAC_SA[0].GMAC_SAT = interface->macAddr.w[2];
//Configure the receive filter
GMAC->GMAC_NCFGR |= GMAC_NCFGR_UNIHEN | GMAC_NCFGR_MTIHEN;
//Initialize hash table
GMAC->GMAC_HRB = 0;
GMAC->GMAC_HRT = 0;
//Initialize buffer descriptors
sam4eEthInitBufferDesc(interface);
//Clear transmit status register
GMAC->GMAC_TSR = GMAC_TSR_HRESP | GMAC_TSR_UND | GMAC_TSR_TXCOMP | GMAC_TSR_TFC |
GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL | GMAC_TSR_UBR;
//Clear receive status register
GMAC->GMAC_RSR = GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA;
//First disable all GMAC interrupts
GMAC->GMAC_IDR = 0xFFFFFFFF;
//Only the desired ones are enabled
GMAC->GMAC_IER = GMAC_IER_HRESP | GMAC_IER_ROVR | GMAC_IER_TCOMP | GMAC_IER_TFC |
GMAC_IER_RLEX | GMAC_IER_TUR | GMAC_IER_RXUBR | GMAC_IER_RCOMP;
//Read GMAC ISR register to clear any pending interrupt
status = GMAC->GMAC_ISR;
//Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
NVIC_SetPriorityGrouping(SAM4E_ETH_IRQ_PRIORITY_GROUPING);
//Configure GMAC interrupt priority
NVIC_SetPriority(GMAC_IRQn, NVIC_EncodePriority(SAM4E_ETH_IRQ_PRIORITY_GROUPING,
SAM4E_ETH_IRQ_GROUP_PRIORITY, SAM4E_ETH_IRQ_SUB_PRIORITY));
//Enable the GMAC to transmit and receive data
GMAC->GMAC_NCR |= GMAC_NCR_TXEN | GMAC_NCR_RXEN;
//Force the TCP/IP stack to check the link state
osSetEvent(&interface->nicRxEvent);
//SAM4E Ethernet MAC is now ready to send
osSetEvent(&interface->nicTxEvent);
//Successful initialization
return NO_ERROR;
}
error_t m2sxxxEthInit(NetInterface *interface)
{
error_t error;
//Debug message
TRACE_INFO("Initializing M2Sxxx Ethernet MAC...\r\n");
//Disable EDAC feature
SYSREG->EDAC_CR &= ~(EDAC_CR_MAC_EDAC_RX_EN | EDAC_CR_MAC_EDAC_TX_EN);
//Reset the MAC module
MAC->CFG1 = CFG1_SOFT_RESET | CFG1_RESET_RX_MAC_CTRL |
CFG1_RESET_TX_MAC_CTRL | CFG1_RESET_RX_FUNCTION | CFG1_RESET_TX_FUNCTION;
//Reset the interface module
MAC->INTERFACE_CTRL = INTERFACE_CTRL_RESET;
//Reset FIFOs
MAC->FIFO_CFG0 = FIFO_CFG0_HSTRSTFT | FIFO_CFG0_HSTRSTST |
FIFO_CFG0_HSTRSTFR | FIFO_CFG0_HSTRSTSR | FIFO_CFG0_HSTRSTWT;
//Take the MAC module out of reset
MAC->CFG1 = 0;
//Take the interface module out of reset
MAC->INTERFACE_CTRL = 0;
//Take the FIFOs out of reset
MAC->FIFO_CFG0 = 0;
//Select interface mode (MII, RMII, GMII or TBI)
m2sxxxEthInitGpio(interface);
//Select the proper divider for the MDC clock
MAC->MII_CONFIG = MII_CONFIG_CLKSEL_DIV28;
//PHY transceiver initialization
error = interface->phyDriver->init(interface);
//Failed to initialize PHY transceiver?
if(error) return error;
//Set the upper 16 bits of the MAC address
MAC->STATION_ADDRESS2 = (interface->macAddr.b[0] << 16) |
(interface->macAddr.b[1] << 24);
//Set the lower 32 bits of the MAC address
MAC->STATION_ADDRESS1 = interface->macAddr.b[2] |
(interface->macAddr.b[3] << 8) |
(interface->macAddr.b[4] << 16) |
(interface->macAddr.b[5] << 24);
//Maximum frame length to be accepted
MAC->MAX_FRAME_LENGTH = 1518;
//Disable flow control
MAC->CFG1 = 0;
//All short frames will be zero-padded to 60 bytes and a valid CRC is then appended
MAC->CFG2 = CFG2_PREAMBLE_7 | CFG2_INTERFACE_MODE_NIBBLE |
CFG2_LENGTH_FIELD_CHECK | CFG2_PAD_CRC_EN | CFG2_CRC_EN;
//Enable TX and RX FIFOs
MAC->FIFO_CFG0 = FIFO_CFG0_FTFENREQ | FIFO_CFG0_STFENREQ |
FIFO_CFG0_FRFENREQ | FIFO_CFG0_SRFENREQ | FIFO_CFG0_WTMENREQ;
//Use default FIFO configuration
MAC->FIFO_CFG1 = FIFO_CFG1_DEFAULT_VALUE;
MAC->FIFO_CFG2 = FIFO_CFG2_DEFAULT_VALUE;
MAC->FIFO_CFG3 = FIFO_CFG3_DEFAULT_VALUE;
//Drop frames less than 64 bytes
MAC->FIFO_CFG5 = FIFO_CFG5_HSTDRPLT64 | FIFO_CFG5_HSTFLTRFRMDC;
//Specify the statistics vectors that will be checked
MAC->FIFO_CFG5 &= ~(FIFO_CFG5_TRUNCATED | FIFO_CFG5_RECEPTION_OK |
FIFO_CFG5_INVALID_CRC | FIFO_CFG5_RECEIVE_ERROR);
//Configure frame filtering
MAC->FIFO_CFG4 = FIFO_CFG4_TRUNCATED |
FIFO_CFG4_INVALID_CRC | FIFO_CFG4_RECEIVE_ERROR;
//Initialize DMA descriptor lists
m2sxxxEthInitDmaDesc(interface);
//Configure Ethernet interrupts as desired
MAC->DMA_IRQ_MASK = DMA_IRQ_MASK_RX_PKT_RECEIVED | DMA_IRQ_MASK_TX_PKT_SENT;
//Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
NVIC_SetPriorityGrouping(M2SXXX_ETH_IRQ_PRIORITY_GROUPING);
//Configure Ethernet interrupt priority
NVIC_SetPriority(EthernetMAC_IRQn, NVIC_EncodePriority(M2SXXX_ETH_IRQ_PRIORITY_GROUPING,
M2SXXX_ETH_IRQ_GROUP_PRIORITY, M2SXXX_ETH_IRQ_SUB_PRIORITY));
//Enable transmission and reception
MAC->CFG1 |= CFG1_TX_EN | CFG1_RX_EN;
//Enable the DMA transfer of received packets
MAC->DMA_RX_CTRL = DMA_RX_CTRL_RX_EN;
//Force the TCP/IP stack to check the link state
osSetEvent(&interface->nicRxEvent);
//M2Sxxx Ethernet MAC is now ready to send
osSetEvent(&interface->nicTxEvent);
//Successful initialization
return NO_ERROR;
}
error_t stm32f4x7EthInit(NetInterface *interface)
{
error_t error;
//Debug message
TRACE_INFO("Initializing STM32F4x7 Ethernet MAC...\r\n");
//Save underlying network interface
nicDriverInterface = interface;
//GPIO configuration
stm32f4x7EthInitGpio(interface);
#if defined(USE_HAL_DRIVER)
//Enable Ethernet MAC clock
__HAL_RCC_ETHMAC_CLK_ENABLE();
__HAL_RCC_ETHMACTX_CLK_ENABLE();
__HAL_RCC_ETHMACRX_CLK_ENABLE();
//Reset Ethernet MAC peripheral
__HAL_RCC_ETHMAC_FORCE_RESET();
__HAL_RCC_ETHMAC_RELEASE_RESET();
#else
//Enable Ethernet MAC clock
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC |
RCC_AHB1Periph_ETH_MAC_Tx | RCC_AHB1Periph_ETH_MAC_Rx, ENABLE);
//Reset Ethernet MAC peripheral
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, ENABLE);
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, DISABLE);
#endif
//Perform a software reset
ETH->DMABMR |= ETH_DMABMR_SR;
//Wait for the reset to complete
while(ETH->DMABMR & ETH_DMABMR_SR);
//Adjust MDC clock range depending on HCLK frequency
ETH->MACMIIAR = ETH_MACMIIAR_CR_Div102;
//PHY transceiver initialization
error = interface->phyDriver->init(interface);
//Failed to initialize PHY transceiver?
if(error) return error;
//Use default MAC configuration
ETH->MACCR = ETH_MACCR_ROD;
//Set the MAC address
ETH->MACA0LR = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
ETH->MACA0HR = interface->macAddr.w[2];
//Initialize hash table
ETH->MACHTLR = 0;
ETH->MACHTHR = 0;
//Configure the receive filter
ETH->MACFFR = ETH_MACFFR_HPF | ETH_MACFFR_HM;
//Disable flow control
ETH->MACFCR = 0;
//Enable store and forward mode
ETH->DMAOMR = ETH_DMAOMR_RSF | ETH_DMAOMR_TSF;
//Configure DMA bus mode
ETH->DMABMR = ETH_DMABMR_AAB | ETH_DMABMR_USP | ETH_DMABMR_RDP_1Beat |
ETH_DMABMR_RTPR_1_1 | ETH_DMABMR_PBL_1Beat | ETH_DMABMR_EDE;
//Initialize DMA descriptor lists
stm32f4x7EthInitDmaDesc(interface);
//Prevent interrupts from being generated when the transmit statistic
//counters reach half their maximum value
ETH->MMCTIMR = ETH_MMCTIMR_TGFM | ETH_MMCTIMR_TGFMSCM | ETH_MMCTIMR_TGFSCM;
//Prevent interrupts from being generated when the receive statistic
//counters reach half their maximum value
ETH->MMCRIMR = ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFAEM | ETH_MMCRIMR_RFCEM;
//Disable MAC interrupts
ETH->MACIMR = ETH_MACIMR_TSTIM | ETH_MACIMR_PMTIM;
//Enable the desired DMA interrupts
ETH->DMAIER = ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE;
//Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
NVIC_SetPriorityGrouping(STM32F4X7_ETH_IRQ_PRIORITY_GROUPING);
//Configure Ethernet interrupt priority
NVIC_SetPriority(ETH_IRQn, NVIC_EncodePriority(STM32F4X7_ETH_IRQ_PRIORITY_GROUPING,
STM32F4X7_ETH_IRQ_GROUP_PRIORITY, STM32F4X7_ETH_IRQ_SUB_PRIORITY));
//Enable MAC transmission and reception
ETH->MACCR |= ETH_MACCR_TE | ETH_MACCR_RE;
//Enable DMA transmission and reception
ETH->DMAOMR |= ETH_DMAOMR_ST | ETH_DMAOMR_SR;
//Accept any packets from the upper layer
osSetEvent(&interface->nicTxEvent);
//Successful initialization
return NO_ERROR;
}
error_t xmc4700EthInit(NetInterface *interface)
{
error_t error;
//Debug message
TRACE_INFO("Initializing XMC4700 Ethernet MAC...\r\n");
//Save underlying network interface
nicDriverInterface = interface;
//Disable parity error trap
SCU_PARITY->PETE = 0;
//Disable unaligned access trap
PPB->CCR &= ~PPB_CCR_UNALIGN_TRP_Msk;
//Enable ETH0 peripheral clock
SCU_CLK->CLKSET = SCU_CLK_CLKSET_ETH0CEN_Msk;
//GPIO configuration
xmc4700EthInitGpio(interface);
//Reset ETH0 peripheral
SCU_RESET->PRSET2 = SCU_RESET_PRSET2_ETH0RS_Msk;
SCU_RESET->PRCLR2 = SCU_RESET_PRCLR2_ETH0RS_Msk;
//Reset DMA controller
ETH0->BUS_MODE |= ETH_BUS_MODE_SWR_Msk;
//Wait for the reset to complete
while(ETH0->BUS_MODE & ETH_BUS_MODE_SWR_Msk);
//Adjust MDC clock range depending on ETH clock frequency
ETH0->GMII_ADDRESS = ETH_GMII_ADDRESS_CR_DIV62;
//PHY transceiver initialization
error = interface->phyDriver->init(interface);
//Failed to initialize PHY transceiver?
if(error) return error;
//Use default MAC configuration
ETH0->MAC_CONFIGURATION = ETH_MAC_CONFIGURATION_RESERVED15_Msk |
ETH_MAC_CONFIGURATION_DO_Msk;
//Set the MAC address
ETH0->MAC_ADDRESS0_LOW = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
ETH0->MAC_ADDRESS0_HIGH = interface->macAddr.w[2];
//Initialize hash table
ETH0->HASH_TABLE_LOW = 0;
ETH0->HASH_TABLE_HIGH = 0;
//Configure the receive filter
ETH0->MAC_FRAME_FILTER = ETH_MAC_FRAME_FILTER_HPF_Msk | ETH_MAC_FRAME_FILTER_HMC_Msk;
//Disable flow control
ETH0->FLOW_CONTROL = 0;
//Enable store and forward mode
ETH0->OPERATION_MODE = ETH_OPERATION_MODE_RSF_Msk | ETH_OPERATION_MODE_TSF_Msk;
//Configure DMA bus mode
ETH0->BUS_MODE = ETH_BUS_MODE_AAL_Msk | ETH_BUS_MODE_USP_Msk |
ETH_BUS_MODE_RPBL_1 | ETH_BUS_MODE_PR_1_1 | ETH_BUS_MODE_PBL_1;
//Initialize DMA descriptor lists
xmc4700EthInitDmaDesc(interface);
//Prevent interrupts from being generated when statistic counters reach
//half their maximum value
ETH0->MMC_TRANSMIT_INTERRUPT_MASK = 0xFFFFFFFF;
ETH0->MMC_RECEIVE_INTERRUPT_MASK = 0xFFFFFFFF;
ETH0->MMC_IPC_RECEIVE_INTERRUPT_MASK = 0xFFFFFFFF;
//Disable MAC interrupts
ETH0->INTERRUPT_MASK = ETH_INTERRUPT_MASK_TSIM_Msk | ETH_INTERRUPT_MASK_PMTIM_Msk;
//Enable the desired DMA interrupts
ETH0->INTERRUPT_ENABLE = ETH_INTERRUPT_ENABLE_NIE_Msk |
ETH_INTERRUPT_ENABLE_RIE_Msk | ETH_INTERRUPT_ENABLE_TIE_Msk;
//Set priority grouping (6 bits for pre-emption priority, no bits for subpriority)
NVIC_SetPriorityGrouping(XMC4700_ETH_IRQ_PRIORITY_GROUPING);
//Configure Ethernet interrupt priority
NVIC_SetPriority(ETH0_0_IRQn, NVIC_EncodePriority(XMC4700_ETH_IRQ_PRIORITY_GROUPING,
XMC4700_ETH_IRQ_GROUP_PRIORITY, XMC4700_ETH_IRQ_SUB_PRIORITY));
//Enable MAC transmission and reception
ETH0->MAC_CONFIGURATION |= ETH_MAC_CONFIGURATION_TE_Msk | ETH_MAC_CONFIGURATION_RE_Msk;
//Enable DMA transmission and reception
ETH0->OPERATION_MODE |= ETH_OPERATION_MODE_ST_Msk | ETH_OPERATION_MODE_SR_Msk;
//Accept any packets from the upper layer
osSetEvent(&interface->nicTxEvent);
//Successful initialization
return NO_ERROR;
}
error_t dm9000Init(NetInterface *interface)
{
uint_t i;
uint16_t vendorId;
uint16_t productId;
uint8_t chipRevision;
Dm9000Context *context;
//Debug message
TRACE_INFO("Initializing DM9000 Ethernet controller...\r\n");
//Initialize external interrupt line
interface->extIntDriver->init();
//Point to the driver context
context = (Dm9000Context *) interface->nicContext;
//Initialize driver specific variables
context->queuedPackets = 0;
//Retrieve vendorID, product ID and chip revision
vendorId = (dm9000ReadReg(DM9000_REG_VIDH) << 8) | dm9000ReadReg(DM9000_REG_VIDL);
productId = (dm9000ReadReg(DM9000_REG_PIDH) << 8) | dm9000ReadReg(DM9000_REG_PIDL);
chipRevision = dm9000ReadReg(DM9000_REG_CHIPR);
//Check vendor ID and product ID
if(vendorId != DM9000_VID || productId != DM9000_PID)
return ERROR_WRONG_IDENTIFIER;
//Check chip revision
if(chipRevision != DM9000A_CHIP_REV && chipRevision != DM9000B_CHIP_REV)
return ERROR_WRONG_IDENTIFIER;
//Power up the internal PHY by clearing PHYPD
dm9000WriteReg(DM9000_REG_GPR, 0x00);
//Wait for the PHY to be ready
sleep(10);
//Software reset
dm9000WriteReg(DM9000_REG_NCR, NCR_RST);
//Wait for the reset to complete
while(dm9000ReadReg(DM9000_REG_NCR) & NCR_RST);
//PHY software reset
dm9000WritePhyReg(DM9000_PHY_REG_BMCR, BMCR_RST);
//Wait for the PHY reset to complete
while(dm9000ReadPhyReg(DM9000_PHY_REG_BMCR) & BMCR_RST);
//Debug message
TRACE_INFO(" VID = 0x%04" PRIX16 "\r\n", vendorId);
TRACE_INFO(" PID = 0x%04" PRIX16 "\r\n", productId);
TRACE_INFO(" CHIPR = 0x%02" PRIX8 "\r\n", chipRevision);
TRACE_INFO(" PHYIDR1 = 0x%04" PRIX16 "\r\n", dm9000ReadPhyReg(DM9000_PHY_REG_PHYIDR1));
TRACE_INFO(" PHYIDR2 = 0x%04" PRIX16 "\r\n", dm9000ReadPhyReg(DM9000_PHY_REG_PHYIDR2));
//Enable loopback mode?
#if (DM9000_LOOPBACK_MODE == ENABLED)
dm9000WriteReg(DM9000_REG_NCR, DM9000_LBK_PHY);
dm9000WritePhyReg(DM9000_PHY_REG_BMCR, BMCR_LOOPBACK | BMCR_SPEED_SEL | BMCR_AN_EN | BMCR_DUPLEX_MODE);
#endif
//Set host MAC address
for(i = 0; i < 6; i++)
dm9000WriteReg(DM9000_REG_PAR0 + i, interface->macAddr.b[i]);
//Initialize hash table
for(i = 0; i < 8; i++)
dm9000WriteReg(DM9000_REG_MAR0 + i, 0x00);
//Always accept broadcast packets
dm9000WriteReg(DM9000_REG_MAR7, 0x80);
//Enable the Pointer Auto Return function
dm9000WriteReg(DM9000_REG_IMR, IMR_PAR);
//Clear NSR status bits
dm9000WriteReg(DM9000_REG_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
//Clear interrupt flags
dm9000WriteReg(DM9000_REG_ISR, ISR_LNKCHG | ISR_UDRUN | ISR_ROO | ISR_ROS | ISR_PT | ISR_PR);
//Enable interrupts
dm9000WriteReg(DM9000_REG_IMR, IMR_PAR | IMR_LNKCHGI | IMR_PTI | IMR_PRI);
//Enable the receiver by setting RXEN
dm9000WriteReg(DM9000_REG_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
//DM9000 transmitter is now ready to send
osSetEvent(&interface->nicTxEvent);
//Successful initialization
return NO_ERROR;
}
error_t tm4c129EthInit(NetInterface *interface)
{
//Debug message
TRACE_INFO("Initializing Tiva TM4C129 Ethernet controller...\r\n");
//Save underlying network interface
nicDriverInterface = interface;
//Enable Ethernet controller clock
SysCtlPeripheralEnable(SYSCTL_PERIPH_EMAC0);
//Reset Ethernet controller
SysCtlPeripheralReset(SYSCTL_PERIPH_EMAC0);
//Wait for the reset to complete
while(!SysCtlPeripheralReady(SYSCTL_PERIPH_EMAC0));
//Enable internal PHY clock
SysCtlPeripheralEnable(SYSCTL_PERIPH_EPHY0);
//Reset internal PHY
SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0);
//Wait for the reset to complete
while(!SysCtlPeripheralReady(SYSCTL_PERIPH_EPHY0));
//GPIO configuration
tm4c129EthInitGpio(interface);
//Perform a software reset
EMAC0_DMABUSMOD_R |= EMAC_DMABUSMOD_SWR;
//Wait for the reset to complete
while(EMAC0_DMABUSMOD_R & EMAC_DMABUSMOD_SWR);
//Adjust MDC clock range depending on SYSCLK frequency
EMAC0_MIIADDR_R = EMAC_MIIADDR_CR_100_150;
//Reset PHY transceiver
tm4c129EthWritePhyReg(EPHY_BMCR, EPHY_BMCR_MIIRESET);
//Wait for the reset to complete
while(tm4c129EthReadPhyReg(EPHY_BMCR) & EPHY_BMCR_MIIRESET);
//Dump PHY registers for debugging purpose
tm4c129EthDumpPhyReg();
//Configure LED0, LED1 and LED2
tm4c129EthWritePhyReg(EPHY_LEDCFG, EPHY_LEDCFG_LED0_TX |
EPHY_LEDCFG_LED1_RX | EPHY_LEDCFG_LED2_LINK);
//Configure PHY interrupts as desired
tm4c129EthWritePhyReg(EPHY_MISR1, EPHY_MISR1_LINKSTATEN);
//Enable PHY interrupts
tm4c129EthWritePhyReg(EPHY_SCR, EPHY_SCR_INTEN);
//Use default MAC configuration
EMAC0_CFG_R = EMAC_CFG_DRO;
//Set the MAC address
EMAC0_ADDR0L_R = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
EMAC0_ADDR0H_R = interface->macAddr.w[2];
//Initialize hash table
EMAC0_HASHTBLL_R = 0;
EMAC0_HASHTBLH_R = 0;
//Configure the receive filter
EMAC0_FRAMEFLTR_R = EMAC_FRAMEFLTR_HPF | EMAC_FRAMEFLTR_HMC;
//Disable flow control
EMAC0_FLOWCTL_R = 0;
//Enable store and forward mode
EMAC0_DMAOPMODE_R = EMAC_DMAOPMODE_RSF | EMAC_DMAOPMODE_TSF;
//Configure DMA bus mode
EMAC0_DMABUSMOD_R = EMAC_DMABUSMOD_AAL | EMAC_DMABUSMOD_USP | EMAC_DMABUSMOD_RPBL_1 |
EMAC_DMABUSMOD_PR_1_1 | EMAC_DMABUSMOD_PBL_1 | EMAC_DMABUSMOD_ATDS;
//Initialize DMA descriptor lists
tm4c129EthInitDmaDesc(interface);
//Prevent interrupts from being generated when the transmit statistic
//counters reach half their maximum value
EMAC0_MMCTXIM_R = EMAC_MMCTXIM_OCTCNT | EMAC_MMCTXIM_MCOLLGF |
EMAC_MMCTXIM_SCOLLGF | EMAC_MMCTXIM_GBF;
//Prevent interrupts from being generated when the receive statistic
//counters reach half their maximum value
EMAC0_MMCRXIM_R = EMAC_MMCRXIM_UCGF | EMAC_MMCRXIM_ALGNERR |
EMAC_MMCRXIM_CRCERR | EMAC_MMCRXIM_GBF;
//Disable MAC interrupts
EMAC0_IM_R = EMAC_IM_TSI | EMAC_IM_PMT;
//Enable the desired DMA interrupts
EMAC0_DMAIM_R = EMAC_DMAIM_NIE | EMAC_DMAIM_RIE | EMAC_DMAIM_TIE;
//Enable PHY interrupts
EMAC0_EPHYIM_R = EMAC_EPHYIM_INT;
//Set priority grouping (3 bits for pre-emption priority, no bits for subpriority)
IntPriorityGroupingSet(TM4C129_ETH_IRQ_PRIORITY_GROUPING);
//Configure Ethernet interrupt priority
IntPrioritySet(INT_EMAC0, TM4C129_ETH_IRQ_PRIORITY);
//Enable MAC transmission and reception
EMAC0_CFG_R |= EMAC_CFG_TE | EMAC_CFG_RE;
//Enable DMA transmission and reception
EMAC0_DMAOPMODE_R |= EMAC_DMAOPMODE_ST | EMAC_DMAOPMODE_SR;
//Accept any packets from the upper layer
osSetEvent(&interface->nicTxEvent);
//Successful initialization
return NO_ERROR;
}
error_t sama5d3GigabitEthInit(NetInterface *interface)
{
error_t error;
volatile uint32_t status;
//Debug message
TRACE_INFO("Initializing SAMA5D3 Gigabit Ethernet MAC...\r\n");
//Enable GMAC peripheral clock
PMC->PMC_PCER1 = (1 << (ID_GMAC - 32));
//Enable IRQ controller peripheral clock
PMC->PMC_PCER1 = (1 << (ID_IRQ - 32));
//GPIO configuration
sama5d3GigabitEthInitGpio(interface);
//Configure MDC clock speed
GMAC->GMAC_NCFGR = GMAC_NCFGR_DBW_DBW64 | GMAC_NCFGR_CLK_MCK_224;
//Enable management port (MDC and MDIO)
GMAC->GMAC_NCR |= GMAC_NCR_MPE;
//PHY transceiver initialization
error = interface->phyDriver->init(interface);
//Failed to initialize PHY transceiver?
if(error) return error;
//Set the MAC address
GMAC->GMAC_SA[0].GMAC_SAB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
GMAC->GMAC_SA[0].GMAC_SAT = interface->macAddr.w[2];
//Configure the receive filter
GMAC->GMAC_NCFGR |= GMAC_NCFGR_UNIHEN | GMAC_NCFGR_MTIHEN;
//Initialize hash table
GMAC->GMAC_HRB = 0;
GMAC->GMAC_HRT = 0;
//Initialize buffer descriptors
sama5d3GigabitEthInitBufferDesc(interface);
//Clear transmit status register
GMAC->GMAC_TSR = GMAC_TSR_HRESP | GMAC_TSR_UND | GMAC_TSR_TXCOMP | GMAC_TSR_TFC |
GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL | GMAC_TSR_UBR;
//Clear receive status register
GMAC->GMAC_RSR = GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA;
//First disable all GMAC interrupts
GMAC->GMAC_IDR = 0xFFFFFFFF;
//Only the desired ones are enabled
GMAC->GMAC_IER = GMAC_IER_HRESP | GMAC_IER_ROVR | GMAC_IER_TCOMP | GMAC_IER_TFC |
GMAC_IER_RLEX | GMAC_IER_TUR | GMAC_IER_RXUBR | GMAC_IER_RCOMP;
//Read GMAC ISR register to clear any pending interrupt
status = GMAC->GMAC_ISR;
//Configure interrupt controller
AIC->AIC_SSR = ID_GMAC;
AIC->AIC_SMR = AIC_SMR_SRCTYPE_INT_LEVEL_SENSITIVE | AIC_SMR_PRIOR(SAMA5D3_GIGABIT_ETH_IRQ_PRIORITY);
AIC->AIC_SVR = (uint32_t) sama5d3GigabitEthIrqHandler;
//Enable the GMAC to transmit and receive data
GMAC->GMAC_NCR |= GMAC_NCR_TXEN | GMAC_NCR_RXEN;
//Force the TCP/IP stack to check the link state
osSetEvent(&interface->nicRxEvent);
//SAMA5D3 Gigabit Ethernet MAC is now ready to send
osSetEvent(&interface->nicTxEvent);
//Successful initialization
return NO_ERROR;
}
