int main(void) { // Configure pin 7 on EXT1 as output ioport_configure_pin(EXT1_PIN_7,IOPORT_DIR_OUTPUT); sysclk_init(); board_init(); // Start TC and configure pin to get PWM output to LED on IO1 Xplained Pro extension board tc_init(); while (1) { struct pll_config pcfg; /* * Initial state: Running from RC32M prescalers with 16x * prescaling of CLKsys, 2x prescaling for CLKper2 and 2x * prescaling for CLKper. */ wait_for_btn_press(); /* * Prescale CLKsys by 128x, prescale all peripheral clocks by 1. */ sysclk_set_prescalers(SYSCLK_PSADIV_128, SYSCLK_PSBCDIV_1_1); wait_for_btn_press(); /* * Switch to RC2M with 4x prescaling of CLKsys, 4x prescaling * for CLKper2 and 1x prescaling for CLKper. */ osc_enable(OSC_ID_RC2MHZ); do {} while (!osc_is_ready(OSC_ID_RC2MHZ)); sysclk_set_source(SYSCLK_SRC_RC2MHZ); sysclk_set_prescalers(SYSCLK_PSADIV_4, SYSCLK_PSBCDIV_4_1); osc_disable(OSC_ID_RC32MHZ); wait_for_btn_press(); /* * Switch to PLL with RC2M as reference and 4x multiplier. * Prescale CLKsys by 128x, and all peripheral clocks by 1x. */ pll_config_init(&pcfg, PLL_SRC_RC2MHZ, 1, 4); pll_enable(&pcfg, 0); do {} while (!pll_is_locked(0)); sysclk_set_prescalers(SYSCLK_PSADIV_128, SYSCLK_PSBCDIV_1_1); sysclk_set_source(SYSCLK_SRC_PLL); wait_for_btn_press(); /* * Go back to the initial state and start over. */ osc_enable(OSC_ID_RC32MHZ); do {} while(!osc_is_ready(OSC_ID_RC32MHZ)); sysclk_set_source(SYSCLK_SRC_RC32MHZ); sysclk_set_prescalers(SYSCLK_PSADIV_16, SYSCLK_PSBCDIV_2_2); pll_disable(0); osc_disable(OSC_ID_RC2MHZ); } }
/** * \brief cleanup 32KHz oscillator test * * \param test Current test case. */ static void cleanup_osc32_test(const struct test_case *test) { #ifdef BOARD_OSC32_HZ osc_disable(OSC_ID_OSC32); #endif }
/** * \brief cleanup oscillator test * * \param test Current test case. */ static void cleanup_osc_test(const struct test_case *test) { #ifdef BOARD_OSC0_HZ osc_disable(OSC_ID_OSC0); #endif #ifdef BOARD_OSC1_HZ osc_disable(OSC_ID_OSC1); #endif #ifdef BOARD_RC8M_HZ osc_disable(OSC_ID_RC8M); #endif #ifdef BOARD_RC120_HZ osc_disable(OSC_ID_RC120M); #endif #ifdef BOARD_RC1M_HZ osc_disable(OSC_ID_RC1M); #endif #ifdef BOARD_RC80M_HZ osc_disable(OSC_ID_RC80M); #endif #ifdef BOARD_RCFAST_HZ osc_disable(OSC_ID_RCFAST); #endif }
/** * \brief cleanup pll/dfll test * * \param test Current test case. */ static void cleanup_pll_dfll_test(const struct test_case *test) { #ifdef CONFIG_PLL0_SOURCE pll_disable(PLL0); #endif #ifdef CONFIG_PLL1_SOURCE pll_disable(PLL1); #endif #ifdef CONFIG_DFLL0_SOURCE dfll_disable_closed_loop(0); osc_disable(OSC_ID_RCSYS); #endif }
/** * \brief Switch between various system clock sources and prescalers at * run time. * * \return Unused (ANSI-C compatibility). */ int main(void) { struct genclk_config gcfg; sysclk_init(); board_init(); /* Setup SysTick Timer for 1 msec interrupts */ if (SysTick_Config(SystemCoreClock / 1000)) { while (1); // Capture error } /* Enable PIO module related clock */ sysclk_enable_peripheral_clock(PIN_PUSHBUTTON_1_ID); /* Configure specific CLKOUT pin */ ioport_set_pin_mode(GCLK_PIN, GCLK_PIN_MUX); ioport_disable_pin(GCLK_PIN); /* Configure the output clock source and frequency */ genclk_config_defaults(&gcfg, GCLK_ID); genclk_config_set_source(&gcfg, GENCLK_PCK_SRC_PLLACK); genclk_config_set_divider(&gcfg, GENCLK_PCK_PRES_1); genclk_enable(&gcfg, GCLK_ID); while (1) { /* * Initial state. */ wait_for_switches(); /* * Divide MCK frequency by 2. */ sysclk_set_prescalers(SYSCLK_PRES_2); genclk_config_set_divider(&gcfg, GENCLK_PCK_PRES_2); genclk_enable(&gcfg, GCLK_ID); wait_for_switches(); #ifdef BOARD_NO_32K_XTAL /* * Switch to the slow clock with all prescalers disabled. */ sysclk_set_source(SYSCLK_SRC_SLCK_RC); sysclk_set_prescalers(SYSCLK_PRES_1); genclk_config_set_source(&gcfg, GENCLK_PCK_SRC_SLCK_RC); genclk_config_set_divider(&gcfg, GENCLK_PCK_PRES_1); genclk_enable(&gcfg, GCLK_ID); osc_disable(OSC_MAINCK_XTAL); wait_for_switches(); #endif /* * Switch to internal 8 MHz RC. */ /* Switch to slow clock before switch main clock */ sysclk_set_source(SYSCLK_SRC_SLCK_RC); osc_enable(OSC_MAINCK_8M_RC); osc_wait_ready(OSC_MAINCK_8M_RC); sysclk_set_source(SYSCLK_SRC_MAINCK_8M_RC); genclk_config_set_source(&gcfg, GENCLK_PCK_SRC_MAINCK_8M_RC); genclk_enable(&gcfg, GCLK_ID); wait_for_switches(); #if BOARD_FREQ_MAINCK_XTAL /* * Switch to external crystal (8MHz or 12MHz, depend on the board). */ osc_enable(OSC_MAINCK_XTAL); osc_wait_ready(OSC_MAINCK_XTAL); sysclk_set_source(SYSCLK_SRC_MAINCK_XTAL); genclk_config_set_source(&gcfg, GENCLK_PCK_SRC_MAINCK_XTAL); genclk_enable(&gcfg, GCLK_ID); osc_disable(OSC_MAINCK_8M_RC); wait_for_switches(); #endif /* * Go back to the initial state and start over. */ sysclk_init(); genclk_config_set_source(&gcfg, GENCLK_PCK_SRC_PLLACK); genclk_config_set_divider(&gcfg, GENCLK_PCK_PRES_1); genclk_enable(&gcfg, GCLK_ID); } }
void sysclk_init(void) { uint8_t *reg = (uint8_t *)&PR.PRGEN; uint8_t i; #ifdef CONFIG_OSC_RC32_CAL uint16_t cal; #endif bool need_rc2mhz = false; /* Turn off all peripheral clocks that can be turned off. */ for (i = 0; i <= SYSCLK_PORT_F; i++) { *(reg++) = 0xff; } /* Set up system clock prescalers if different from defaults */ if ((CONFIG_SYSCLK_PSADIV != SYSCLK_PSADIV_1) || (CONFIG_SYSCLK_PSBCDIV != SYSCLK_PSBCDIV_1_1)) { sysclk_set_prescalers(CONFIG_SYSCLK_PSADIV, CONFIG_SYSCLK_PSBCDIV); } #if (CONFIG_OSC_RC32_CAL==48000000UL) MSB(cal) = nvm_read_production_signature_row( nvm_get_production_signature_row_offset(USBRCOSC)); LSB(cal) = nvm_read_production_signature_row( nvm_get_production_signature_row_offset(USBRCOSCA)); /* * If a device has an uncalibrated value in the * production signature row (early sample part), load a * sane default calibration value. */ if (cal == 0xFFFF) { cal = 0x2340; } osc_user_calibration(OSC_ID_RC32MHZ,cal); #endif /* * Switch to the selected initial system clock source, unless * the default internal 2 MHz oscillator is selected. */ if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_RC2MHZ) { need_rc2mhz = true; } else { switch (CONFIG_SYSCLK_SOURCE) { case SYSCLK_SRC_RC32MHZ: osc_enable(OSC_ID_RC32MHZ); osc_wait_ready(OSC_ID_RC32MHZ); #ifdef CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC if (CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC != OSC_ID_USBSOF) { osc_enable(CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC); osc_wait_ready(CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC); } osc_enable_autocalibration(OSC_ID_RC32MHZ, CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC); #endif break; case SYSCLK_SRC_RC32KHZ: osc_enable(OSC_ID_RC32KHZ); osc_wait_ready(OSC_ID_RC32KHZ); break; case SYSCLK_SRC_XOSC: osc_enable(OSC_ID_XOSC); osc_wait_ready(OSC_ID_XOSC); break; #ifdef CONFIG_PLL0_SOURCE case SYSCLK_SRC_PLL: if (CONFIG_PLL0_SOURCE == PLL_SRC_RC2MHZ) { need_rc2mhz = true; } pll_enable_config_defaults(0); break; #endif default: //unhandled_case(CONFIG_SYSCLK_SOURCE); return; } ccp_write_io((uint8_t *)&CLK.CTRL, CONFIG_SYSCLK_SOURCE); Assert(CLK.CTRL == CONFIG_SYSCLK_SOURCE); } if (need_rc2mhz) { #ifdef CONFIG_OSC_AUTOCAL_RC2MHZ_REF_OSC osc_enable(CONFIG_OSC_AUTOCAL_RC2MHZ_REF_OSC); osc_wait_ready(CONFIG_OSC_AUTOCAL_RC2MHZ_REF_OSC); osc_enable_autocalibration(OSC_ID_RC2MHZ, CONFIG_OSC_AUTOCAL_RC2MHZ_REF_OSC); #endif } else { osc_disable(OSC_ID_RC2MHZ); } #ifdef CONFIG_RTC_SOURCE sysclk_rtcsrc_enable(CONFIG_RTC_SOURCE); #endif }
void sysclk_init(void) { uint8_t *reg = (uint8_t *)&PR.PRGEN; uint8_t i; #ifdef CONFIG_OSC_RC32_CAL uint16_t cal; #endif /* Turn off all peripheral clocks that can be turned off. */ for (i = 0; i <= SYSCLK_PORT_F; i++) { *(reg++) = 0xff; } /* Set up system clock prescalers if different from defaults */ if ((CONFIG_SYSCLK_PSADIV != SYSCLK_PSADIV_1) || (CONFIG_SYSCLK_PSBCDIV != SYSCLK_PSBCDIV_1_1)) { sysclk_set_prescalers(CONFIG_SYSCLK_PSADIV, CONFIG_SYSCLK_PSBCDIV); } #if (CONFIG_OSC_RC32_CAL==48000000UL) MSB(cal) = nvm_read_production_signature_row( nvm_get_production_signature_row_offset(USBRCOSC)); LSB(cal) = nvm_read_production_signature_row( nvm_get_production_signature_row_offset(USBRCOSCA)); /* * If a device has an uncalibrated value in the * production signature row (early sample part), load a * sane default calibration value. * * MODIFIED 16-7-2012 by C.DOGGEN: * - commented the if statement, otherwise the USART won't work * - don't know exactly the problem, but this seems to be a workaround. */ if (cal == 0xFFFF) { cal = 0x2340; } osc_user_calibration(OSC_ID_RC32MHZ,cal); #endif /* * Switch to the selected initial system clock source, unless * the default internal 2 MHz oscillator is selected. */ if (CONFIG_SYSCLK_SOURCE != SYSCLK_SRC_RC2MHZ) { bool need_rc2mhz = false; switch (CONFIG_SYSCLK_SOURCE) { case SYSCLK_SRC_RC32MHZ: osc_enable(OSC_ID_RC32MHZ); osc_wait_ready(OSC_ID_RC32MHZ); break; case SYSCLK_SRC_RC32KHZ: osc_enable(OSC_ID_RC32KHZ); osc_wait_ready(OSC_ID_RC32KHZ); break; case SYSCLK_SRC_XOSC: osc_enable(OSC_ID_XOSC); osc_wait_ready(OSC_ID_XOSC); break; #ifdef CONFIG_PLL0_SOURCE case SYSCLK_SRC_PLL: if (CONFIG_PLL0_SOURCE == PLL_SRC_RC2MHZ) { need_rc2mhz = true; } pll_enable_config_defaults(0); break; #endif default: //unhandled_case(CONFIG_SYSCLK_SOURCE); return; } ccp_write_io((uint8_t *)&CLK.CTRL, CONFIG_SYSCLK_SOURCE); Assert(CLK.CTRL == CONFIG_SYSCLK_SOURCE); #ifdef CONFIG_OSC_AUTOCAL osc_enable_autocalibration(CONFIG_OSC_AUTOCAL,CONFIG_OSC_AUTOCAL_REF_OSC); if (CONFIG_OSC_AUTOCAL == OSC_ID_RC2MHZ || CONFIG_OSC_AUTOCAL_REF_OSC == OSC_ID_RC2MHZ) { need_rc2mhz = true; } #endif if (!need_rc2mhz) { osc_disable(OSC_ID_RC2MHZ); } } }
int main(void) { sysclk_init(); board_init(); /* Enable one wait state for flash access */ flashcalw_set_wait_state(1); /* * Configure systick for 200ms (CPU frequency / 5) at startup time. * * Note: CPU frequency will be changed with below clock switching. */ if (SysTick_Config(sysclk_get_cpu_hz() / 5)) { while (1) { /* Capture error */ } } while (1) { struct dfll_config dcfg; struct pll_config pcfg; /* avoid Cppcheck Warning */ UNUSED(pcfg); /* * Initial state: Running from RC80M with all * prescalers set to 2 (Divide frequency by 4). */ wait_for_switches(); /* * Divide CPU frequency by 8. This will make the LED * blink half as fast. */ sysclk_set_prescalers(3, 3, 3, 3, 3); wait_for_switches(); /* * Switch to the DFLL running at ~48 MHz in Open Loop * mode, with the CPU running at ~48 MHz. */ dfll_config_init_open_loop_mode(&dcfg); dfll_config_tune_for_target_hz(&dcfg, 48000000); dfll_enable_open_loop(&dcfg, 0); sysclk_set_prescalers(1, 1, 1, 1, 1); sysclk_set_source(SYSCLK_SRC_DFLL); osc_disable(OSC_ID_RC80M); wait_for_switches(); /* * Switch to the slow clock with all prescalers * disabled. */ sysclk_set_source(SYSCLK_SRC_RCSYS); sysclk_set_prescalers(0, 0, 0, 0, 0); dfll_disable_open_loop(0); wait_for_switches(); /* * Switch to the RCFAST clock with all prescalers * disabled. */ osc_enable(OSC_ID_RCFAST); sysclk_set_prescalers(0, 0, 0, 0, 0); osc_wait_ready(OSC_ID_RCFAST); sysclk_set_source(SYSCLK_SRC_RCFAST); wait_for_switches(); /* * Switch to the RC1M clock with all prescalers * disabled. */ osc_enable(OSC_ID_RC1M); sysclk_set_prescalers(0, 0, 0, 0, 0); osc_wait_ready(OSC_ID_RC1M); sysclk_set_source(SYSCLK_SRC_RC1M); osc_disable(OSC_ID_RCFAST); wait_for_switches(); /* * Switch to external OSC0, if available. */ #ifdef BOARD_OSC0_HZ osc_enable(OSC_ID_OSC0); osc_wait_ready(OSC_ID_OSC0); sysclk_set_source(SYSCLK_SRC_OSC0); osc_disable(OSC_ID_RC1M); wait_for_switches(); /* * Switch to PLL0 running at 96 MHz. Use OSC0 as the * source */ pll_config_init(&pcfg, PLL_SRC_OSC0, 1, 96000000 / BOARD_OSC0_HZ); pll_enable(&pcfg, 0); sysclk_set_prescalers(2, 2, 2, 2, 2); pll_wait_for_lock(0); sysclk_set_source(SYSCLK_SRC_PLL0); wait_for_switches(); #endif /* * Switch to the DFLL, using the 32 kHz oscillator as a * reference if available, or failing that, the 115 kHz * RCSYS oscillator. */ #ifdef BOARD_OSC32_HZ osc_enable(OSC_ID_OSC32); dfll_config_init_closed_loop_mode(&dcfg, GENCLK_SRC_OSC32K, 1, CONFIG_DFLL0_FREQ / BOARD_OSC32_HZ); osc_wait_ready(OSC_ID_OSC32); #else dfll_config_init_closed_loop_mode(&dcfg, GENCLK_SRC_RCSYS, 1, CONFIG_DFLL0_FREQ / OSC_RCSYS_NOMINAL_HZ); #endif dfll_enable_closed_loop(&dcfg, 0); sysclk_set_prescalers(1, 1, 1, 1, 1); dfll_wait_for_fine_lock(0); sysclk_set_source(SYSCLK_SRC_DFLL); #ifdef BOARD_OSC0_HZ osc_disable(OSC_ID_OSC0); #endif wait_for_switches(); /* * Go back to the initial state and start over. */ osc_enable(OSC_ID_RC80M); sysclk_set_prescalers(2, 2, 2, 2, 2); osc_wait_ready(OSC_ID_RC80M); sysclk_set_source(SYSCLK_SRC_RC80M); dfll_disable_closed_loop(0); #ifdef BOARD_OSC32_HZ osc_disable(OSC_ID_OSC32); #endif } }