int SensorHAL::getHeight() {
/*
Bohrung oben 3506,3524,3528
Bohrung unten 2470,2478,2480
zu flach 2731,2737
Bohrung oben oM 3492
*/
int hoehe = -1;
int i;
out8(AIO_PORT_A, AIO_GET_VAL);
for (i = 0; i < 50; i++) {
//Bit 7 goes HIGH when an A/D conversion completes
if ((in8(AIO_BASE) & (1 << 7))) { // == (1<<7)
hoehe = in16(AIO_PORT_A);
break;
}
}
return hoehe;
}
/*
* IOControl constructor - initializes I/O settings and controls
*/
IOControl::IOControl( std::queue<Event>* qin, pthread_mutex_t *aQ ) {
// Initialize variables
accessQ = aQ;
q = qin;
// Initialize HW I/O control handlers
if( ThreadCtl(_NTO_TCTL_IO, NULL) == -1 )
{
std::perror("Error - could not access I/O registers");
}
CONTROL_HANDLE = mmap_device_io(IO_PORT_SIZE, IO_CONTROL_REGISTER);
A_HANDLE = mmap_device_io(IO_PORT_SIZE, IO_A_REGISTER);
B_HANDLE = mmap_device_io(IO_PORT_SIZE, IO_B_REGISTER);
C_HANDLE = mmap_device_io(IO_PORT_SIZE, IO_C_REGISTER);
if(CONTROL_HANDLE == MAP_DEVICE_FAILED)
{
std::cout << "Failed to map control register";
}
if(A_HANDLE == MAP_DEVICE_FAILED)
{
std::cout << "Failed to map register A";
}
if(B_HANDLE == MAP_DEVICE_FAILED)
{
std::cout << "Failed to map register B";
}
if(C_HANDLE == MAP_DEVICE_FAILED)
{
std::cout << "Failed to map register C";
}
// Initialize control register
// A is input
// B,C are output
out8(CONTROL_HANDLE,0x90);
}
static int __read_sectors_lba48(void *data, unsigned long long sector,
size_t count)
{
const unsigned long slo = sector & 0xfffffffful;
const unsigned long shi = sector >> 32;
const unsigned clo = count & 0xffu;
const unsigned chi = count >> 8;
ide_wait_ready();
out8(IDE_DEVCTL_REG, IDE_NIEN);
out8(IDE_SC_REG, chi);
out8(IDE_LBA0_REG, shi & 0xff);
out8(IDE_LBA1_REG, (shi >> 8) & 0xff);
out8(IDE_LBA2_REG, (shi >> 16) & 0xff);
out8(IDE_SC_REG, clo);
out8(IDE_LBA0_REG, slo & 0xff);
out8(IDE_LBA1_REG, (slo >> 8) & 0xff);
out8(IDE_LBA2_REG, (slo >> 16) & 0xff);
out8(IDE_DEV_REG, IDE_LBA);
out8(IDE_CMD_REG, IDE_CMD_READ_LBA48);
ide_wait_ready();
uint16_t *wptr = (uint16_t *)data;
const size_t words = IDE_SECTOR_SIZE / sizeof(*wptr);
for (size_t i = 0; i != count; ++i) {
for (size_t j = 0; j != words; ++j)
*wptr++ = in16(IDE_DATA_REG);
in8(IDE_ASTATUS_REG); // wait one PIO transfer cycle
if (ide_wait_ready() != 0)
return -1;
}
return 0;
}
///// 制御ボードイニシャライズ関数//////////////////////////////////////////////
void Board_Open(void)
{
int ch;
ThreadCtl(_NTO_TCTL_IO,0);
mmap_device_io(BIO_SIZE,0x300);
///// カウンタ初期化 /////
out8(Count_com,0x13); //A-2-phase x4
out8(Count_com,0x1b); //B-2-phase x4
out8(Count_com,0x14); //A-count enable set
out8(Count_com,0x1c); //B-count enable set
out8(Count_com,0x16); //separate mode
out8(Count_com,0x0e); //level CLR
out8(Count_com,0x0f); //edge CLR
for(ch=1; ch<=Channel; ch++){
M[ch].AD_Init = 2048; //とりあえずのADの初期値
DA_Write(ch,2048); //2.5V出力
}
}
/** Handler for a PCI ATA IRQ.
* @param num IRQ number.
* @param _channel Pointer to channel structure.
* @return Whether the IRQ was handled. */
static irq_status_t pci_ata_irq_handler(unsigned num, void *_channel) {
pci_ata_channel_t *data = _channel;
uint8_t status;
if(!data->channel) {
return IRQ_UNHANDLED;
}
/* Check whether this device has raised an interrupt. */
status = in8(data->bus_master_base + PCI_ATA_BM_REG_STATUS);
if(!(status & PCI_ATA_BM_STATUS_INTERRUPT)) {
return IRQ_UNHANDLED;
}
/* Clear interrupt flag. */
out8(data->bus_master_base + PCI_ATA_BM_REG_STATUS, (status & 0xF8) | PCI_ATA_BM_STATUS_INTERRUPT);
/* Clear INTRQ. */
in8(data->cmd_base + ATA_CMD_REG_STATUS);
/* Pass the interrupt to the ATA bus manager. */
return ata_channel_interrupt(data->channel);
}
/**
* Hauptschleife des geerbten HAW-Thread.
* Die oberklasse HAW-Thread erzwingt die Implementierung der execute Methode.
* Der Thread endet nach Ende dieser Methode.
*/
void Blink_Thread::execute(void*){
/* Klassenweiten Mutex, locken. */
Lock lock(&mtx_);
cout << "Blink_Thread executing" << endl;
/* Zugriffsrechte von QNX fuer diesen Thread, auf die Hardware erbitten. */
if( ThreadCtl(_NTO_TCTL_IO_PRIV,0) == -1 ){
cout << "Can't get Hardware access, therefore can't do anything." << endl;
}
/* IO Register als Eingänge bzw. Ausgänge definieren. */
out8(ioControlAddress_, ioControlBitmask_);
/* Gruenes Licht blinken lassen inkl. Pruefung ob der Thread extern gestoppt wurde. */
for(int i = 0; i < times_; i++){
/* Pruefen ob der Thread durch stop() beendet wurde. */
if( !isStopped() ){
turnGreenOn();
usleep(500000);
turnGreenOff();
usleep(500000);
}
}
}
const struct sigevent* ISR(void *arg, int id) {
struct sigevent *event = (struct sigevent *) arg;
int portB = 0;
int portC = 0;
int iir = in8(DIO_INTERRUPT_READ_CLEAR); //Status auslesen und IRQ zurück setzen
event->sigev_value.sival_int = 0;
event->sigev_notify = SIGEV_PULSE;
if (iir == PORTB_INTERRUPT || iir == PORTC_INTERRUPT) {
portB = in8(PORT_B);
portC = in8(PORT_C) & 0xF0;
portC = portC << 4;
event->sigev_value.sival_int = portC | portB;
} else {
return NULL;
}
out8(DIO_INTERRUPT_CLEAR_REG, 0x00);
return event;
}
int write_RXFE_EEPROM_address(int base, int cardnum, unsigned int address, int Adata){
int temp;
int WE_on=0x01, RW_on=0x40;
if ( (cardnum > 32) || (cardnum < 0)){
printf("ERROR: Card numnber must be between 0 and 32\n");
}
cardnum=cardnum & 0x1f;
cardnum=cardnum << 1;
#ifdef __QNX__
// set all groups as output
out8(base+CNTRL_GRP_4,0x80);
set_RXFE_EEPROM_address(base, address);
// set R/W bit to write
out8(base+PC_GRP_4,RW_on | cardnum);
// set data to write
out8(base+PA_GRP_4,Adata);
// set WE bit high
out8(base+PC_GRP_4,RW_on | WE_on | cardnum);
// set WE bit low
out8(base+PC_GRP_4,RW_on | cardnum);
delay(10);
// set port A as input
out8(base+CNTRL_GRP_4,0x90);
set_RXFE_EEPROM_address(base, address);
// set R/W bit low
out8(base+PC_GRP_4,cardnum);
//delay(1000);
delay(4);
temp=in8(base+PA_GRP_4);
if (temp != Adata){
printf("WRITE ERROR\n");
}
printf("%d was read on port A\n", temp);
#endif
}
void
pic_init()
{
static const interrupt_controller picController = {
"8259 PIC",
&pic_enable_io_interrupt,
&pic_disable_io_interrupt,
&pic_configure_io_interrupt,
&pic_is_spurious_interrupt,
&pic_is_level_triggered_interrupt,
&pic_end_of_interrupt
};
// Start initialization sequence for the master and slave PICs
out8(PIC_INIT1 | PIC_INIT1_SEND_INIT4, PIC_MASTER_INIT1);
out8(PIC_INIT1 | PIC_INIT1_SEND_INIT4, PIC_SLAVE_INIT1);
// Set start of interrupts to 0x20 for master, 0x28 for slave
out8(ARCH_INTERRUPT_BASE, PIC_MASTER_INIT2);
out8(ARCH_INTERRUPT_BASE + PIC_SLAVE_INT_BASE, PIC_SLAVE_INIT2);
// Specify cascading through interrupt 2
out8(PIC_INIT3_IR2_IS_SLAVE, PIC_MASTER_INIT3);
out8(PIC_INIT3_SLAVE_ID2, PIC_SLAVE_INIT3);
// Set both to operate in 8086 mode
out8(PIC_INIT4_x86_MODE, PIC_MASTER_INIT4);
out8(PIC_INIT4_x86_MODE, PIC_SLAVE_INIT4);
out8(0xfb, PIC_MASTER_MASK); // Mask off all interrupts (except slave pic line IRQ 2).
out8(0xff, PIC_SLAVE_MASK); // Mask off interrupts on the slave.
// determine which interrupts are level or edge triggered
#if 0
// should set everything possible to level triggered
out8(0xf8, PIC_MASTER_TRIGGER_MODE);
out8(0xde, PIC_SLAVE_TRIGGER_MODE);
#endif
sLevelTriggeredInterrupts = in8(PIC_MASTER_TRIGGER_MODE)
| (in8(PIC_SLAVE_TRIGGER_MODE) << 8);
TRACE(("PIC level trigger mode: 0x%08lx\n", sLevelTriggeredInterrupts));
// make the pic controller the current one
arch_int_set_interrupt_controller(picController);
}
void kbd_write_output(unsigned char data)
{
out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data);
}
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
volatile ulong addr = info->start[0];
int flag, prot, sect, l_sect;
ulong start, now, last;
flash_to_xd();
if (s_first < 0 || s_first > s_last) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
flash_to_mem();
return 1;
}
if (info->flash_id == FLASH_UNKNOWN) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
flash_to_mem();
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
out8(addr + 0x555, 0xAA);
iobarrier_rw();
out8(addr + 0x2AA, 0x55);
iobarrier_rw();
out8(addr + 0x555, 0x80);
iobarrier_rw();
out8(addr + 0x555, 0xAA);
iobarrier_rw();
out8(addr + 0x2AA, 0x55);
iobarrier_rw();
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = info->start[sect];
out8(addr, 0x30);
iobarrier_rw();
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer (0);
last = start;
addr = info->start[l_sect];
DEBUGF ("Start erase timeout: %d\n", CONFIG_SYS_FLASH_ERASE_TOUT);
while ((in8(addr) & 0x80) != 0x80) {
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
flash_reset (info->start[0]);
flash_to_mem();
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
iobarrier_rw();
}
DONE:
/* reset to read mode */
flash_reset (info->start[0]);
flash_to_mem();
printf (" done\n");
return 0;
}
/*
* pic_init()
* Initialise the 8259 interrupt controllers
*/
void pic_init(void)
{
/*
* initialise the 8259's
*/
out8(PIC0_ICW1, 0x11); /* Reset */
out8(PIC0_ICW2, IRQ_BASE); /* Vectors served */
out8(PIC0_ICW3, 1 << 2); /* Chain to PIC1 */
out8(PIC0_ICW4, 1); /* 8086 mode */
out8(PIC0_OCW1, 0xff); /* No interrupts for now */
out8(PIC0_OCW2, 2); /* ISR mode */
out8(PIC1_ICW1, 0x11); /* Reset */
out8(PIC1_ICW2, IRQ_BASE + 8); /* Vectors served */
out8(PIC1_ICW3, 2); /* We are a slave unit */
out8(PIC1_ICW4, 1); /* 8086 mode */
out8(PIC1_OCW1, 0xff); /* No interrupts for now */
out8(PIC1_OCW2, 2); /* ISR mode */
}
void kbd_write_command(unsigned char cmd)
{
out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd);
}
void write_ec_sc(ec_dev_t* dev, uint8_t data)
{
out8(EC_SC, data);
}
status_t
pci_controller_init(void)
{
bool search_mech1 = true;
bool search_mech2 = true;
bool search_bios = true;
void *config = NULL;
status_t status;
status = pci_x86_irq_init();
if (status != B_OK)
return status;
config = load_driver_settings("pci");
if (config) {
const char *mech = get_driver_parameter(config, "mechanism",
NULL, NULL);
if (mech) {
search_mech1 = search_mech2 = search_bios = false;
if (strcmp(mech, "1") == 0)
search_mech1 = true;
else if (strcmp(mech, "2") == 0)
search_mech2 = true;
else if (strcmp(mech, "bios") == 0)
search_bios = true;
else
panic("Unknown pci config mechanism setting %s\n", mech);
}
unload_driver_settings(config);
}
// TODO: check safemode "don't call the BIOS" setting and unset search_bios!
// PCI configuration mechanism 1 is the preferred one.
// If it doesn't work, try mechanism 2.
// Finally, try to fallback to PCI BIOS
if (search_mech1) {
// check for mechanism 1
out32(0x80000000, PCI_MECH1_REQ_PORT);
if (0x80000000 == in32(PCI_MECH1_REQ_PORT)) {
dprintf("PCI: mechanism 1 controller found\n");
return pci_controller_add(&pci_controller_x86_mech1, NULL);
}
}
if (search_mech2) {
// check for mechanism 2
out8(0x00, 0xCFB);
out8(0x00, 0xCF8);
out8(0x00, 0xCFA);
if (in8(0xCF8) == 0x00 && in8(0xCFA) == 0x00) {
dprintf("PCI: mechanism 2 controller found\n");
return pci_controller_add(&pci_controller_x86_mech2, NULL);
}
}
if (search_bios) {
// check for PCI BIOS
if (pci_bios_init() == B_OK) {
dprintf("PCI: BIOS support found\n");
return pci_controller_add(&pci_controller_x86_bios, NULL);
}
}
dprintf("PCI: no configuration mechanism found\n");
return B_ERROR;
}
void i2c_init (int speed, int slaveadd)
{
sys_info_t sysInfo;
unsigned long freqOPB;
int val, divisor;
#ifdef CFG_I2C_INIT_BOARD
/* call board specific i2c bus reset routine before accessing the */
/* environment, which might be in a chip on that bus. For details */
/* about this problem see doc/I2C_Edge_Conditions. */
i2c_init_board();
#endif
/* Handle possible failed I2C state */
/* FIXME: put this into i2c_init_board()? */
_i2c_bus_reset ();
/* clear lo master address */
out8 (IIC_LMADR, 0);
/* clear hi master address */
out8 (IIC_HMADR, 0);
/* clear lo slave address */
out8 (IIC_LSADR, 0);
/* clear hi slave address */
out8 (IIC_HSADR, 0);
/* Clock divide Register */
/* get OPB frequency */
get_sys_info (&sysInfo);
freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
/* set divisor according to freqOPB */
divisor = (freqOPB - 1) / 10000000;
if (divisor == 0)
divisor = 1;
out8 (IIC_CLKDIV, divisor);
/* no interrupts */
out8 (IIC_INTRMSK, 0);
/* clear transfer count */
out8 (IIC_XFRCNT, 0);
/* clear extended control & stat */
/* write 1 in SRC SRS SWC SWS to clear these fields */
out8 (IIC_XTCNTLSS, 0xF0);
/* Mode Control Register
Flush Slave/Master data buffer */
out8 (IIC_MDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
__asm__ volatile ("eieio");
val = in8(IIC_MDCNTL);
__asm__ volatile ("eieio");
/* Ignore General Call, slave transfers are ignored,
disable interrupts, exit unknown bus state, enable hold
SCL
100kHz normaly or FastMode for 400kHz and above
*/
val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
if( speed >= 400000 ){
val |= IIC_MDCNTL_FSM;
}
out8 (IIC_MDCNTL, val);
/* clear control reg */
out8 (IIC_CNTL, 0x00);
__asm__ volatile ("eieio");
}
static void rtc_write (short reg, uchar val)
{
out8(RTC(reg),val);
}
/*
This code tries to use the features of the 405GP i2c
controller. It will transfer up to 4 bytes in one pass
on the loop. It only does out8(lbz) to the buffer when it
is possible to do out16(lhz) transfers.
cmd_type is 0 for write 1 for read.
addr_len can take any value from 0-255, it is only limited
by the char, we could make it larger if needed. If it is
0 we skip the address write cycle.
Typical case is a Write of an addr followd by a Read. The
IBM FAQ does not cover this. On the last byte of the write
we don't set the creg CHT bit, and on the first bytes of the
read we set the RPST bit.
It does not support address only transfers, there must be
a data part. If you want to write the address yourself, put
it in the data pointer.
It does not support transfer to/from address 0.
It does not check XFRCNT.
*/
static
int i2c_transfer(unsigned char cmd_type,
unsigned char chip,
unsigned char addr[],
unsigned char addr_len,
unsigned char data[],
unsigned short data_len )
{
unsigned char* ptr;
int reading;
int tran,cnt;
int result;
int status;
int i;
uchar creg;
if( data == 0 || data_len == 0 ){
/*Don't support data transfer of no length or to address 0*/
printf( "i2c_transfer: bad call\n" );
return IIC_NOK;
}
if( addr && addr_len ){
ptr = addr;
cnt = addr_len;
reading = 0;
}else{
ptr = data;
cnt = data_len;
reading = cmd_type;
}
/*Clear Stop Complete Bit*/
out8(IIC_STS,IIC_STS_SCMP);
/* Check init */
i=10;
do {
/* Get status */
status = in8(IIC_STS);
__asm__ volatile("eieio");
i--;
} while ((status & IIC_STS_PT) && (i>0));
if (status & IIC_STS_PT) {
result = IIC_NOK_TOUT;
return(result);
}
/*flush the Master/Slave Databuffers*/
out8(IIC_MDCNTL, ((in8(IIC_MDCNTL))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
/*need to wait 4 OPB clocks? code below should take that long*/
/* 7-bit adressing */
out8(IIC_HMADR,0);
out8(IIC_LMADR, chip);
__asm__ volatile("eieio");
tran = 0;
result = IIC_OK;
creg = 0;
while ( tran != cnt && (result == IIC_OK)) {
int bc,j;
/* Control register =
Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
Transfer is a sequence of transfers
*/
creg |= IIC_CNTL_PT;
bc = (cnt - tran) > 4 ? 4 :
cnt - tran;
creg |= (bc-1)<<4;
/* if the real cmd type is write continue trans*/
if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) )
creg |= IIC_CNTL_CHT;
if (reading)
creg |= IIC_CNTL_READ;
else {
for(j=0; j<bc; j++) {
/* Set buffer */
out8(IIC_MDBUF,ptr[tran+j]);
__asm__ volatile("eieio");
}
}
out8(IIC_CNTL, creg );
__asm__ volatile("eieio");
/* Transfer is in progress
we have to wait for upto 5 bytes of data
1 byte chip address+r/w bit then bc bytes
of data.
udelay(10) is 1 bit time at 100khz
Doubled for slop. 20 is too small.
*/
i=2*5*8;
do {
/* Get status */
status = in8(IIC_STS);
__asm__ volatile("eieio");
udelay (10);
i--;
} while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
&& (i>0));
if (status & IIC_STS_ERR) {
result = IIC_NOK;
status = in8 (IIC_EXTSTS);
/* Lost arbitration? */
if (status & IIC_EXTSTS_LA)
result = IIC_NOK_LA;
/* Incomplete transfer? */
if (status & IIC_EXTSTS_ICT)
result = IIC_NOK_ICT;
/* Transfer aborted? */
if (status & IIC_EXTSTS_XFRA)
result = IIC_NOK_XFRA;
} else if ( status & IIC_STS_PT) {
result = IIC_NOK_TOUT;
}
/* Command is reading => get buffer */
if ((reading) && (result == IIC_OK)) {
/* Are there data in buffer */
if (status & IIC_STS_MDBS) {
/*
even if we have data we have to wait 4OPB clocks
for it to hit the front of the FIFO, after that
we can just read. We should check XFCNT here and
if the FIFO is full there is no need to wait.
*/
udelay (1);
for(j=0;j<bc;j++) {
ptr[tran+j] = in8(IIC_MDBUF);
__asm__ volatile("eieio");
}
} else
result = IIC_NOK_DATA;
}
/*
* Function - operation_thread()
*
* Arguments - <args> Pointer to this thread's arguments
*
* Return Value - Pointer to the return value
*/
void * operation_thread(void * args)
{
uint8_t port_val = 0;
uint32_t total_time = 0;
uint32_t count = 0, sec = 0;
sint32_t rcv_id;
#if defined (__ARM__)
sint32_t temp_high = 0, temp_low = 0;
#endif // #if defined (__ARM__)
// Setup the timer for PWM
__pwm_setup();
// Wait for timer pulse
for (;;)
{
rcv_id = MsgReceive(channel_id, &timer_msg, sizeof(timer_msg), NULL);
if(rcv_id == 0)
{
if(timer_msg.pulse.code == __TIMER_PULSE_CODE)
{
if(__OP_IDLE == state)
{
sec = 0;
count = 0;
total_time = 0;
}
else
{
if(0 == local_vol)
{
state = __OP_IDLE;
if(0 == pthread_mutex_lock(&operation_mutex))
{
operation = __OP_COMPLETE;
pthread_mutex_unlock(&operation_mutex);
}
}
if(1000 == ++count)
{
count = 0;
sec++;
}
if(60 == sec)
{
sec = 0;
total_time++;
if(local_vol >= local_flowrate)
local_vol -= local_flowrate;
else
local_vol = 0;
if(0 == pthread_mutex_lock(&operation_mutex))
{
op_percentage = 100 - ((local_vol * 100) / start_vol);
pthread_mutex_unlock(&operation_mutex);
}
}
}
#if defined (__ARM__)
// PWM pulse
if(0 < --temp_high)
{
port_val = in8(gpio_base + 0);
port_val |= GPIO_SERVO_PIN;
out8(gpio_base + 0, port_val);
}
else if(0 < --temp_low)
{
port_val = in8(gpio_base + 0);
port_val &= (uint8_t)(~(GPIO_SERVO_PIN));
out8(gpio_base + 0, port_val);
}
else if(__OP_IDLE == state)
{
temp_high = __DEFALT_DUTY_CYCLE;
temp_low = __DEFALT_DUTY_CYCLE;
}
else
{
temp_high = steps_high;
temp_low = steps_low;
}
#endif // #if defined (__ARM__)
}
}
}
return ((void *)NULL);
}
// ------------------------------------------------------------------------------------------------
void pci_out8(uint id, uint reg, u8 data)
{
u32 address = 0x80000000 | id | (reg & 0xfc);
out32(PCI_CONFIG_ADDR, address);
out8(PCI_CONFIG_DATA + (reg & 0x03), data);
}
static uchar rtc_read (short reg)
{
out8(RTC_PORT_ADDR0, reg & 0xFF);
out8(RTC_PORT_ADDR1, (reg>>8) & 0xFF);
return in8(RTC_PORT_DATA);
}
/*
* ATIUnlock --
*
* This function is entered to unlock registers and disable unwanted
* emulations. It saves the current state for later restoration by ATILock().
*/
void
ATIUnlock
(
ATIPtr pATI
)
{
CARD32 tmp;
#ifndef AVOID_CPIO
CARD32 saved_lcd_gen_ctrl = 0, lcd_gen_ctrl = 0;
#endif /* AVOID_CPIO */
if (pATI->Unlocked)
return;
pATI->Unlocked = TRUE;
{
/* Reset everything */
pATI->LockData.bus_cntl = inr(BUS_CNTL);
if (pATI->Chip < ATI_CHIP_264VT4)
{
pATI->LockData.bus_cntl =
(pATI->LockData.bus_cntl & ~BUS_HOST_ERR_INT_EN) |
BUS_HOST_ERR_INT;
if (pATI->Chip < ATI_CHIP_264VTB)
pATI->LockData.bus_cntl =
(pATI->LockData.bus_cntl & ~BUS_FIFO_ERR_INT_EN) |
BUS_FIFO_ERR_INT;
}
tmp = pATI->LockData.bus_cntl & ~BUS_ROM_DIS;
if (pATI->Chip < ATI_CHIP_264VTB)
tmp |= SetBits(15, BUS_FIFO_WS);
else
tmp &= ~BUS_MASTER_DIS;
if (pATI->Chip >= ATI_CHIP_264VT)
tmp |= BUS_EXT_REG_EN; /* Enable Block 1 */
outr(BUS_CNTL, tmp);
pATI->LockData.crtc_int_cntl = inr(CRTC_INT_CNTL);
outr(CRTC_INT_CNTL, (pATI->LockData.crtc_int_cntl & ~CRTC_INT_ENS) |
CRTC_INT_ACKS);
#ifdef XF86DRI_DEVEL
if (pATI->irq > 0)
outr(CRTC_INT_CNTL, (inr(CRTC_INT_CNTL) & ~CRTC_INT_ACKS) |
CRTC_VBLANK_INT_EN); /* Enable VBLANK interrupt - handled by DRM */
#endif /* XF86DRI_DEVEL */
pATI->LockData.gen_test_cntl = inr(GEN_TEST_CNTL) &
(GEN_OVR_OUTPUT_EN | GEN_OVR_POLARITY | GEN_CUR_EN |
GEN_BLOCK_WR_EN);
tmp = pATI->LockData.gen_test_cntl & ~GEN_CUR_EN;
outr(GEN_TEST_CNTL, tmp | GEN_GUI_EN);
outr(GEN_TEST_CNTL, tmp);
outr(GEN_TEST_CNTL, tmp | GEN_GUI_EN);
tmp = pATI->LockData.crtc_gen_cntl = inr(CRTC_GEN_CNTL) &
~(CRTC_EN | CRTC_LOCK_REGS);
if (pATI->Chip >= ATI_CHIP_264XL)
tmp = (tmp & ~CRTC_INT_ENS_X) | CRTC_INT_ACKS_X;
outr(CRTC_GEN_CNTL, tmp | CRTC_EN);
outr(CRTC_GEN_CNTL, tmp);
outr(CRTC_GEN_CNTL, tmp | CRTC_EN);
if ((pATI->LCDPanelID >= 0) && (pATI->Chip != ATI_CHIP_264LT))
{
pATI->LockData.lcd_index = inr(LCD_INDEX);
if (pATI->Chip >= ATI_CHIP_264XL)
outr(LCD_INDEX, pATI->LockData.lcd_index &
~(LCD_MONDET_INT_EN | LCD_MONDET_INT));
/*
* Prevent BIOS initiated display switches on dual-CRT controllers.
*/
if (!pATI->OptionBIOSDisplay && (pATI->Chip != ATI_CHIP_264XL))
{
#ifdef TV_OUT
pATI->LockData.scratch_reg3 = inr(SCRATCH_REG3) & ~DISPLAY_SWITCH_DISABLE;
outr(SCRATCH_REG3, pATI->LockData.scratch_reg3);
#else
pATI->LockData.scratch_reg3 = inr(SCRATCH_REG3);
outr(SCRATCH_REG3,
pATI->LockData.scratch_reg3 | DISPLAY_SWITCH_DISABLE);
#endif /* TV_OUT */
}
}
pATI->LockData.mem_cntl = inr(MEM_CNTL);
if (pATI->Chip < ATI_CHIP_264CT)
outr(MEM_CNTL, pATI->LockData.mem_cntl &
~(CTL_MEM_BNDRY | CTL_MEM_BNDRY_EN));
/* Disable feature connector on integrated controllers */
tmp = pATI->LockData.dac_cntl = inr(DAC_CNTL);
if (pATI->Chip >= ATI_CHIP_264CT)
tmp &= ~DAC_FEA_CON_EN;
#ifndef AVOID_CPIO
/* Ensure VGA aperture is enabled */
pATI->LockData.config_cntl = inr(CONFIG_CNTL);
tmp |= DAC_VGA_ADR_EN;
outr(CONFIG_CNTL, pATI->LockData.config_cntl & ~CFG_VGA_DIS);
#endif /* AVOID_CPIO */
outr(DAC_CNTL, tmp);
if (pATI->Chip >= ATI_CHIP_264VTB)
{
pATI->LockData.mpp_config = inr(MPP_CONFIG);
pATI->LockData.mpp_strobe_seq = inr(MPP_STROBE_SEQ);
pATI->LockData.tvo_cntl = inr(TVO_CNTL);
if (pATI->Chip >= ATI_CHIP_264GT2C)
{
pATI->LockData.hw_debug = inr(HW_DEBUG);
if (pATI->Chip >= ATI_CHIP_264GTPRO)
{
if (!(pATI->LockData.hw_debug & CMDFIFO_SIZE_EN))
outr(HW_DEBUG,
pATI->LockData.hw_debug | CMDFIFO_SIZE_EN);
pATI->LockData.i2c_cntl_0 =
inr(I2C_CNTL_0) | (I2C_CNTL_STAT | I2C_CNTL_HPTR_RST);
outr(I2C_CNTL_0,
pATI->LockData.i2c_cntl_0 & ~I2C_CNTL_INT_EN);
pATI->LockData.i2c_cntl_1 = inr(I2C_CNTL_1);
}
else
{
if (pATI->LockData.hw_debug & CMDFIFO_SIZE_DIS)
outr(HW_DEBUG,
pATI->LockData.hw_debug & ~CMDFIFO_SIZE_DIS);
}
}
}
}
#ifndef AVOID_CPIO
if (pATI->VGAAdapter)
{
if (pATI->CPIO_VGAWonder)
{
/*
* Ensure all registers are read/write and disable all non-VGA
* emulations.
*/
pATI->LockData.b1 = ATIGetExtReg(0xB1U);
ATIModifyExtReg(pATI, 0xB1U, pATI->LockData.b1, 0xFCU, 0x00U);
pATI->LockData.b4 = ATIGetExtReg(0xB4U);
ATIModifyExtReg(pATI, 0xB4U, pATI->LockData.b4, 0x00U, 0x00U);
pATI->LockData.b5 = ATIGetExtReg(0xB5U);
ATIModifyExtReg(pATI, 0xB5U, pATI->LockData.b5, 0xBFU, 0x00U);
pATI->LockData.b6 = ATIGetExtReg(0xB6U);
ATIModifyExtReg(pATI, 0xB6U, pATI->LockData.b6, 0xDDU, 0x00U);
pATI->LockData.b8 = ATIGetExtReg(0xB8U);
ATIModifyExtReg(pATI, 0xB8U, pATI->LockData.b8, 0xC0U, 0x00U);
pATI->LockData.b9 = ATIGetExtReg(0xB9U);
ATIModifyExtReg(pATI, 0xB9U, pATI->LockData.b9, 0x7FU, 0x00U);
{
pATI->LockData.be = ATIGetExtReg(0xBEU);
ATIModifyExtReg(pATI, 0xBEU, pATI->LockData.be, 0xFAU, 0x01U);
{
pATI->LockData.a6 = ATIGetExtReg(0xA6U);
ATIModifyExtReg(pATI, 0xA6U, pATI->LockData.a6,
0x7FU, 0x00U);
pATI->LockData.ab = ATIGetExtReg(0xABU);
ATIModifyExtReg(pATI, 0xABU, pATI->LockData.ab,
0xE7U, 0x00U);
}
}
}
if (pATI->LCDPanelID >= 0)
{
if (pATI->Chip == ATI_CHIP_264LT)
{
saved_lcd_gen_ctrl = inr(LCD_GEN_CTRL);
/* Setup to unlock non-shadow registers */
lcd_gen_ctrl = saved_lcd_gen_ctrl & ~SHADOW_RW_EN;
outr(LCD_GEN_CTRL, lcd_gen_ctrl);
}
else /* if ((pATI->Chip == ATI_CHIP_264LTPRO) ||
(pATI->Chip == ATI_CHIP_264XL) ||
(pATI->Chip == ATI_CHIP_MOBILITY)) */
{
saved_lcd_gen_ctrl = ATIMach64GetLCDReg(LCD_GEN_CNTL);
/* Setup to unlock non-shadow registers */
lcd_gen_ctrl = saved_lcd_gen_ctrl &
~(CRTC_RW_SELECT | SHADOW_RW_EN);
ATIMach64PutLCDReg(LCD_GEN_CNTL, lcd_gen_ctrl);
}
}
ATISetVGAIOBase(pATI, inb(R_GENMO));
/*
* There's a bizarre interaction here. If bit 0x80 of CRTC[17] is on,
* then CRTC[3] is read-only. If bit 0x80 of CRTC[3] is off, then
* CRTC[17] is write-only (or a read attempt actually returns bits from
* C/EGA's light pen position). This means that if both conditions are
* met, CRTC[17]'s value on server entry cannot be retrieved.
*/
pATI->LockData.crt03 = tmp = GetReg(CRTX(pATI->CPIO_VGABase), 0x03U);
if ((tmp & 0x80U) ||
((outb(CRTD(pATI->CPIO_VGABase), tmp | 0x80U),
tmp = inb(CRTD(pATI->CPIO_VGABase))) & 0x80U))
{
/* CRTC[16-17] should be readable */
pATI->LockData.crt11 = tmp =
GetReg(CRTX(pATI->CPIO_VGABase), 0x11U);
if (tmp & 0x80U) /* Unprotect CRTC[0-7] */
outb(CRTD(pATI->CPIO_VGABase), tmp & 0x7FU);
}
else
{
/*
* Could not make CRTC[17] readable, so unprotect CRTC[0-7]
* replacing VSyncEnd with zero. This zero will be replaced after
* acquiring the needed access.
*/
unsigned int VSyncEnd, VBlankStart, VBlankEnd;
CARD8 crt07, crt09;
PutReg(CRTX(pATI->CPIO_VGABase), 0x11U, 0x20U);
/* Make CRTC[16-17] readable */
PutReg(CRTX(pATI->CPIO_VGABase), 0x03U, tmp | 0x80U);
/* Make vertical synch pulse as wide as possible */
crt07 = GetReg(CRTX(pATI->CPIO_VGABase), 0x07U);
crt09 = GetReg(CRTX(pATI->CPIO_VGABase), 0x09U);
VBlankStart = (((crt09 & 0x20U) << 4) | ((crt07 & 0x08U) << 5) |
GetReg(CRTX(pATI->CPIO_VGABase), 0x15U)) + 1;
VBlankEnd = (VBlankStart & 0x0300U) |
GetReg(CRTX(pATI->CPIO_VGABase), 0x16U);
if (VBlankEnd <= VBlankStart)
VBlankEnd += 0x0100U;
VSyncEnd = (((crt07 & 0x80U) << 2) | ((crt07 & 0x04U) << 6) |
GetReg(CRTX(pATI->CPIO_VGABase), 0x10U)) + 0x0FU;
if (VSyncEnd >= VBlankEnd)
VSyncEnd = VBlankEnd - 1;
pATI->LockData.crt11 = (VSyncEnd & 0x0FU) | 0x20U;
PutReg(CRTX(pATI->CPIO_VGABase), 0x11U, pATI->LockData.crt11);
pATI->LockData.crt11 |= 0x80U;
}
if (pATI->LCDPanelID >= 0)
{
/* Setup to unlock shadow registers */
lcd_gen_ctrl |= SHADOW_RW_EN;
if (pATI->Chip == ATI_CHIP_264LT)
outr(LCD_GEN_CTRL, lcd_gen_ctrl);
else /* if ((pATI->Chip == ATI_CHIP_264LTPRO) ||
(pATI->Chip == ATI_CHIP_264XL) ||
(pATI->Chip == ATI_CHIP_MOBILITY)) */
ATIMach64PutLCDReg(LCD_GEN_CNTL, lcd_gen_ctrl);
/* Unlock shadow registers */
ATISetVGAIOBase(pATI, inb(R_GENMO));
pATI->LockData.shadow_crt03 = tmp =
GetReg(CRTX(pATI->CPIO_VGABase), 0x03U);
if ((tmp & 0x80U) ||
((outb(CRTD(pATI->CPIO_VGABase), tmp | 0x80U),
tmp = inb(CRTD(pATI->CPIO_VGABase))) & 0x80U))
{
/* CRTC[16-17] should be readable */
pATI->LockData.shadow_crt11 = tmp =
GetReg(CRTX(pATI->CPIO_VGABase), 0x11U);
if (tmp & 0x80U) /* Unprotect CRTC[0-7] */
{
outb(CRTD(pATI->CPIO_VGABase), tmp & 0x7FU);
}
else if (!tmp && pATI->LockData.crt11)
{
pATI->LockData.shadow_crt11 = tmp = pATI->LockData.crt11;
outb(CRTD(pATI->CPIO_VGABase), tmp & 0x7FU);
}
}
else
{
/*
* Could not make CRTC[17] readable, so unprotect CRTC[0-7]
* replacing VSyncEnd with zero. This zero will be replaced
* after acquiring the needed access.
*/
unsigned int VSyncEnd, VBlankStart, VBlankEnd;
CARD8 crt07, crt09;
PutReg(CRTX(pATI->CPIO_VGABase), 0x11U, 0x20U);
/* Make CRTC[16-17] readable */
PutReg(CRTX(pATI->CPIO_VGABase), 0x03U, tmp | 0x80U);
/* Make vertical synch pulse as wide as possible */
crt07 = GetReg(CRTX(pATI->CPIO_VGABase), 0x07U);
crt09 = GetReg(CRTX(pATI->CPIO_VGABase), 0x09U);
VBlankStart = (((crt09 & 0x20U) << 4) |
((crt07 & 0x08U) << 5) |
GetReg(CRTX(pATI->CPIO_VGABase), 0x15U)) + 1;
VBlankEnd = (VBlankStart & 0x0300U) |
GetReg(CRTX(pATI->CPIO_VGABase), 0x16U);
if (VBlankEnd <= VBlankStart)
VBlankEnd += 0x0100U;
VSyncEnd = (((crt07 & 0x80U) << 2) | ((crt07 & 0x04U) << 6) |
GetReg(CRTX(pATI->CPIO_VGABase), 0x10U)) + 0x0FU;
if (VSyncEnd >= VBlankEnd)
VSyncEnd = VBlankEnd - 1;
pATI->LockData.shadow_crt11 = (VSyncEnd & 0x0FU) | 0x20U;
PutReg(CRTX(pATI->CPIO_VGABase), 0x11U,
pATI->LockData.shadow_crt11);
pATI->LockData.shadow_crt11 |= 0x80U;
}
/* Restore selection */
if (pATI->Chip == ATI_CHIP_264LT)
{
outr(LCD_GEN_CTRL, saved_lcd_gen_ctrl);
}
else /* if ((pATI->Chip == ATI_CHIP_264LTPRO) ||
(pATI->Chip == ATI_CHIP_264XL) ||
(pATI->Chip == ATI_CHIP_MOBILITY)) */
{
ATIMach64PutLCDReg(LCD_GEN_CNTL, saved_lcd_gen_ctrl);
/* Restore LCD index */
out8(LCD_INDEX, GetByte(pATI->LockData.lcd_index, 0));
}
}
}
#endif /* AVOID_CPIO */
}
static void rtc_write (short reg, uchar val)
{
out8(RTC_PORT_ADDR0, reg & 0xFF);
out8(RTC_PORT_ADDR1, (reg>>8) & 0xFF);
out8(RTC_PORT_DATA, val);
}
void sendEOI()
{
out8(MasterCmdStsR, EOI);
}
unsigned char get_board_revcfg (void)
{
out8 (PER_BOARD_ADDR, 0);
return (in8 (PER_BOARD_ADDR));
}
/** Register a new PCI ATA channel.
* @param pci_device PCI device the channel is on.
* @param idx Channel index.
* @param ctrl_base Control registers base address.
* @param cmd_base Command registers base address.
* @param bm_base Bus master base address.
* @param irq IRQ number.
* @return Pointer to ATA channel structure if present. */
static ata_channel_t *pci_ata_channel_add(pci_device_t *pci_device, int idx, uint32_t ctrl_base,
uint32_t cmd_base, uint32_t bm_base, uint32_t irq) {
uint16_t pci_cmd_old, pci_cmd_new;
pci_ata_channel_t *channel;
bool dma = true;
status_t ret;
/* Configure the PCI device appropriately. */
pci_cmd_old = pci_cmd_new = pci_config_read16(pci_device, PCI_CONFIG_COMMAND);
pci_cmd_new &= ~PCI_COMMAND_INT_DISABLE;
pci_cmd_new |= (PCI_COMMAND_IO | PCI_COMMAND_BUS_MASTER);
if(pci_cmd_new != pci_cmd_old) {
pci_config_write16(pci_device, PCI_CONFIG_COMMAND, pci_cmd_new);
kprintf(LOG_DEBUG, "ata: reconfigured PCI device %d:%02x.%d (old: 0x%04x, new: 0x%04x)\n",
pci_device->bus, pci_device->device, pci_device->function,
pci_cmd_old, pci_cmd_new);
}
/* Check presence by writing a value to the low LBA port on the channel,
* then reading it back. If the value is the same, it is present. */
out8(cmd_base + ATA_CMD_REG_LBA_LOW, 0xAB);
if(in8(cmd_base + ATA_CMD_REG_LBA_LOW) != 0xAB) {
if(pci_cmd_new != pci_cmd_old) {
pci_config_write16(pci_device, PCI_CONFIG_COMMAND, pci_cmd_old);
}
return NULL;
}
/* Allocate our information structure. */
channel = kmalloc(sizeof(*channel), MM_WAIT);
channel->channel = NULL;
channel->pci_device = pci_device;
channel->ctrl_base = ctrl_base;
channel->cmd_base = cmd_base;
channel->bus_master_base = bm_base + (idx * 8);
channel->irq = irq;
channel->prdt = NULL;
/* If the bus master is in simplex mode, disable DMA on the second
* channel. According to the Haiku code, Intel controllers use this for
* something other than simplex mode. */
if(pci_device->vendor_id != 0x8086) {
if(in8(bm_base + PCI_ATA_BM_REG_STATUS) & PCI_ATA_BM_STATUS_SIMPLEX && idx > 1) {
dma = false;
}
}
/* Allocate a PRDT if necessary. */
if(dma) {
phys_alloc(PRDT_SIZE, 0, 0, 0, (phys_ptr_t)0x100000000, MM_WAIT, &channel->prdt_phys);
channel->prdt = phys_map(channel->prdt_phys, PRDT_SIZE, MM_WAIT);
}
/* Register the IRQ handler. */
ret = irq_register(channel->irq, pci_ata_irq_handler, NULL, channel);
if(ret != STATUS_SUCCESS) {
kprintf(LOG_WARN, "ata: failed to register PCI ATA IRQ handler %u\n", channel->irq);
if(dma) {
phys_unmap(channel->prdt, PRDT_SIZE, true);
phys_free(channel->prdt_phys, PRDT_SIZE);
}
kfree(channel);
return NULL;
}
/* Try to register the ATA channel. */
channel->channel = ata_sff_channel_add(pci_device->node, idx, &pci_ata_channel_ops, channel,
dma, PRDT_ENTRIES, (phys_ptr_t)0x100000000);
if(!channel->channel) {
irq_unregister(channel->irq, pci_ata_irq_handler, NULL, channel);
if(dma) {
phys_unmap(channel->prdt, PRDT_SIZE, true);
phys_free(channel->prdt_phys, PRDT_SIZE);
}
kfree(channel);
return NULL;
}
return channel->channel;
}
void write_ec_data(ec_dev_t* dev, uint8_t data)
{
out8(EC_DATA, data);
}
/** Write to a control register.
* @param channel Channel to read from.
* @param reg Register to write to.
* @param val Value to write. */
static void pci_ata_channel_write_ctrl(ata_channel_t *channel, int reg, uint8_t val) {
pci_ata_channel_t *data = channel->data;
out8(data->ctrl_base + reg, val);
}
void fpga_init(void)
{
unsigned long group;
unsigned long sdr0_pfc0;
unsigned long sdr0_pfc1;
unsigned long sdr0_cust0;
unsigned long pvr;
mfsdr (SDR0_PFC0, sdr0_pfc0);
mfsdr (SDR0_PFC1, sdr0_pfc1);
group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
pvr = get_pvr ();
sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE;
if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) {
sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE;
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
FPGA_REG2_EXT_INTFACE_ENABLE);
mtsdr (SDR0_PFC0, sdr0_pfc0);
mtsdr (SDR0_PFC1, sdr0_pfc1);
} else {
sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE;
switch (group)
{
case 0:
case 1:
case 2:
/* CPU trace A */
out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
FPGA_REG2_EXT_INTFACE_ENABLE);
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
mtsdr (SDR0_PFC0, sdr0_pfc0);
mtsdr (SDR0_PFC1, sdr0_pfc1);
break;
case 3:
case 4:
case 5:
case 6:
/* CPU trace B - Over EBMI */
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE;
mtsdr (SDR0_PFC0, sdr0_pfc0);
mtsdr (SDR0_PFC1, sdr0_pfc1);
out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
FPGA_REG2_EXT_INTFACE_DISABLE);
break;
}
}
/* Initialize the ethernet specific functions in the fpga */
mfsdr(SDR0_PFC1, sdr0_pfc1);
mfsdr(SDR0_CUST0, sdr0_cust0);
if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) ||
(SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
{
if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
{
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
FPGA_REG3_ENET_GROUP7);
}
else
{
if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII)
{
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
FPGA_REG3_ENET_GROUP7);
}
else
{
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
FPGA_REG3_ENET_GROUP8);
}
}
}
else
{
if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
{
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
}
else
{
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
}
}
out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 |
FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 |
FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS);
/* reset the gigabyte phy if necessary */
if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3)
{
if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
{
out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE);
udelay(10000);
out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE);
}
else
{
out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE);
udelay(10000);
out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE);
}
}
/*
* new Ocotea with Rev. F (pass 3) chips has SMII PHY reset
*/
if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) {
out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE);
udelay(10000);
out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_SMII_RESET_DISABLE);
}
/* Turn off the LED's */
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) |
FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB |
FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB);
return;
}
uint32_t pci_write_config8(uint32_t bus, uint32_t dev_fn,
uint32_t where, uint8_t value) {
out32(PCI_CONFIG_CMD(bus, dev_fn, where), PCI_CONFIG_ADDRESS);
out8(value, PCI_CONFIG_DATA + (where & 3));
return PCIUTILS_SUCCESS;
}
