示例#1
0
static void lpc_init(struct device *dev)
{
	printk(BIOS_DEBUG, "pch: lpc_init\n");

	/* Set the value for PCI command register. */
	pci_write_config16(dev, PCI_COMMAND, 0x000f);

	/* IO APIC initialization. */
	pch_enable_ioapic(dev);

	pch_enable_serial_irqs(dev);

	/* Setup the PIRQ. */
	pch_pirq_init(dev);

	/* Setup power options. */
	pch_power_options(dev);

	/* Initialize power management */
	switch (pch_silicon_type()) {
	case PCH_TYPE_CPT: /* CougarPoint */
		cpt_pm_init(dev);
		break;
	case PCH_TYPE_PPT: /* PantherPoint */
		ppt_pm_init(dev);
		break;
	default:
		printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device);
	}

	/* Set the state of the GPIO lines. */
	//gpio_init(dev);

	/* Initialize the real time clock. */
	pch_rtc_init(dev);

	/* Initialize ISA DMA. */
	isa_dma_init();

	/* Initialize the High Precision Event Timers, if present. */
	enable_hpet();

	/* Initialize Clock Gating */
	enable_clock_gating(dev);

	setup_i8259();

	/* The OS should do this? */
	/* Interrupt 9 should be level triggered (SCI) */
	i8259_configure_irq_trigger(9, 1);

	pch_disable_smm_only_flashing(dev);

#if CONFIG_HAVE_SMI_HANDLER
	pch_lock_smm(dev);
#endif

	pch_fixups(dev);
}
示例#2
0
static int lpc_init_extra(struct udevice *dev)
{
	struct udevice *pch = dev->parent;
	const void *blob = gd->fdt_blob;
	int node;

	debug("pch: lpc_init\n");
	dm_pci_write_bar32(pch, 0, 0);
	dm_pci_write_bar32(pch, 1, 0xff800000);
	dm_pci_write_bar32(pch, 2, 0xfec00000);
	dm_pci_write_bar32(pch, 3, 0x800);
	dm_pci_write_bar32(pch, 4, 0x900);

	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
	if (node < 0)
		return -ENOENT;

	/* Set the value for PCI command register. */
	dm_pci_write_config16(pch, PCI_COMMAND, 0x000f);

	/* IO APIC initialization. */
	pch_enable_apic(pch);

	pch_enable_serial_irqs(pch);

	/* Setup the PIRQ. */
	pch_pirq_init(pch);

	/* Setup power options. */
	pch_power_options(pch);

	/* Initialize power management */
	switch (pch_silicon_type(pch)) {
	case PCH_TYPE_CPT: /* CougarPoint */
		cpt_pm_init(pch);
		break;
	case PCH_TYPE_PPT: /* PantherPoint */
		ppt_pm_init(pch);
		break;
	default:
		printf("Unknown Chipset: %s\n", pch->name);
		return -ENOSYS;
	}

	/* Initialize the real time clock. */
	pch_rtc_init(pch);

	/* Initialize the High Precision Event Timers, if present. */
	enable_hpet();

	/* Initialize Clock Gating */
	enable_clock_gating(pch);

	pch_disable_smm_only_flashing(pch);

	pch_fixups(pch);

	return 0;
}
示例#3
0
int lpc_init(struct pci_controller *hose, pci_dev_t dev)
{
	const void *blob = gd->fdt_blob;
	int node;

	debug("pch: lpc_init\n");
	pci_write_bar32(hose, dev, 0, 0);
	pci_write_bar32(hose, dev, 1, 0xff800000);
	pci_write_bar32(hose, dev, 2, 0xfec00000);
	pci_write_bar32(hose, dev, 3, 0x800);
	pci_write_bar32(hose, dev, 4, 0x900);

	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
	if (node < 0)
		return -ENOENT;

	/* Set the value for PCI command register. */
	pci_write_config16(dev, PCI_COMMAND, 0x000f);

	/* IO APIC initialization. */
	pch_enable_apic(dev);

	pch_enable_serial_irqs(dev);

	/* Setup the PIRQ. */
	pch_pirq_init(blob, node, dev);

	/* Setup power options. */
	pch_power_options(blob, node, dev);

	/* Initialize power management */
	switch (pch_silicon_type()) {
	case PCH_TYPE_CPT: /* CougarPoint */
		cpt_pm_init(dev);
		break;
	case PCH_TYPE_PPT: /* PantherPoint */
		ppt_pm_init(dev);
		break;
	default:
		printf("Unknown Chipset: %#02x.%dx\n", PCI_DEV(dev),
		       PCI_FUNC(dev));
		return -ENOSYS;
	}

	/* Initialize the real time clock. */
	pch_rtc_init(dev);

	/* Initialize the High Precision Event Timers, if present. */
	enable_hpet();

	/* Initialize Clock Gating */
	enable_clock_gating(dev);

	pch_disable_smm_only_flashing(dev);

#if CONFIG_HAVE_SMI_HANDLER
	pch_lock_smm(dev);
#endif

	pch_fixups(dev);

	return 0;
}