static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "pch: lpc_init\n"); /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); /* IO APIC initialization. */ pch_enable_apic(dev); pch_enable_serial_irqs(dev); /* Setup the PIRQ. */ pch_pirq_init(dev); /* Setup power options. */ pch_power_options(dev); /* Initialize power management */ switch (pch_silicon_type()) { case PCH_TYPE_CPT: /* CougarPoint */ cpt_pm_init(dev); break; case PCH_TYPE_PPT: /* PantherPoint */ ppt_pm_init(dev); break; default: printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device); } /* Set the state of the GPIO lines. */ //gpio_init(dev); /* Initialize the real time clock. */ pch_rtc_init(dev); /* Initialize ISA DMA. */ isa_dma_init(); /* Initialize the High Precision Event Timers, if present. */ enable_hpet(); setup_i8259(); /* The OS should do this? */ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); pch_disable_smm_only_flashing(dev); pch_set_acpi_mode(); pch_fixups(dev); }
static void pmc_init(struct device *dev) { config_t *config = dev->chip_info; pch_rtc_init(); /* Initialize power management */ pch_power_options(); reg_script_run_on_dev(dev, pch_pmc_misc_init_script); pch_set_acpi_mode(); config_deep_s3(config->deep_s3_enable); config_deep_s5(config->deep_s5_enable); config_deep_sx(config->deep_sx_config); }
static void pmc_init(struct device *dev) { printk(BIOS_DEBUG, "pch: pmc_init\n"); /* Get the base address */ acpi_base = pci_read_config16(dev, PMC_ACPI_BASE) & MASK_PMC_ACPI_BASE; pwrm_base = pci_read_config32(dev, PMC_PWRM_BASE) & MASK_PMC_PWRM_BASE; /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); /* Setup power options. */ pch_power_options(dev); /* Configure ACPI mode. */ pch_set_acpi_mode(); }
static void pmc_init(struct device *dev) { config_t *config = dev->chip_info; pch_rtc_init(); /* Initialize power management */ pch_power_options(); /* Note that certain bits may be cleared from running script as * certain bit fields are write 1 to clear. */ reg_script_run_on_dev(dev, pch_pmc_misc_init_script); pch_set_acpi_mode(); config_deep_s3(config->deep_s3_enable); config_deep_s5(config->deep_s5_enable); config_deep_sx(config->deep_sx_config); /* Clear registers that contain write-1-to-clear bits. */ reg_script_run_on_dev(dev, pmc_write1_to_clear_script); }