static void intel_8xx_tlbflush(void *mem)
{
u32_t temp;
temp = pciReadLong(bridge->PciTag, INTEL_AGPCTRL);
pciWriteLong(bridge->PciTag, INTEL_AGPCTRL, temp & ~(1 << 7));
temp = pciReadLong(bridge->PciTag, INTEL_AGPCTRL);
pciWriteLong(bridge->PciTag, INTEL_AGPCTRL, temp | (1 << 7));
}
_X_EXPORT void
pciWriteWord(PCITAG tag, int offset, CARD16 val)
{
CARD32 tmp;
int aligned_offset = offset & ~3;
int shift = (offset & 3) * 8;
int bus = PCI_BUS_FROM_TAG(tag);
if (shift != 0 && shift != 16)
FatalError("pciWriteWord: Alignment Error: Cannot read 16 bits "
"from offset %d\n", offset);
pciInit();
if ((bus >= 0) && (bus < pciNumBuses) && pciBusInfo[bus] &&
pciBusInfo[bus]->funcs->pciWriteWord) {
(*pciBusInfo[bus]->funcs->pciWriteWord)(tag, offset, val);
} else {
tmp = pciReadLong(tag, aligned_offset);
tmp &= ~(0xffffL << shift);
tmp |= (((CARD32)val) << shift);
pciWriteLong(tag, aligned_offset, tmp);
}
}
static int intel_845_configure()
{
u32_t temp;
u8_t temp2;
aper_size_t *current_size;
current_size = bridge->current_size;
/* aperture size */
pciWriteByte(bridge->PciTag, INTEL_APSIZE, current_size->size_value);
dbgprintf("INTEL_APSIZE %d\n", current_size->size_value );
if (bridge->apbase_config != 0)
{
pciWriteLong(bridge->PciTag, AGP_APBASE, bridge->apbase_config);
}
else
{
/* address to map to */
temp = pciReadLong(bridge->PciTag, AGP_APBASE);
bridge->gart_addr = (temp & PCI_MAP_MEMORY_ADDRESS_MASK);
bridge->apbase_config = temp;
}
dbgprintf("AGP_APBASE %x\n", temp );
/* attbase - aperture base */
pciWriteLong(bridge->PciTag, INTEL_ATTBASE, bridge->gatt_dma);
/* agpctrl */
pciWriteLong(bridge->PciTag, INTEL_AGPCTRL, 0x0000);
/* agpm */
temp2 = pciReadByte(bridge->PciTag, INTEL_I845_AGPM);
pciWriteByte(bridge->PciTag, INTEL_I845_AGPM, temp2 | (1 << 1));
/* clear any possible error conditions */
pciWriteWord(bridge->PciTag, INTEL_I845_ERRSTS, 0x001c);
return 0;
}
void agp_generic_enable(u32_t requested_mode)
{
u32_t bridge_agpstat, temp;
get_agp_version(bridge);
dbgprintf("Found an AGP %d.%d compliant device.\n",
bridge->major_version, bridge->minor_version);
bridge_agpstat = pciReadLong(bridge->PciTag,
bridge->capndx + PCI_AGP_STATUS);
bridge_agpstat = agp_collect_device_status(bridge, requested_mode, bridge_agpstat);
if (bridge_agpstat == 0)
/* Something bad happened. FIXME: Return error code? */
return;
bridge_agpstat |= AGPSTAT_AGP_ENABLE;
/* Do AGP version specific frobbing. */
if (bridge->major_version >= 3)
{
if (bridge->mode & AGPSTAT_MODE_3_0)
{
/* If we have 3.5, we can do the isoch stuff. */
if (bridge->minor_version >= 5)
agp_3_5_enable(bridge);
agp_device_command(bridge_agpstat, TRUE);
return;
}
else
{
/* Disable calibration cycle in RX91<1> when not in AGP3.0 mode of operation.*/
bridge_agpstat &= ~(7<<10) ;
temp = pciReadLong(bridge->PciTag, bridge->capndx+AGPCTRL);
temp |= (1<<9);
pciWriteLong(bridge->PciTag, bridge->capndx+AGPCTRL, temp);
dbgprintf("Device is in legacy mode,"
" falling back to 2.x\n");
}
}
/* AGP v<3 */
agp_device_command(bridge_agpstat, FALSE);
}
void agp_device_command(u32_t bridge_agpstat, int agp_v3)
{
PCITAG device = 0;
int mode;
mode = bridge_agpstat & 0x7;
if (agp_v3)
mode *= 4;
for_each_pci_dev(device)
{
int agp = pci_find_capability(device, PCI_CAP_ID_AGP);
if (!agp)
continue;
dbgprintf("Putting AGP V%d device at into %dx mode\n",
agp_v3 ? 3 : 2, mode);
pciWriteLong(device, agp + PCI_AGP_COMMAND, bridge_agpstat);
}
}
_X_EXPORT void
pciWriteByte(PCITAG tag, int offset, CARD8 val)
{
CARD32 tmp;
int aligned_offset = offset & ~3;
int shift = (offset & 3) *8 ;
int bus = PCI_BUS_FROM_TAG(tag);
pciInit();
if ((bus >= 0) && (bus < pciNumBuses) && pciBusInfo[bus] &&
pciBusInfo[bus]->funcs->pciWriteByte) {
(*pciBusInfo[bus]->funcs->pciWriteByte)(tag, offset, val);
} else {
tmp = pciReadLong(tag, aligned_offset);
tmp &= ~(0xffL << shift);
tmp |= (((CARD32)val) << shift);
pciWriteLong(tag, aligned_offset, tmp);
}
}
int
pciGetBaseSize(PCITAG tag, int index, Bool destructive, Bool *min)
{
int offset;
CARD32 addr1;
CARD32 addr2;
CARD32 mask1;
CARD32 mask2;
int bits = 0;
/*
* Eventually a function for this should be added to pciBusFuncs_t, but for
* now we'll just use a simple method based on the alignment of the already
* allocated address.
*/
/*
* silently ignore bogus index values. Valid values are 0-6. 0-5 are
* the 6 base address registers, and 6 is the ROM base address register.
*/
if (index < 0 || index > 6)
return 0;
pciInit();
if (xf86GetPciSizeFromOS(tag, index, &bits)) {
if (min)
*min = TRUE;
return bits;
}
if (min)
*min = destructive;
/* Get the PCI offset */
if (index == 6)
offset = PCI_MAP_ROM_REG;
else
offset = PCI_MAP_REG_START + (index << 2);
addr1 = pciReadLong(tag, offset);
/*
* Check if this is the second part of a 64 bit address.
* XXX need to check how endianness affects 64 bit addresses.
*/
if (index > 0 && index < 6) {
addr2 = pciReadLong(tag, offset - 4);
if (PCI_MAP_IS_MEM(addr2) && PCI_MAP_IS64BITMEM(addr2))
return 0;
}
if (destructive) {
pciWriteLong(tag, offset, 0xffffffff);
mask1 = pciReadLong(tag, offset);
pciWriteLong(tag, offset, addr1);
} else {
mask1 = addr1;
}
/* Check if this is the first part of a 64 bit address. */
if (index < 5 && PCI_MAP_IS_MEM(mask1) && PCI_MAP_IS64BITMEM(mask1)) {
if (PCIGETMEMORY(mask1) == 0) {
addr2 = pciReadLong(tag, offset + 4);
if (destructive) {
pciWriteLong(tag, offset + 4, 0xffffffff);
mask2 = pciReadLong(tag, offset + 4);
pciWriteLong(tag, offset + 4, addr2);
} else {
mask2 = addr2;
}
if (mask2 == 0)
return 0;
bits = 32;
while ((mask2 & 1) == 0) {
bits++;
mask2 >>= 1;
}
if (bits > 32)
return bits;
}
}
