int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res) { int ret; void *sysdata; struct pci_bus *bus; if (!pcie || !pcie->dev || !pcie->base) return -EINVAL; ret = phy_init(pcie->phy); if (ret) { dev_err(pcie->dev, "unable to initialize PCIe PHY\n"); return ret; } ret = phy_power_on(pcie->phy); if (ret) { dev_err(pcie->dev, "unable to power on PCIe PHY\n"); goto err_exit_phy; } iproc_pcie_reset(pcie); #ifdef CONFIG_ARM pcie->sysdata.private_data = pcie; sysdata = &pcie->sysdata; #else sysdata = pcie; #endif bus = pci_create_root_bus(pcie->dev, 0, &iproc_pcie_ops, sysdata, res); if (!bus) { dev_err(pcie->dev, "unable to create PCI root bus\n"); ret = -ENOMEM; goto err_power_off_phy; } pcie->root_bus = bus; ret = iproc_pcie_check_link(pcie, bus); if (ret) { dev_err(pcie->dev, "no PCIe EP device detected\n"); goto err_rm_root_bus; } iproc_pcie_enable(pcie); pci_scan_child_bus(bus); pci_assign_unassigned_bus_resources(bus); #ifdef CONFIG_ARM pci_fixup_irqs(pci_common_swizzle, pcie->map_irq); #endif pci_bus_add_devices(bus); return 0; err_rm_root_bus: pci_stop_root_bus(bus); pci_remove_root_bus(bus); err_power_off_phy: phy_power_off(pcie->phy); err_exit_phy: phy_exit(pcie->phy); return ret; }
static int versatile_pci_probe(struct platform_device *pdev) { struct resource *res; int ret, i, myslot = -1; u32 val; void __iomem *local_pci_cfg_base; struct pci_bus *bus; LIST_HEAD(pci_res); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); versatile_pci_base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(versatile_pci_base)) return PTR_ERR(versatile_pci_base); res = platform_get_resource(pdev, IORESOURCE_MEM, 1); versatile_cfg_base[0] = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(versatile_cfg_base[0])) return PTR_ERR(versatile_cfg_base[0]); res = platform_get_resource(pdev, IORESOURCE_MEM, 2); versatile_cfg_base[1] = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(versatile_cfg_base[1])) return PTR_ERR(versatile_cfg_base[1]); ret = versatile_pci_parse_request_of_pci_ranges(&pdev->dev, &pci_res); if (ret) return ret; /* * We need to discover the PCI core first to configure itself * before the main PCI probing is performed */ for (i = 0; i < 32; i++) { if ((readl(versatile_cfg_base[0] + (i << 11) + PCI_VENDOR_ID) == VP_PCI_DEVICE_ID) && (readl(versatile_cfg_base[0] + (i << 11) + PCI_CLASS_REVISION) == VP_PCI_CLASS_ID)) { myslot = i; break; } } if (myslot == -1) { dev_err(&pdev->dev, "Cannot find PCI core!\n"); return -EIO; } /* * Do not to map Versatile FPGA PCI device into memory space */ pci_slot_ignore |= (1 << myslot); dev_info(&pdev->dev, "PCI core found (slot %d)\n", myslot); writel(myslot, PCI_SELFID); local_pci_cfg_base = versatile_cfg_base[1] + (myslot << 11); val = readl(local_pci_cfg_base + PCI_COMMAND); val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE; writel(val, local_pci_cfg_base + PCI_COMMAND); /* * Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM */ writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0); writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1); writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2); /* * For many years the kernel and QEMU were symbiotically buggy * in that they both assumed the same broken IRQ mapping. * QEMU therefore attempts to auto-detect old broken kernels * so that they still work on newer QEMU as they did on old * QEMU. Since we now use the correct (ie matching-hardware) * IRQ mapping we write a definitely different value to a * PCI_INTERRUPT_LINE register to tell QEMU that we expect * real hardware behaviour and it need not be backwards * compatible for us. This write is harmless on real hardware. */ writel(0, versatile_cfg_base[0] + PCI_INTERRUPT_LINE); pci_add_flags(PCI_ENABLE_PROC_DOMAINS); pci_add_flags(PCI_REASSIGN_ALL_BUS | PCI_REASSIGN_ALL_RSRC); bus = pci_scan_root_bus(&pdev->dev, 0, &pci_versatile_ops, NULL, &pci_res); if (!bus) return -ENOMEM; pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); pci_assign_unassigned_bus_resources(bus); pci_bus_add_devices(bus); return 0; }
int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res) { struct device *dev; int ret; void *sysdata; struct pci_bus *bus; dev = pcie->dev; ret = devm_request_pci_bus_resources(dev, res); if (ret) return ret; ret = phy_init(pcie->phy); if (ret) { dev_err(dev, "unable to initialize PCIe PHY\n"); return ret; } ret = phy_power_on(pcie->phy); if (ret) { dev_err(dev, "unable to power on PCIe PHY\n"); goto err_exit_phy; } switch (pcie->type) { case IPROC_PCIE_PAXB: pcie->reg_offsets = iproc_pcie_reg_paxb; break; case IPROC_PCIE_PAXC: pcie->reg_offsets = iproc_pcie_reg_paxc; break; default: dev_err(dev, "incompatible iProc PCIe interface\n"); ret = -EINVAL; goto err_power_off_phy; } iproc_pcie_reset(pcie); if (pcie->need_ob_cfg) { ret = iproc_pcie_map_ranges(pcie, res); if (ret) { dev_err(dev, "map failed\n"); goto err_power_off_phy; } } #ifdef CONFIG_ARM pcie->sysdata.private_data = pcie; sysdata = &pcie->sysdata; #else sysdata = pcie; #endif bus = pci_create_root_bus(dev, 0, &iproc_pcie_ops, sysdata, res); if (!bus) { dev_err(dev, "unable to create PCI root bus\n"); ret = -ENOMEM; goto err_power_off_phy; } pcie->root_bus = bus; ret = iproc_pcie_check_link(pcie, bus); if (ret) { dev_err(dev, "no PCIe EP device detected\n"); goto err_rm_root_bus; } iproc_pcie_enable(pcie); if (IS_ENABLED(CONFIG_PCI_MSI)) if (iproc_pcie_msi_enable(pcie)) dev_info(dev, "not using iProc MSI\n"); pci_scan_child_bus(bus); pci_assign_unassigned_bus_resources(bus); pci_fixup_irqs(pci_common_swizzle, pcie->map_irq); pci_bus_add_devices(bus); return 0; err_rm_root_bus: pci_stop_root_bus(bus); pci_remove_root_bus(bus); err_power_off_phy: phy_power_off(pcie->phy); err_exit_phy: phy_exit(pcie->phy); return ret; }