/* * pcie_portdrv_probe - Probe PCI-Express port devices * @dev: PCI-Express port device being probed * * If detected invokes the pcie_port_device_register() method for * this port device. * */ static int __devinit pcie_portdrv_probe (struct pci_dev *dev, const struct pci_device_id *id ) { int status; status = pcie_port_device_probe(dev); if (status) return status; if (pci_enable_device(dev) < 0) return -ENODEV; pci_set_master(dev); if (!dev->irq) { printk(KERN_WARNING "%s->Dev[%04x:%04x] has invalid IRQ. Check vendor BIOS\n", __FUNCTION__, dev->device, dev->vendor); } if (pcie_port_device_register(dev)) { pci_disable_device(dev); return -ENOMEM; } pcie_portdrv_save_config(dev); pci_enable_pcie_error_reporting(dev); return 0; }
/** * adf_enable_aer() - Enable Advance Error Reporting for acceleration device * @accel_dev: Pointer to acceleration device. * @adf: PCI device driver owning the given acceleration device. * * Function enables PCI Advance Error Reporting for the * QAT acceleration device accel_dev. * To be used by QAT device specific drivers. * * Return: 0 on success, error code othewise. */ int adf_enable_aer(struct adf_accel_dev *accel_dev, struct pci_driver *adf) { struct pci_dev *pdev = accel_to_pci_dev(accel_dev); adf->err_handler = &adf_err_handler; pci_enable_pcie_error_reporting(pdev); return 0; }
static pci_ers_result_t pcie_portdrv_slot_reset(struct pci_dev *dev) { pci_ers_result_t status; /* If fatal, restore cfg space for possible link reset at upstream */ if (dev->error_state == pci_channel_io_frozen) { pcie_portdrv_restore_config(dev); pci_enable_pcie_error_reporting(dev); } device_for_each_child(&dev->dev, &status, slot_reset_iter); return status; }
static pci_ers_result_t pcie_portdrv_slot_reset(struct pci_dev *dev) { pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; /* If fatal, restore cfg space for possible link reset at upstream */ if (dev->error_state == pci_channel_io_frozen) { dev->state_saved = true; pci_restore_state(dev); pcie_portdrv_restore_config(dev); pci_enable_pcie_error_reporting(dev); } /* get true return value from &status */ device_for_each_child(&dev->dev, &status, slot_reset_iter); return status; }
static int set_device_error_reporting(struct pci_dev *dev, void *data) { bool enable = *((bool *)data); if ((dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) || (dev->pcie_type == PCI_EXP_TYPE_UPSTREAM) || (dev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)) { if (enable) pci_enable_pcie_error_reporting(dev); else pci_disable_pcie_error_reporting(dev); } if (enable) pcie_set_ecrc_checking(dev); return 0; }
static int set_device_error_reporting(struct pci_dev *dev, void *data) { bool enable = *((bool *)data); if (dev->pcie_type == PCIE_RC_PORT || dev->pcie_type == PCIE_SW_UPSTREAM_PORT || dev->pcie_type == PCIE_SW_DOWNSTREAM_PORT) { if (enable) pci_enable_pcie_error_reporting(dev); else pci_disable_pcie_error_reporting(dev); } if (enable) pcie_set_ecrc_checking(dev); return 0; }
static pci_ers_result_t pcie_portdrv_slot_reset(struct pci_dev *dev) { pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; int retval; if (dev->error_state == pci_channel_io_frozen) { dev->state_saved = true; pci_restore_state(dev); pcie_portdrv_restore_config(dev); pci_enable_pcie_error_reporting(dev); } retval = device_for_each_child(&dev->dev, &status, slot_reset_iter); return status; }
/* * Do all the common PCIe setup and initialization. * devdata is not yet allocated, and is not allocated until after this * routine returns success. Therefore qib_dev_err() can't be used for error * printing. */ int qib_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent) { int ret; ret = pci_enable_device(pdev); if (ret) { /* * This can happen (in theory) iff: * We did a chip reset, and then failed to reprogram the * BAR, or the chip reset due to an internal error. We then * unloaded the driver and reloaded it. * * Both reset cases set the BAR back to initial state. For * the latter case, the AER sticky error bit at offset 0x718 * should be set, but the Linux kernel doesn't yet know * about that, it appears. If the original BAR was retained * in the kernel data structures, this may be OK. */ qib_early_err(&pdev->dev, "pci enable failed: error %d\n", -ret); goto done; } ret = pci_request_regions(pdev, QIB_DRV_NAME); if (ret) { qib_devinfo(pdev, "pci_request_regions fails: err %d\n", -ret); goto bail; } ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); if (ret) { /* * If the 64 bit setup fails, try 32 bit. Some systems * do not setup 64 bit maps on systems with 2GB or less * memory installed. */ ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); if (ret) { qib_devinfo(pdev, "Unable to set DMA mask: %d\n", ret); goto bail; } ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); } else ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); if (ret) { qib_early_err(&pdev->dev, "Unable to set DMA consistent mask: %d\n", ret); goto bail; } pci_set_master(pdev); ret = pci_enable_pcie_error_reporting(pdev); if (ret) { qib_early_err(&pdev->dev, "Unable to enable pcie error reporting: %d\n", ret); ret = 0; } goto done; bail: pci_disable_device(pdev); pci_release_regions(pdev); done: return ret; }
int qib_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent) { int ret; ret = pci_enable_device(pdev); if (ret) { /* */ qib_early_err(&pdev->dev, "pci enable failed: error %d\n", -ret); goto done; } ret = pci_request_regions(pdev, QIB_DRV_NAME); if (ret) { qib_devinfo(pdev, "pci_request_regions fails: err %d\n", -ret); goto bail; } ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); if (ret) { /* */ ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); if (ret) { qib_devinfo(pdev, "Unable to set DMA mask: %d\n", ret); goto bail; } ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); } else ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); if (ret) { qib_early_err(&pdev->dev, "Unable to set DMA consistent mask: %d\n", ret); goto bail; } pci_set_master(pdev); ret = pci_enable_pcie_error_reporting(pdev); if (ret) { qib_early_err(&pdev->dev, "Unable to enable pcie error reporting: %d\n", ret); ret = 0; } goto done; bail: pci_disable_device(pdev); pci_release_regions(pdev); done: return ret; }
/** * genwqe_pci_setup() - Allocate PCIe related resources for our card */ static int genwqe_pci_setup(struct genwqe_dev *cd) { int err; struct pci_dev *pci_dev = cd->pci_dev; err = pci_enable_device_mem(pci_dev); if (err) { dev_err(&pci_dev->dev, "err: failed to enable pci memory (err=%d)\n", err); goto err_out; } /* Reserve PCI I/O and memory resources */ err = pci_request_mem_regions(pci_dev, genwqe_driver_name); if (err) { dev_err(&pci_dev->dev, "[%s] err: request bars failed (%d)\n", __func__, err); err = -EIO; goto err_disable_device; } /* check for 64-bit DMA address supported (DAC) */ if (!pci_set_dma_mask(pci_dev, DMA_BIT_MASK(64))) { err = pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(64)); if (err) { dev_err(&pci_dev->dev, "err: DMA64 consistent mask error\n"); err = -EIO; goto out_release_resources; } /* check for 32-bit DMA address supported (SAC) */ } else if (!pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32))) { err = pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(32)); if (err) { dev_err(&pci_dev->dev, "err: DMA32 consistent mask error\n"); err = -EIO; goto out_release_resources; } } else { dev_err(&pci_dev->dev, "err: neither DMA32 nor DMA64 supported\n"); err = -EIO; goto out_release_resources; } pci_set_master(pci_dev); pci_enable_pcie_error_reporting(pci_dev); /* EEH recovery requires PCIe fundamental reset */ pci_dev->needs_freset = 1; /* request complete BAR-0 space (length = 0) */ cd->mmio_len = pci_resource_len(pci_dev, 0); cd->mmio = pci_iomap(pci_dev, 0, 0); if (cd->mmio == NULL) { dev_err(&pci_dev->dev, "[%s] err: mapping BAR0 failed\n", __func__); err = -ENOMEM; goto out_release_resources; } cd->num_vfs = pci_sriov_get_totalvfs(pci_dev); if (cd->num_vfs < 0) cd->num_vfs = 0; err = genwqe_read_ids(cd); if (err) goto out_iounmap; return 0; out_iounmap: pci_iounmap(pci_dev, cd->mmio); out_release_resources: pci_release_mem_regions(pci_dev); err_disable_device: pci_disable_device(pci_dev); err_out: return err; }
/* * Do all the common PCIe setup and initialization. * devdata is not yet allocated, and is not allocated until after this * routine returns success. Therefore qib_dev_err() can't be used for error * printing. */ int qib_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent) { int ret; ret = pci_enable_device(pdev); if (ret) { /* * This can happen (in theory) iff: * We did a chip reset, and then failed to reprogram the * BAR, or the chip reset due to an internal error. We then * unloaded the driver and reloaded it. * * Both reset cases set the BAR back to initial state. For * the latter case, the AER sticky error bit at offset 0x718 * should be set, but the Linux kernel doesn't yet know * about that, it appears. If the original BAR was retained * in the kernel data structures, this may be OK. */ qib_early_err(&pdev->dev, "pci enable failed: error %d\n", -ret); goto done; } ret = pci_request_regions(pdev, QIB_DRV_NAME); if (ret) { qib_devinfo(pdev, "pci_request_regions fails: err %d\n", -ret); goto bail; } ret = pci_set_dma_mask(pdev, DMA_64BIT_MASK); if (ret) { /* * If the 64 bit setup fails, try 32 bit. Some systems * do not setup 64 bit maps on systems with 2GB or less * memory installed. */ ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK); if (ret) { qib_devinfo(pdev, "Unable to set DMA mask: %d\n", ret); goto bail; } qib_dbg("No 64bit DMA mask, used 32 bit mask\n"); ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); } else ret = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); if (ret) { qib_early_err(&pdev->dev, "Unable to set DMA consistent mask: %d\n", ret); goto bail; } pci_set_master(pdev); #ifdef CONFIG_PCIEAER /* enable basic AER reporting. Perhaps more later */ if (pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR)) { ret = pci_enable_pcie_error_reporting(pdev); if (ret) qib_early_err(&pdev->dev, "Unable to enable pcie error reporting" ": %d\n", ret); ret = 0; } else qib_dbg("AER capability not found! AER reports not enabled\n"); #endif goto done; bail: pci_disable_device(pdev); pci_release_regions(pdev); done: return ret; }