void intel_detect_pch(struct drm_device *dev)
{
struct drm_i915_private *dev_priv;
device_t pch;
uint32_t id;
dev_priv = dev->dev_private;
pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA);
if (pch != NULL && pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_IBX;
dev_priv->num_pch_pll = 2;
DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CPT;
dev_priv->num_pch_pll = 2;
DRM_DEBUG_KMS("Found CougarPoint PCH\n");
} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
/* PantherPoint is CPT compatible */
dev_priv->pch_type = PCH_CPT;
dev_priv->num_pch_pll = 2;
DRM_DEBUG_KMS("Found PatherPoint PCH\n");
} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_LPT;
dev_priv->num_pch_pll = 0;
DRM_DEBUG_KMS("Found LynxPoint PCH\n");
} else
DRM_DEBUG_KMS("No PCH detected\n");
KASSERT(dev_priv->num_pch_pll <= I915_NUM_PLLS,
("num_pch_pll %d\n", dev_priv->num_pch_pll));
} else
DRM_DEBUG_KMS("No Intel PCI-ISA bridge found\n");
}
static void
ns16550pci_uart_probe(cfe_driver_t *drv,
unsigned long probe_a, unsigned long probe_b,
void *probe_ptr)
{
int index;
/*
* NS16550-compatible UART on the PCI bus
* probe_a, probe_b and probe_ptr are unused.
*
* This is for generic 16550-like UARTs. We use the PCI class and
* interface codes to identify compatible hardware. We require
* 16550 or better compatibility. The 16{6,7,8,9}50 parts are
* claimed to be 16550 compatible but are as yet untested.
*/
for (index = 0; ; index++) {
pcitag_t tag;
pcireg_t cr;
phys_addr_t pa;
if (pci_find_class(PCI_CLASS_COMMUNICATIONS, index, &tag) != 0) {
break;
}
cr = pci_conf_read(tag, PCI_CLASS_REG);
if (PCI_SUBCLASS(cr) == PCI_SUBCLASS_COMMUNICATIONS_SERIAL
&& PCI_INTERFACE(cr) >= 0x02 /* 16550 .. */
&& PCI_INTERFACE(cr) <= 0x06) { /* 16950 */
if (pci_map_io(tag, PCI_MAPREG(0), PCI_MATCH_BYTES, &pa) == 0)
ns16550_uart_probe(drv, pa, 0, NULL);
}
}
}
/*
* test_find_hcd
* make call to pci_find_class with correct flags
* to attempt to find a usb hostcontroller, that
* we can later use to test hcd functions, must
* have either uchi or ohci usb options enabled
* or will not find a device
*/
static int test_find_hcd()
{
struct pci_dev *pdev =
(struct pci_dev *)kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
ltp_usb.pdev = pdev;
#if 0
/* try and get a usb hostcontroller if possible */
pdev = pci_find_class(PCI_CLASS_SERIAL_USB << 8, NULL);
if (pdev) {
printk("tusb: WOOT! Found a usb host controller!\n");
printk("tusb: Slot number: %d\n", pdev->devfn);
memcpy(ltp_usb.pdev, pdev, sizeof(struct pci_dev));
if (pdev->driver->id_table)
printk("tusb: id_table exists\n");
return 0;
} else {
printk("tusb: Failed to find host controller\n");
printk("tusb: Check kernel options enabled\n");
return 1;
}
#else
return 1;
#endif
}
/*
* Create the appropriate control structures to manage a new XHCI host
* controller.
*/
int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
struct xhci_hcor **ret_hcor)
{
struct xhci_hccr *hccr;
struct xhci_hcor *hcor;
pci_dev_t pdev;
uint32_t cmd;
int len;
pdev = pci_find_class(PCI_CLASS_SERIAL_USB_XHCI, index);
if (pdev < 0) {
printf("XHCI host controller not found\n");
return -1;
}
hccr = (struct xhci_hccr *)pci_map_bar(pdev,
PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
len = HC_LENGTH(xhci_readl(&hccr->cr_capbase));
hcor = (struct xhci_hcor *)((uint32_t)hccr + len);
debug("XHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
(uint32_t)hccr, (uint32_t)hcor, len);
*ret_hccr = hccr;
*ret_hcor = hcor;
/* enable busmaster */
pci_read_config_dword(pdev, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_MASTER;
pci_write_config_dword(pdev, PCI_COMMAND, cmd);
return 0;
}
void intel_detect_pch(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
device_t pch;
/*
* The reason to probe ISA bridge instead of Dev31:Fun0 is to
* make graphics device passthrough work easy for VMM, that only
* need to expose ISA bridge to let driver know the real hardware
* underneath. This is a requirement from virtualization team.
*/
pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA);
if (pch) {
if (pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
unsigned short id;
id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
dev_priv->pch_id = id;
if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_IBX;
dev_priv->num_pch_pll = 2;
DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
WARN_ON(!IS_GEN5(dev));
} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CPT;
dev_priv->num_pch_pll = 2;
DRM_DEBUG_KMS("Found CougarPoint PCH\n");
WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
/* PantherPoint is CPT compatible */
dev_priv->pch_type = PCH_CPT;
dev_priv->num_pch_pll = 2;
DRM_DEBUG_KMS("Found PatherPoint PCH\n");
WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_LPT;
dev_priv->num_pch_pll = 0;
DRM_DEBUG_KMS("Found LynxPoint PCH\n");
WARN_ON(!IS_HASWELL(dev));
} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_LPT;
dev_priv->num_pch_pll = 0;
DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
WARN_ON(!IS_HASWELL(dev));
}
BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
}
#if 0
pci_dev_put(pch);
#endif
}
}
static u32 probe_pci_video(void)
{
pci_dev_t devbusfn;
if ((devbusfn = pci_find_class(PCI_CLASS_VIDEO,
PCI_CLASS_VIDEO_STD,
PCI_CLASS_VIDEO_PROG_IF_VGA, 0)) != -1) {
u32 old;
u32 addr;
/* PCI video device detected */
printf("Found PCI VGA device at %02x.%02x.%x\n",
PCI_BUS(devbusfn), PCI_DEV(devbusfn), PCI_FUNC(devbusfn));
/* Enable I/O decoding as well, PCI viudeo boards
* support I/O accesses, but they provide no
* bar register for this since the ports are fixed.
*/
pci_write_config_word(devbusfn, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_MASTER);
/* Test the ROM decoder, do the device support a rom? */
pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &old);
pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, PCI_ROM_ADDRESS_MASK);
pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &addr);
pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, old);
if (!addr) {
printf("PCI VGA have no ROM?\n");
return 0;
}
/* device have a rom */
if (pci_shadow_rom(devbusfn, (void*)0xc0000)) {
printf("Shadowing of PCI VGA BIOS failed\n");
return 0;
}
/* Now enable lagacy VGA port access */
if (pci_enable_legacy_video_ports(pci_bus_to_hose(PCI_BUS(devbusfn)))) {
printf("PCI VGA enable failed\n");
return 0;
}
/* return the pci device info, that we'll need later */
return PCI_BUS(devbusfn) << 8 |
PCI_DEV(devbusfn) << 3 | (PCI_FUNC(devbusfn)&7);
}
return 0;
}
u32_t agp_collect_device_status(agp_t *bridge, u32_t requested_mode,
u32_t bridge_agpstat)
{
PCITAG vgaTag;
u32_t vga_agpstat;
int cap_ptr;
for (;;)
{
vgaTag = pci_find_class(PCI_CLASS_DISPLAY_VGA);
if (vgaTag == -1)
{
dbgprintf("Couldn't find an AGP VGA controller.\n");
return 0;
}
cap_ptr = pci_find_capability(vgaTag, PCI_CAP_ID_AGP);
if (cap_ptr)
break;
}
/*
* Ok, here we have a AGP device. Disable impossible
* settings, and adjust the readqueue to the minimum.
*/
vga_agpstat = pciReadLong(vgaTag, cap_ptr+PCI_AGP_STATUS);
/* adjust RQ depth */
bridge_agpstat = ((bridge_agpstat & ~AGPSTAT_RQ_DEPTH) |
min_t(u32_t, (requested_mode & AGPSTAT_RQ_DEPTH),
min_t(u32_t, (bridge_agpstat & AGPSTAT_RQ_DEPTH), (vga_agpstat & AGPSTAT_RQ_DEPTH))));
/* disable FW if it's not supported */
if (!((bridge_agpstat & AGPSTAT_FW) &&
(vga_agpstat & AGPSTAT_FW) &&
(requested_mode & AGPSTAT_FW)))
bridge_agpstat &= ~AGPSTAT_FW;
/* Check to see if we are operating in 3.0 mode */
if (bridge->mode & AGPSTAT_MODE_3_0)
agp_v3_parse_one(&requested_mode, &bridge_agpstat, &vga_agpstat);
else
agp_v2_parse_one(&requested_mode, &bridge_agpstat, &vga_agpstat);
return bridge_agpstat;
}
/*
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **ret_hccr, struct ehci_hcor **ret_hcor)
{
pci_dev_t pdev;
#ifdef CONFIG_PCI_EHCI_DEVICE
pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVICE);
#else
pdev = pci_find_class(PCI_CLASS_SERIAL_USB_EHCI, index);
#endif
if (pdev < 0) {
printf("EHCI host controller not found\n");
return -1;
}
ehci_pci_common_init(pdev, ret_hccr, ret_hcor);
return 0;
}
/* walk through every ethernet PCI devices to see if some of them are matched with our card list*/
int sis900_probe (struct device * net_dev)
{
int found = 0;
struct pci_dev * pci_dev = NULL;
if (!pci_present())
return -ENODEV;
while ((pci_dev = pci_find_class (PCI_CLASS_NETWORK_ETHERNET << 8, pci_dev)) != NULL) {
/* pci_dev contains all ethernet devices */
u32 pci_io_base;
struct mac_chip_info * mac;
for (mac = mac_chip_table; mac->vendor_id; mac++) {
/* try to match our card list */
if (pci_dev->vendor == mac->vendor_id &&
pci_dev->device == mac->device_id)
break;
}
if (mac->vendor_id == 0)
/* pci_dev does not match any of our cards */
continue;
/* now, pci_dev should be either 900 or 7016 */
pci_io_base = pci_dev->base_address[0] & PCI_BASE_ADDRESS_IO_MASK;
if ((mac->flags & PCI_COMMAND_IO ) &&
check_region(pci_io_base, mac->io_size))
continue;
/* setup various bits in PCI command register */
pci_set_master(pci_dev);
/* do the real low level jobs */
net_dev = mac->probe(mac, pci_dev, net_dev);
if (net_dev != NULL) {
found++;
}
net_dev = NULL;
}
return found ? 0 : -ENODEV;
}
void *video_hw_init(void)
{
GraphicDevice *gdev = &ctfb;
int bits_per_pixel;
pci_dev_t dev;
int ret;
printf("Video: ");
if (vbe_get_video_info(gdev)) {
dev = pci_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0);
if (dev == -1) {
printf("no card detected\n");
return NULL;
}
bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
ret = pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE |
PCI_ROM_ALLOW_FALLBACK);
bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
if (ret) {
printf("failed to run video BIOS: %d\n", ret);
return NULL;
}
}
if (vbe_get_video_info(gdev)) {
printf("No video mode configured\n");
return NULL;
}
bits_per_pixel = gdev->gdfBytesPP * 8;
sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY,
bits_per_pixel);
printf("%s\n", gdev->modeIdent);
debug("Frame buffer at %x\n", gdev->pciBase);
return (void *)gdev;
}
/*
Search DM910X board ,allocate space and register it
*/
int dmfe_probe(struct device *dev)
{
unsigned long pci_iobase;
u16 dm9102_count = 0;
u8 pci_irqline;
static int index = 0; /* For multiple call */
struct dmfe_board_info *db; /* Point a board information structure */
int i;
struct pci_dev *net_dev = NULL;
DMFE_DBUG(0, "dmfe_probe()", 0);
if (!pci_present())
return -ENODEV;
index = 0;
while ((net_dev = pci_find_class(PCI_CLASS_NETWORK_ETHERNET << 8, net_dev)))
{
u32 pci_id;
u32 dev_rev;
u8 pci_cmd;
index++;
if (pci_read_config_dword(net_dev, PCI_VENDOR_ID, &pci_id) != DMFE_SUCC)
continue;
if ((pci_id != PCI_DM9102_ID) && (pci_id != PCI_DM9132_ID))
continue;
/* read PCI IO base address and IRQ to check */
pci_iobase = net_dev->base_address[0];
pci_irqline = net_dev->irq;
pci_iobase &= ~0x7f; /* mask off bit0~6 */
/* Enable Master/IO access, Disable memory access */
pci_read_config_byte(net_dev, PCI_COMMAND, &pci_cmd);
pci_cmd |= PCI_COMMAND_IO + PCI_COMMAND_MASTER;
pci_cmd &= ~PCI_COMMAND_MEMORY;
pci_write_config_byte(net_dev, PCI_COMMAND, pci_cmd);
/* Set Latency Timer 80h */
pci_write_config_byte(net_dev, PCI_LATENCY_TIMER, 0x80);
/* Read Chip revesion */
pci_read_config_dword(net_dev, PCI_REVISION_ID, &dev_rev);
/* IO range check */
if (check_region(pci_iobase, CHK_IO_SIZE(pci_id, dev_rev)))
continue;
/* Interrupt check */
if (pci_irqline == 0) {
printk(KERN_ERR "dmfe: Interrupt wrong : IRQ=%d\n", pci_irqline);
continue;
}
/* Found DM9102 card and PCI resource allocated OK */
dm9102_count++; /* Found a DM9102 card */
/* Init network device */
dev = init_etherdev(dev, 0);
/* Allocated board information structure */
db = (void *) (kmalloc(sizeof(*db), GFP_KERNEL | GFP_DMA));
memset(db, 0, sizeof(*db));
dev->priv = db; /* link device and board info */
db->next_dev = dmfe_root_dev;
dmfe_root_dev = dev;
db->chip_id = pci_id; /* keep Chip vandor/Device ID */
db->ioaddr = pci_iobase;
db->chip_revesion = dev_rev;
db->net_dev = net_dev;
dev->base_addr = pci_iobase;
dev->irq = pci_irqline;
dev->open = &dmfe_open;
dev->hard_start_xmit = &dmfe_start_xmit;
dev->stop = &dmfe_stop;
dev->get_stats = &dmfe_get_stats;
dev->set_multicast_list = &dmfe_set_filter_mode;
dev->do_ioctl = &dmfe_do_ioctl;
request_region(pci_iobase, CHK_IO_SIZE(pci_id, dev_rev), dev->name);
/* read 64 word srom data */
for (i = 0; i < 64; i++)
((u16 *) db->srom)[i] = read_srom_word(pci_iobase, i);
/* Set Node address */
for (i = 0; i < 6; i++)
dev->dev_addr[i] = db->srom[20 + i];
dev = 0; /* NULL device */
}
return dm9102_count ? 0 : -ENODEV;
}
static bool radeon_atrm_get_bios(struct radeon_device *rdev)
{
int ret;
int size = 256 * 1024;
int i;
device_t dev;
ACPI_HANDLE dhandle, atrm_handle;
ACPI_STATUS status;
bool found = false;
DRM_INFO("%s: ===> Try ATRM...\n", __func__);
/* ATRM is for the discrete card only */
if (rdev->flags & RADEON_IS_IGP) {
DRM_INFO("%s: IGP card detected, skipping this method...\n",
__func__);
return false;
}
#ifdef FREEBSD_WIP
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
#endif /* FREEBSD_WIP */
if ((dev = pci_find_class(PCIC_DISPLAY, PCIS_DISPLAY_VGA)) != NULL) {
DRM_INFO("%s: pci_find_class() found: %d:%d:%d:%d, vendor=%04x, device=%04x\n",
__func__,
pci_get_domain(dev),
pci_get_bus(dev),
pci_get_slot(dev),
pci_get_function(dev),
pci_get_vendor(dev),
pci_get_device(dev));
DRM_INFO("%s: Get ACPI device handle\n", __func__);
dhandle = acpi_get_handle(dev);
#ifdef FREEBSD_WIP
if (!dhandle)
continue;
#endif /* FREEBSD_WIP */
if (!dhandle)
return false;
DRM_INFO("%s: Get ACPI handle for \"ATRM\"\n", __func__);
status = AcpiGetHandle(dhandle, "ATRM", &atrm_handle);
if (!ACPI_FAILURE(status)) {
found = true;
#ifdef FREEBSD_WIP
break;
#endif /* FREEBSD_WIP */
} else {
DRM_INFO("%s: Failed to get \"ATRM\" handle: %s\n",
__func__, AcpiFormatException(status));
}
}
if (!found)
return false;
rdev->bios = malloc(size, DRM_MEM_DRIVER, M_NOWAIT);
if (!rdev->bios) {
DRM_ERROR("Unable to allocate bios\n");
return false;
}
for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
DRM_INFO("%s: Call radeon_atrm_call()\n", __func__);
ret = radeon_atrm_call(atrm_handle,
rdev->bios,
(i * ATRM_BIOS_PAGE),
ATRM_BIOS_PAGE);
if (ret < ATRM_BIOS_PAGE)
break;
}
if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
if (i == 0) {
DRM_INFO("%s: Incorrect BIOS size\n", __func__);
} else {
DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n",
__func__, rdev->bios[0], rdev->bios[1]);
}
free(rdev->bios, DRM_MEM_DRIVER);
return false;
}
return true;
}
#else
static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
{
return false;
}
#endif
static bool ni_read_disabled_bios(struct radeon_device *rdev)
{
u32 bus_cntl;
u32 d1vga_control;
u32 d2vga_control;
u32 vga_render_control;
u32 rom_cntl;
bool r;
DRM_INFO("%s: ===> Try disabled BIOS (ni)...\n", __func__);
bus_cntl = RREG32(R600_BUS_CNTL);
d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
rom_cntl = RREG32(R600_ROM_CNTL);
/* enable the rom */
WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
/* Disable VGA mode */
WREG32(AVIVO_D1VGA_CONTROL,
(d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
AVIVO_DVGA_CONTROL_TIMING_SELECT)));
WREG32(AVIVO_D2VGA_CONTROL,
(d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
AVIVO_DVGA_CONTROL_TIMING_SELECT)));
WREG32(AVIVO_VGA_RENDER_CONTROL,
(vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
r = radeon_read_bios(rdev);
/* restore regs */
WREG32(R600_BUS_CNTL, bus_cntl);
WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
WREG32(R600_ROM_CNTL, rom_cntl);
return r;
}
void intel_detect_pch(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct device *pch = NULL;
/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
* (which really amounts to a PCH but no South Display).
*/
if (INTEL_INFO(dev)->num_pipes == 0) {
dev_priv->pch_type = PCH_NOP;
return;
}
/* XXX The ISA bridge probe causes some old Core2 machines to hang */
if (INTEL_INFO(dev)->gen < 5)
return;
/*
* The reason to probe ISA bridge instead of Dev31:Fun0 is to
* make graphics device passthrough work easy for VMM, that only
* need to expose ISA bridge to let driver know the real hardware
* underneath. This is a requirement from virtualization team.
*
* In some virtualized environments (e.g. XEN), there is irrelevant
* ISA bridge in the system. To work reliably, we should scan trhough
* all the ISA bridge devices and check for the first match, instead
* of only checking the first one.
*/
while ((pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA))) {
if (pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
unsigned short id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
dev_priv->pch_id = id;
if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_IBX;
DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
WARN_ON(!IS_GEN5(dev));
} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found CougarPoint PCH\n");
WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
/* PantherPoint is CPT compatible */
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found PantherPoint PCH\n");
WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_LPT;
DRM_DEBUG_KMS("Found LynxPoint PCH\n");
WARN_ON(!IS_HASWELL(dev));
WARN_ON(IS_ULT(dev));
} else if (IS_BROADWELL(dev)) {
dev_priv->pch_type = PCH_LPT;
dev_priv->pch_id =
INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
DRM_DEBUG_KMS("This is Broadwell, assuming "
"LynxPoint LP PCH\n");
} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_LPT;
DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
WARN_ON(!IS_HASWELL(dev));
WARN_ON(!IS_ULT(dev));
} else
continue;
break;
}
}
if (!pch)
DRM_DEBUG_KMS("No PCH found.\n");
#if 0
pci_dev_put(pch);
#endif
}
