void
nautilus_kill_arch(int mode)
{
	u32 pmuport;
	int off;

	switch (mode) {
	case LINUX_REBOOT_CMD_RESTART:
		if (! alpha_using_srm) {
			u8 t8;
			pcibios_read_config_byte(0, 0x38, 0x43, &t8);
			pcibios_write_config_byte(0, 0x38, 0x43, t8 | 0x80);
			outb(1, 0x92);
			outb(0, 0x92);
			/* NOTREACHED */
		}
		break;

	case LINUX_REBOOT_CMD_POWER_OFF:
		/* Assume M1543C */
		off = 0x2000;		/* SLP_TYPE = 0, SLP_EN = 1 */
		pcibios_read_config_dword(0, 0x88, 0x10, &pmuport);
		if (!pmuport) {
			/* M1535D/D+ */
			off = 0x3400;	/* SLP_TYPE = 5, SLP_EN = 1 */
			pcibios_read_config_dword(0, 0x88, 0xe0, &pmuport);
		}
		pmuport &= 0xfffe;
		outw(0xffff, pmuport);	/* Clear pending events. */
		outw(off, pmuport + 4);
		/* NOTREACHED */
		break;
	}
}
示例#2
0
int pcimod_read_proc(char *buf, char **start, off_t offset,
                   int len, int unused)
{
    int i, pos=0;
    int bus, fun;
    unsigned char headertype=0;
    unsigned int id;

    if (!pcibios_present())
        return sprintf(buf,"No PCI bios present\n");

    /*
     * This code is derived from "drivers/pci/pci.c". This means that
     * the GPL applies to this source file and credit is due to the
     * original authors (Drew Eckhardt, Frederic Potter, David
     * Mosberger-Tang)
     */
    for (bus=0; !bus; bus++) { /* only bus 0 :-) */
        for (fun=0; fun < 0x100 && pos < PAGE_SIZE; fun++) {
            if (!PCI_FUNC(fun)) /* first function */
                pcibios_read_config_byte(bus,fun,PCI_HEADER_TYPE,&headertype);
            else if (!(headertype&0x80))
                continue;
            pcibios_read_config_dword(bus,fun,PCI_VENDOR_ID, &id);
            if (!id || id==~0) {
                headertype=0; continue;
            }

            /* Ok, we've found a device, copy its cfg space to the buffer*/
            for (i=0; i<256; i+=4, pos+=4)
                pcibios_read_config_dword(bus,fun,i,(u32 *)(buf+pos));
        }
    }
    return pos;
}
示例#3
0
asmlinkage int
sys_pciconfig_read(unsigned long bus, unsigned long dfn,
		   unsigned long off, unsigned long len,
		   unsigned char *buf)
{
	unsigned char ubyte;
	unsigned short ushort;
	unsigned int uint;
	long err = 0;

	if (!capable(CAP_SYS_ADMIN))
		return -EPERM;
	if (!pcibios_present())
		return -ENOSYS;
	
	switch (len) {
	case 1:
		err = pcibios_read_config_byte(bus, dfn, off, &ubyte);
		put_user(ubyte, buf);
		break;
	case 2:
		err = pcibios_read_config_word(bus, dfn, off, &ushort);
		put_user(ushort, (unsigned short *)buf);
		break;
	case 4:
		err = pcibios_read_config_dword(bus, dfn, off, &uint);
		put_user(uint, (unsigned int *)buf);
		break;
	default:
		err = -EINVAL;
		break;
	}
	return err;
}
示例#4
0
static dev_node_t *pcilynx_attach(dev_locator_t *loc)
{
    u_char bus, devfn;
    dev_node_t *node;
    u_int io;
    
    if (loc->bus != LOC_PCI) 
      return NULL;
    bus = loc->b.pci.bus; 
    devfn = loc->b.pci.devfn;
    printk(KERN_INFO "pcilynx_attach(device %02x:%02x.%d)\n",
	   bus, PCI_SLOT(devfn), PCI_FUNC(devfn));

    /* A hack to work around resource allocation confusion */
    pcibios_read_config_dword(bus, devfn, PCI_BASE_ADDRESS_0, &io);
    release_region(io & PCI_BASE_ADDRESS_IO_MASK, 0x100);

    if (hpsb_register_lowlevel(get_lynx_template())) 
      {
	printk(KERN_ERR "registering failed");
	return NULL;
      } 
    else 
      {
	node = kmalloc(sizeof(dev_node_t), GFP_KERNEL);
	strcpy (node->dev_name, "pcilynx");
	node->major = PCILYNX_MAJOR;
	node->minor = 0;
	node->next = NULL;
	MOD_INC_USE_COUNT;
	return node;
      }
}
示例#5
0
void
nautilus_kill_arch(int mode)
{
	switch (mode) {
	case LINUX_REBOOT_CMD_RESTART:
		if (! alpha_using_srm) {
			u8 t8;
			pcibios_read_config_byte(0, 0x38, 0x43, &t8);
			pcibios_write_config_byte(0, 0x38, 0x43, t8 | 0x80);
			outb(1, 0x92);
			outb(0, 0x92);
			/* NOTREACHED */
		}
		break;

	case LINUX_REBOOT_CMD_POWER_OFF:
		{
			u32 pmuport;
			pcibios_read_config_dword(0, 0x88, 0x10, &pmuport);
			pmuport &= 0xfffe;
			outl(0xffff, pmuport); /* clear pending events */
			outw(0x2000, pmuport+4); /* power off */
			/* NOTREACHED */
		}
		break;
	}
}
示例#6
0
unsigned long dec21040_init(unsigned long mem_start, unsigned long mem_end)
{

    if (pcibios_present()) {
	    int pci_index;
		for (pci_index = 0; pci_index < 8; pci_index++) {
			unsigned char pci_bus, pci_device_fn, pci_irq_line;
			unsigned long pci_ioaddr;
		
			if (pcibios_find_device (DEC_VENDOR_ID, DEC_21040_ID, pci_index,
									 &pci_bus, &pci_device_fn) != 0)
				break;
			pcibios_read_config_byte(pci_bus, pci_device_fn,
									 PCI_INTERRUPT_LINE, &pci_irq_line);
			pcibios_read_config_dword(pci_bus, pci_device_fn,
									  PCI_BASE_ADDRESS_0, &pci_ioaddr);
			/* Remove I/O space marker in bit 0. */
			pci_ioaddr &= ~3;
			if (tulip_debug > 2)
				printk("Found DEC PCI Tulip at I/O %#lx, IRQ %d.\n",
					   pci_ioaddr, pci_irq_line);
			mem_start = tulip_probe1(mem_start, pci_ioaddr, pci_irq_line);
		}
	}

	return mem_start;
}
示例#7
0
/*
 * Dword read from configuration space of primary PCI bus.
 */
static unsigned int
pconfig_read(int addr)
{
    unsigned int val;

#ifdef PCI_SUPPORT_VER2
    pci_read_config_dword(safl_pdev, addr, &val);
#else
    pcibios_read_config_dword(safl_pci_bus, safl_pci_devfn, addr, &val);
#endif

    return val;
}
示例#8
0
void UxPciConfigRead(ux_diva_card_t *card, int size, int offset, void *value)
{
	switch (size)
	{
	case sizeof(byte):
		pcibios_read_config_byte(card->bus_num, card->func_num, offset, (byte *) value);
		break;
	case sizeof(word):
		pcibios_read_config_word(card->bus_num, card->func_num, offset, (word *) value);
		break;
	case sizeof(dword):
		pcibios_read_config_dword(card->bus_num, card->func_num, offset, (unsigned int *) value);
		break;
	default:
		printk(KERN_WARNING "Divas: Invalid size in UxPciConfigRead\n");
	}
}
示例#9
0
/*
 * Find the IO address of the controller, its IRQ and so forth.  Fill
 * in some basic stuff into the ctlr_info_t structure.
 */
static void cpqarray_pci_init(ctlr_info_t *c, unchar bus, unchar device_fn)
{
	ushort vendor_id, device_id, command;
	unchar cache_line_size, latency_timer;
	unchar irq, revision;
	uint addr[6];

	int i;

	(void) pcibios_read_config_word(bus, device_fn,
					PCI_VENDOR_ID, &vendor_id);
	(void) pcibios_read_config_word(bus, device_fn,
					PCI_DEVICE_ID, &device_id);
	(void) pcibios_read_config_word(bus, device_fn,
					PCI_COMMAND, &command);
	for(i=0; i<6; i++)
		(void) pcibios_read_config_dword(bus, device_fn,
				PCI_BASE_ADDRESS_0 + i*4, addr+i);

	(void) pcibios_read_config_byte(bus, device_fn,
					PCI_CLASS_REVISION,&revision);
	(void) pcibios_read_config_byte(bus, device_fn,
					PCI_INTERRUPT_LINE, &irq);
	(void) pcibios_read_config_byte(bus, device_fn,
					PCI_CACHE_LINE_SIZE, &cache_line_size);
	(void) pcibios_read_config_byte(bus, device_fn,
					PCI_LATENCY_TIMER, &latency_timer);

DBGINFO(
	printk("vendor_id = %x\n", vendor_id);
	printk("device_id = %x\n", device_id);
	printk("command = %x\n", command);
	for(i=0; i<6; i++)
		printk("addr[%d] = %x\n", i, addr[i]);
	printk("revision = %x\n", revision);
	printk("irq = %x\n", irq);
	printk("cache_line_size = %x\n", cache_line_size);
	printk("latency_timer = %x\n", latency_timer);
);
示例#10
0
__initfunc(int w83c553f_init(void))
{
    u_char bus, dev;
#if 0    
    unsigned char t8;
    unsigned short t16;
#endif    
    unsigned int t32;
    struct pci_dev *pdev;
    if ((pdev = pci_find_device(PCI_VENDOR_ID_WINBOND,
				PCI_DEVICE_ID_WINBOND_83C553, NULL))) {
	bus = pdev->bus->number;
	dev = pdev->devfn + 1;
	pcibios_read_config_dword(bus, dev, PCI_VENDOR_ID, &t32);
	if (t32 == (PCI_DEVICE_ID_WINBOND_82C105<<16) + PCI_VENDOR_ID_WINBOND) {
#if 0
	    printk("Enabling SL82C105 IDE on W83C553F\n");
	    /*
	     *  FIXME: this doesn't help :-(
	     */

	    /* I/O mapping */
	    pcibios_read_config_word(bus, dev, PCI_COMMAND, &t16);
	    t16 |= PCI_COMMAND_IO;
	    pcibios_write_config_word(bus, dev, PCI_COMMAND, t16);

	    /* Standard IDE registers */
	    pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_0,
					    0xffffffff);
	    pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_0, &t32);
	    pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_0,
					    0x000001f0 | 1);
	    pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_1,
					    0xffffffff);
	    pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_1, &t32);
	    pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_1,
					    0x000003f4 | 1);
	    pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_2,
					    0xffffffff);
	    pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_2, &t32);
	    pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_2,
					    0x00000170 | 1);
	    pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_3,
					    0xffffffff);
	    pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_3, &t32);
	    pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_3,
					    0x00000374 | 1);

	    /* IDE Bus Master Control */
	    pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_4,
					    0xffffffff);
	    pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_4, &t32);
	    pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_4,
					    0x1000 | 1);
	    pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_5,
					    0xffffffff);
	    pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_5, &t32);
	    pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_5,
					    0x1010 | 1);

	    /* IDE Interrupt */
	    pcibios_read_config_byte(bus, dev, PCI_INTERRUPT_LINE, &t8);
	    chrp_ide_irq = t8;
#endif
	    return 1;
	}
    }
    return 0;
}
示例#11
0
static int RCscan(void)
{
    int cards_found = 0;
    struct device *dev = 0;

    if (pcibios_present())
    {
        static int pci_index = 0;
        unsigned char pci_bus, pci_device_fn;
        int scan_status;
        int board_index = 0;

        for (; pci_index < 0xff; pci_index++)
        {
            unsigned char pci_irq_line;
            unsigned short pci_command, vendor, device, class;
            unsigned int pci_ioaddr;


            scan_status =
                (pcibios_find_device (RC_PCI45_VENDOR_ID,
                                      RC_PCI45_DEVICE_ID,
                                      pci_index,
                                      &pci_bus,
                                      &pci_device_fn));
#ifdef RCDEBUG
            printk("rc scan_status = 0x%X\n", scan_status);
#endif
            if (scan_status != PCIBIOS_SUCCESSFUL)
                break;
            pcibios_read_config_word(pci_bus,
                                     pci_device_fn,
                                     PCI_VENDOR_ID, &vendor);
            pcibios_read_config_word(pci_bus,
                                     pci_device_fn,
                                     PCI_DEVICE_ID, &device);
            pcibios_read_config_byte(pci_bus,
                                     pci_device_fn,
                                     PCI_INTERRUPT_LINE, &pci_irq_line);
            pcibios_read_config_dword(pci_bus,
                                      pci_device_fn,
                                      PCI_BASE_ADDRESS_0, &pci_ioaddr);
            pcibios_read_config_word(pci_bus,
                                     pci_device_fn,
                                     PCI_CLASS_DEVICE, &class);

            pci_ioaddr &= ~0xf;

#ifdef RCDEBUG
            printk("rc: Found RedCreek PCI adapter\n");
            printk("rc: pci class = 0x%x  0x%x \n", class, class>>8);
            printk("rc: pci_bus = %d,  pci_device_fn = %d\n", pci_bus, pci_device_fn);
            printk("rc: pci_irq_line = 0x%x \n", pci_irq_line);
            printk("rc: pci_ioaddr = 0x%x\n", pci_ioaddr);
#endif

#if 0
            if (check_region(pci_ioaddr, 32768))
            {
                printk("rc: check_region failed\n");
                continue;
            }
            else
            {
                printk("rc: check_region passed\n");
            }
#endif

            /*
             * Get and check the bus-master and latency values.
             * Some PCI BIOSes fail to set the master-enable bit.
             */

            pcibios_read_config_word(pci_bus,
                                     pci_device_fn,
                                     PCI_COMMAND,
                                     &pci_command);
            if ( ! (pci_command & PCI_COMMAND_MASTER)) {
                printk("rc: PCI Master Bit has not been set!\n");

                pci_command |= PCI_COMMAND_MASTER;
                pcibios_write_config_word(pci_bus,
                                          pci_device_fn,
                                          PCI_COMMAND,
                                          pci_command);
            }
            if ( ! (pci_command & PCI_COMMAND_MEMORY)) {
                /*
                 * If the BIOS did not set the memory enable bit, what else
                 * did it not initialize?  Skip this adapter.
                 */
                printk("rc: Adapter %d, PCI Memory Bit has not been set!\n",
                       cards_found);
                printk("rc: Bios problem? \n");
                continue;
            }

            dev = RCfound_device(dev, pci_ioaddr, pci_irq_line,
                                 pci_bus, pci_device_fn,
                                 board_index++, cards_found);

            if (dev) {
                dev = 0;
                cards_found++;
            }
        }
    }
    printk("rc: found %d cards \n", cards_found);
    return cards_found;
}
示例#12
0
__initfunc(int
setup_niccy(struct IsdnCard *card))
{
	struct IsdnCardState *cs = card->cs;
	char tmp[64];

	strcpy(tmp, niccy_revision);
	printk(KERN_INFO "HiSax: Niccy driver Rev. %s\n", HiSax_getrev(tmp));
	if (cs->typ != ISDN_CTYPE_NICCY)
		return (0);

	if (card->para[1]) {
		cs->hw.niccy.isac = card->para[1] + ISAC_PNP;
		cs->hw.niccy.hscx = card->para[1] + HSCX_PNP;
		cs->hw.niccy.isac_ale = card->para[2] + ISAC_PNP;
		cs->hw.niccy.hscx_ale = card->para[2] + HSCX_PNP;
		cs->hw.niccy.cfg_reg = 0;
		cs->subtyp = NICCY_PNP;
		cs->irq = card->para[0];
		if (check_region((cs->hw.niccy.isac), 2)) {
			printk(KERN_WARNING
				"HiSax: %s data port %x-%x already in use\n",
				CardType[card->typ],
				cs->hw.niccy.isac,
				cs->hw.niccy.isac + 1);
			return (0);
		} else
			request_region(cs->hw.niccy.isac, 2, "niccy data");
		if (check_region((cs->hw.niccy.isac_ale), 2)) {
			printk(KERN_WARNING
				"HiSax: %s address port %x-%x already in use\n",
				CardType[card->typ],
				cs->hw.niccy.isac_ale,
				cs->hw.niccy.isac_ale + 1);
			release_region(cs->hw.niccy.isac, 2);
			return (0);
		} else
			request_region(cs->hw.niccy.isac_ale, 2, "niccy addr");
	} else {
#if CONFIG_PCI
		u_char pci_bus, pci_device_fn, pci_irq;
		u_int pci_ioaddr;

		cs->subtyp = 0;
		for (; pci_index < 0xff; pci_index++) {
			if (pcibios_find_device(PCI_VENDOR_DR_NEUHAUS,
			   PCI_NICCY_ID, pci_index, &pci_bus, &pci_device_fn)
			   == PCIBIOS_SUCCESSFUL)
				cs->subtyp = NICCY_PCI;
			else
				break;
			/* get IRQ */
			pcibios_read_config_byte(pci_bus, pci_device_fn,
				PCI_INTERRUPT_LINE, &pci_irq);

			/* get IO pci AMCC address */
			pcibios_read_config_dword(pci_bus, pci_device_fn,
				PCI_BASE_ADDRESS_0, &pci_ioaddr);
			if (!pci_ioaddr) {
				printk(KERN_WARNING "Niccy: No IO-Adr for PCI cfg found\n");
				return(0);
			}
			cs->hw.niccy.cfg_reg = pci_ioaddr & ~3 ;
			/* get IO address */
			pcibios_read_config_dword(pci_bus, pci_device_fn,
				PCI_BASE_ADDRESS_1, &pci_ioaddr);
			if (cs->subtyp)
				break;
		}
		if (!cs->subtyp) {
			printk(KERN_WARNING "Niccy: No PCI card found\n");
			return(0);
		}
		pci_index++;
		if (!pci_irq) {
			printk(KERN_WARNING "Niccy: No IRQ for PCI card found\n");
			return(0);
		}
		if (!pci_ioaddr) {
			printk(KERN_WARNING "Niccy: No IO-Adr for PCI card found\n");
			return(0);
		}
		
		pci_ioaddr &= ~3; /* remove io/mem flag */
		cs->hw.niccy.isac = pci_ioaddr + ISAC_PCI_DATA;
		cs->hw.niccy.isac_ale = pci_ioaddr + ISAC_PCI_ADDR;
		cs->hw.niccy.hscx = pci_ioaddr + HSCX_PCI_DATA;
		cs->hw.niccy.hscx_ale = pci_ioaddr + HSCX_PCI_ADDR;
		cs->irq = pci_irq;
		if (check_region((cs->hw.niccy.isac), 4)) {
			printk(KERN_WARNING
				"HiSax: %s data port %x-%x already in use\n",
				CardType[card->typ],
				cs->hw.niccy.isac,
				cs->hw.niccy.isac + 4);
			return (0);
		} else
			request_region(cs->hw.niccy.isac, 4, "niccy");
		if (check_region(cs->hw.niccy.cfg_reg, 0x80)) {
			printk(KERN_WARNING
			       "HiSax: %s pci port %x-%x already in use\n",
				CardType[card->typ],
				cs->hw.niccy.cfg_reg,
				cs->hw.niccy.cfg_reg + 0x80);
			release_region(cs->hw.niccy.isac, 4);
			return (0);
		} else {
			request_region(cs->hw.niccy.cfg_reg, 0x80, "niccy pci");
		}
#else
		printk(KERN_WARNING "Niccy: io0 0 and NO_PCI_BIOS\n");
		printk(KERN_WARNING "Niccy: unable to config NICCY PCI\n");
		return (0);
#endif /* CONFIG_PCI */
	}
	printk(KERN_INFO
		"HiSax: %s %s config irq:%d data:0x%X ale:0x%X\n",
		CardType[cs->typ], (cs->subtyp==1) ? "PnP":"PCI",
		cs->irq, cs->hw.niccy.isac, cs->hw.niccy.isac_ale);
	cs->readisac = &ReadISAC;
	cs->writeisac = &WriteISAC;
	cs->readisacfifo = &ReadISACfifo;
	cs->writeisacfifo = &WriteISACfifo;
	cs->BC_Read_Reg = &ReadHSCX;
	cs->BC_Write_Reg = &WriteHSCX;
	cs->BC_Send_Data = &hscx_fill_fifo;
	cs->cardmsg = &niccy_card_msg;
	ISACVersion(cs, "Niccy:");
	if (HscxVersion(cs, "Niccy:")) {
		printk(KERN_WARNING
		    "Niccy: wrong HSCX versions check IO address\n");
		release_io_niccy(cs);
		return (0);
	}
	return (1);
}
示例#13
0
/*****************************************************************************
 Function name	: orc_ReturnNumberOfAdapters
 Description	: This function will scan PCI bus to get all Orchid card
 Input		: None.
 Output		: None.
 Return		: SUCCESSFUL	- Successful scan
		  ohterwise	- No drives founded
*****************************************************************************/
int orc_ReturnNumberOfAdapters(void)
{
	unsigned int i, iAdapters;

	iAdapters = 0;
	/*
	 * PCI-bus probe.
	 */
	if (pcibios_present()) {
		struct {
			unsigned short vendor_id;
			unsigned short device_id;
		} const inia100_pci_devices[] =
		{
			{ORC_VENDOR_ID, I920_DEVICE_ID},
			{ORC_VENDOR_ID, ORC_DEVICE_ID}
		};

		unsigned int dRegValue;
		unsigned short command;
		WORD wBIOS, wBASE;
		BYTE bPCIBusNum, bInterrupt, bPCIDeviceNum;

#ifdef MMAPIO
		unsigned long page_offset, base;
#endif

#if LINUX_VERSION_CODE > CVT_LINUX_VERSION(2,1,92)
		struct pci_dev *pdev = NULL;
#else
		int index;
		unsigned char pci_bus, pci_devfn;
#endif

		bPCIBusNum = 0;
		bPCIDeviceNum = 0;
		init_inia100Adapter_table();
		for (i = 0; i < NUMBER(inia100_pci_devices); i++) {
#if LINUX_VERSION_CODE > CVT_LINUX_VERSION(2,1,92)
			pdev = NULL;
			while ((pdev = pci_find_device(inia100_pci_devices[i].vendor_id,
					inia100_pci_devices[i].device_id,
						       pdev)))
#else
			index = 0;
			while (!(pcibios_find_device(inia100_pci_devices[i].vendor_id,
					inia100_pci_devices[i].device_id,
					 index++, &pci_bus, &pci_devfn)))
#endif
			{
				if (iAdapters >= MAX_SUPPORTED_ADAPTERS)
					break;	/* Never greater than maximum   */

				if (i == 0) {
					/*
					   printk("inia100: The RAID controller is not supported by\n");
					   printk("inia100:         this driver, we are ignoring it.\n");
					 */
				} else {
					/*
					 * Read sundry information from PCI BIOS.
					 */
#if LINUX_VERSION_CODE > CVT_LINUX_VERSION(2,1,92)
					bPCIBusNum = pdev->bus->number;
					bPCIDeviceNum = pdev->devfn;
					dRegValue = pdev->base_address[0];
					if (dRegValue == -1) {	/* Check return code            */
						printk("\n\rinia100: orchid read configuration error.\n");
						return (0);	/* Read configuration space error  */
					}
					/* <02> read from base address + 0x50 offset to get the wBIOS balue. */
					wBASE = (WORD) dRegValue;

					/* Now read the interrupt line  */
					dRegValue = pdev->irq;
					bInterrupt = dRegValue & 0xFF;	/* Assign interrupt line      */
					pci_read_config_word(pdev, PCI_COMMAND, &command);
					pci_write_config_word(pdev, PCI_COMMAND,
							      command | PCI_COMMAND_MASTER | PCI_COMMAND_IO);

#else
					bPCIBusNum = pci_bus;
					bPCIDeviceNum = pci_devfn;
					pcibios_read_config_dword(pci_bus, pci_devfn, PCI_BASE_ADDRESS_0,
							     &dRegValue);
					if (dRegValue == -1) {	/* Check return code            */
						printk("\n\rinia100: Orchid read configuration error.\n");
						return (0);	/* Read configuration space error  */
					}
					/* <02> read from base address + 0x50 offset to get the wBIOS balue. */
					wBASE = (WORD) dRegValue;

					/* Now read the interrupt line  */
					pcibios_read_config_dword(pci_bus, pci_devfn, PCI_INTERRUPT_LINE,
							     &dRegValue);
					bInterrupt = dRegValue & 0xFF;	/* Assign interrupt line      */
					pcibios_read_config_word(pci_bus, pci_devfn, PCI_COMMAND, &command);
					pcibios_write_config_word(pci_bus, pci_devfn, PCI_COMMAND,
								  command | PCI_COMMAND_MASTER | PCI_COMMAND_IO);
#endif
					wBASE &= PCI_BASE_ADDRESS_IO_MASK;
					wBIOS = ORC_RDWORD(wBASE, 0x50);

#ifdef MMAPIO
					base = wBASE & PAGE_MASK;
					page_offset = wBASE - base;

					/*
					 * replace the next line with this one if you are using 2.1.x:
					 * temp_p->maddr = ioremap(base, page_offset + 256);
					 */
#if LINUX_VERSION_CODE >= CVT_LINUX_VERSION(2,1,0)
					wBASE = ioremap(base, page_offset + 256);
#else
					wBASE = (WORD) vremap(base, page_offset + 256);
#endif
					if (wBASE) {
						wBASE += page_offset;
					}
#endif

					if (Addinia100_into_Adapter_table(wBIOS, wBASE, bInterrupt, bPCIBusNum,
					    bPCIDeviceNum) == SUCCESSFUL)
						iAdapters++;
				}
			}	/* while(pdev=....) */
		}		/* for PCI_DEVICES */
	}			/* PCI BIOS present */
	return (iAdapters);
}
示例#14
0
int rtl8139_probe(struct device *dev)
{
	int cards_found = 0;
	int pci_index = 0;
	unsigned char pci_bus, pci_device_fn;

	if ( ! pcibios_present())
		return -ENODEV;

	for (; pci_index < 0xff; pci_index++) {
		u16 vendor, device, pci_command, new_command;
		int chip_idx, irq;
		long ioaddr;

		if (pcibios_find_class (PCI_CLASS_NETWORK_ETHERNET << 8, pci_index,
								&pci_bus, &pci_device_fn)
			!= PCIBIOS_SUCCESSFUL)
			break;
		pcibios_read_config_word(pci_bus, pci_device_fn,
								 PCI_VENDOR_ID, &vendor);
		pcibios_read_config_word(pci_bus, pci_device_fn,
								 PCI_DEVICE_ID, &device);

		for (chip_idx = 0; pci_tbl[chip_idx].vendor_id; chip_idx++)
			if (vendor == pci_tbl[chip_idx].vendor_id
				&& (device & pci_tbl[chip_idx].device_id_mask) ==
				pci_tbl[chip_idx].device_id)
				break;
		if (pci_tbl[chip_idx].vendor_id == 0) 		/* Compiled out! */
			continue;

		{
#if defined(PCI_SUPPORT_VER2)
			struct pci_dev *pdev = pci_find_slot(pci_bus, pci_device_fn);
			ioaddr = pdev->base_address[0] & ~3;
			irq = pdev->irq;
#else
			u32 pci_ioaddr;
			u8 pci_irq_line;
			pcibios_read_config_byte(pci_bus, pci_device_fn,
									 PCI_INTERRUPT_LINE, &pci_irq_line);
			pcibios_read_config_dword(pci_bus, pci_device_fn,
									  PCI_BASE_ADDRESS_0, &pci_ioaddr);
			ioaddr = pci_ioaddr & ~3;
			irq = pci_irq_line;
#endif
		}

		if ((pci_tbl[chip_idx].flags & PCI_USES_IO) &&
			check_region(ioaddr, pci_tbl[chip_idx].io_size))
			continue;

		/* Activate the card: fix for brain-damaged Win98 BIOSes. */
		pcibios_read_config_word(pci_bus, pci_device_fn,
								 PCI_COMMAND, &pci_command);
		new_command = pci_command | (pci_tbl[chip_idx].flags & 7);
		if (pci_command != new_command) {
			printk(KERN_INFO "  The PCI BIOS has not enabled the"
				   " device at %d/%d!  Updating PCI command %4.4x->%4.4x.\n",
				   pci_bus, pci_device_fn, pci_command, new_command);
			pcibios_write_config_word(pci_bus, pci_device_fn,
									  PCI_COMMAND, new_command);
		}

		dev = pci_tbl[chip_idx].probe1(pci_bus, pci_device_fn, dev, ioaddr,
									   irq, chip_idx, cards_found);

		if (dev  && (pci_tbl[chip_idx].flags & PCI_COMMAND_MASTER)) {
			u8 pci_latency;
			pcibios_read_config_byte(pci_bus, pci_device_fn,
									 PCI_LATENCY_TIMER, &pci_latency);
			if (pci_latency < 32) {
				printk(KERN_NOTICE "  PCI latency timer (CFLT) is "
					   "unreasonably low at %d.  Setting to 64 clocks.\n",
					   pci_latency);
				pcibios_write_config_byte(pci_bus, pci_device_fn,
										  PCI_LATENCY_TIMER, 64);
			}
		}
		dev = 0;
		cards_found++;
	}

	return cards_found ? 0 : -ENODEV;
}
示例#15
0
static int pci_etherdev_probe(struct device *dev, struct pci_id_info pci_tbl[])
{
	int cards_found = 0;
	int pci_index = 0;
	unsigned char pci_bus, pci_device_fn;

	if ( ! pcibios_present())
		return -ENODEV;

	for (;pci_index < 0xff; pci_index++) {
		u16 vendor, device, pci_command, new_command;
		int chip_idx, irq;
		long pciaddr;
		long ioaddr;

		if (pcibios_find_class (PCI_CLASS_NETWORK_ETHERNET << 8, pci_index,
								&pci_bus, &pci_device_fn)
			!= PCIBIOS_SUCCESSFUL)
			break;
		pcibios_read_config_word(pci_bus, pci_device_fn,
								 PCI_VENDOR_ID, &vendor);
		pcibios_read_config_word(pci_bus, pci_device_fn,
								 PCI_DEVICE_ID, &device);

		for (chip_idx = 0; pci_tbl[chip_idx].vendor_id; chip_idx++)
			if (vendor == pci_tbl[chip_idx].vendor_id
				&& (device & pci_tbl[chip_idx].device_id_mask) ==
				pci_tbl[chip_idx].device_id)
				break;
		if (pci_tbl[chip_idx].vendor_id == 0) 		/* Compiled out! */
			continue;

		{
#if defined(PCI_SUPPORT_VER2)
			struct pci_dev *pdev = pci_find_slot(pci_bus, pci_device_fn);
#ifdef VIA_USE_IO
			pciaddr = pdev->base_address[0];
#else
			pciaddr = pdev->base_address[1];
#endif
			irq = pdev->irq;
#else
			u32 pci_memaddr;
			u8 pci_irq_line;
			pcibios_read_config_byte(pci_bus, pci_device_fn,
									 PCI_INTERRUPT_LINE, &pci_irq_line);
#ifdef VIA_USE_IO
			pcibios_read_config_dword(pci_bus, pci_device_fn,
									  PCI_BASE_ADDRESS_0, &pci_memaddr);
			pciaddr = pci_memaddr;
#else
			pcibios_read_config_dword(pci_bus, pci_device_fn,
									  PCI_BASE_ADDRESS_1, &pci_memaddr);
			pciaddr = pci_memaddr;
#endif
			irq = pci_irq_line;
#endif
		}

		if (debug > 2)
			printk(KERN_INFO "Found %s at PCI address %#lx, IRQ %d.\n",
				   pci_tbl[chip_idx].name, pciaddr, irq);

		if (pci_tbl[chip_idx].flags & PCI_USES_IO) {
			ioaddr = pciaddr & ~3;
			if (check_region(ioaddr, pci_tbl[chip_idx].io_size))
				continue;
		} else if ((ioaddr = (long)ioremap(pciaddr & ~0xf,
										 pci_tbl[chip_idx].io_size)) == 0) {
			printk(KERN_INFO "Failed to map PCI address %#lx.\n",
				   pciaddr);
			continue;
		}

		pcibios_read_config_word(pci_bus, pci_device_fn,
								 PCI_COMMAND, &pci_command);
		new_command = pci_command | (pci_tbl[chip_idx].flags & 7);
		if (pci_command != new_command) {
			printk(KERN_INFO "  The PCI BIOS has not enabled the"
				   " device at %d/%d!  Updating PCI command %4.4x->%4.4x.\n",
				   pci_bus, pci_device_fn, pci_command, new_command);
			pcibios_write_config_word(pci_bus, pci_device_fn,
									  PCI_COMMAND, new_command);
		}

		dev = pci_tbl[chip_idx].probe1(pci_bus, pci_device_fn, dev, ioaddr,
									   irq, chip_idx, cards_found);

		if (dev  && (pci_tbl[chip_idx].flags & PCI_COMMAND_MASTER)) {
			u8 pci_latency;
			pcibios_read_config_byte(pci_bus, pci_device_fn,
									 PCI_LATENCY_TIMER, &pci_latency);
			if (pci_latency < min_pci_latency) {
				printk(KERN_INFO "  PCI latency timer (CFLT) is "
					   "unreasonably low at %d.  Setting to %d clocks.\n",
					   pci_latency, min_pci_latency);
				pcibios_write_config_byte(pci_bus, pci_device_fn,
										  PCI_LATENCY_TIMER, min_pci_latency);
			}
		}
		dev = 0;
		cards_found++;
	}

	return cards_found ? 0 : -ENODEV;
}
示例#16
0
/*
scan the pci bus
 look for vendor/device Id == Siemens PITA
 if found
    look for  subvendor id
    if found
      write to pita register 1c in the first address range the value 0x04000000
*/
int pcimod_scan(void)
{
    int i, pos = 0;
    int bus, fun;
    unsigned char headertype = 0;
    u32 id;
    u32 vdid;				/* vendor/device id */
    int candev = 0;				/* number of found devices */

    if (!pcibios_present()) {
        printk("CAN: No PCI bios present\n");
        return ENODEV;
    }
    /* printk("CAN: PCI bios present!\n"); */

    /*
     * This code is derived from "drivers/pci/pci.c". This means that
     * the GPL applies to this source file and credit is due to the
     * original authors (Drew Eckhardt, Frederic Potter, David
     * Mosberger-Tang)
     */
    for (bus = 0; !bus; bus++) { /* only bus 0 :-) */
        for (fun=0; fun < 0x100 && pos < PAGE_SIZE; fun++) {
            if (!PCI_FUNC(fun)) /* first function */
                pcibios_read_config_byte(bus,fun,PCI_HEADER_TYPE, &headertype);
            else if (!(headertype & 0x80))
                continue;
            /* the following call gets vendor AND device ID */
            pcibios_read_config_dword(bus, fun, PCI_VENDOR_ID, &id);
            if (!id || id == ~0) {
                headertype = 0; continue;
            }
            /* v-endor and d-evice id */
            vdid = id;
#if 0
            printk(" -- found pci device, vendor id = %u/0x%x , device 0x%x\n",
            	(id & 0xffff), (id & 0xffff), (id >> 16));
#endif
            pcibios_read_config_dword(bus, fun, PCI_CLASS_REVISION, &id);
#if 0
            printk("    class 0x%x, Revision %d\n",
            	(id >> 8), (id & 0x0ff));
#endif
            if(vdid == (PCI_VENDOR + (PCI_DEVICE << 16))) {
		unsigned char irq;
		u16 cmd;
		u32 svdid;			/* subsystem vendor/device id */
		    /* found EMS CAN CPC-PCI */
		    vdid = 0;	/* reset it */
		    printk("    found Siemens PITA PCI-Chip\n");
		    pcibios_read_config_byte(bus, fun, PCI_INTERRUPT_LINE, &irq);
		    printk("        using IRQ %d\n", irq);
		    pcibios_read_config_word(bus, fun, PCI_COMMAND, &cmd);
		    /* printk("        cmd: 0x%x\n", cmd); */

                    /* PCI_COMMAND should be at least PCI_COMMAND_MEMORY */
		    pcibios_write_config_word(bus, fun,
		    		/* PCI_COMMAND, PCI_COMMAND_MEMORY); */
		    		PCI_COMMAND, PCI_COMMAND_MEMORY + PCI_COMMAND_MASTER	);
		    pcibios_read_config_word(bus, fun, PCI_COMMAND, &cmd);
		    /* printk("        cmd: 0x%x\n", cmd); */




		    pcibios_read_config_dword(bus, fun, PCI_SUBSYSTEM_VENDOR_ID, &svdid);
		    /* printk("        s_vendor 0x%x, s_device 0x%x\n", */
					/* (svdid & 0xffff), (svdid >> 16)); */

		/* How can we be sure that that is an EMS CAN card ?? */


		for (i = 0; addresses[i]; i++) {
		    u32 curr, mask;
		    char *type;

		    pcibios_read_config_dword(bus, fun, addresses[i], &curr);
		    cli();
		    pcibios_write_config_dword(bus, fun, addresses[i], ~0);
		    pcibios_read_config_dword(bus, fun, addresses[i], &mask);
		    pcibios_write_config_dword(bus, fun, addresses[i], curr);
		    sti();

		    /* printk("    region %i: mask 0x%08lx, now at 0x%08lx\n", i, */
				   /* (unsigned long)mask, */
				   /* (unsigned long)curr); */
#if 0 /* we don't need this message, so we don't need this code */
		    if (!mask) {
			printk("    region %i not existent\n", i);
			break;
		    }
#endif
		    /* extract the type, and the programmable bits */
		    if (mask & PCI_BASE_ADDRESS_SPACE) {
		    type = "I/O"; mask &= PCI_BASE_ADDRESS_IO_MASK;
		    } else {
			type = "mem"; mask &= PCI_BASE_ADDRESS_MEM_MASK;
		    }
		/* printk("    region %i: type %s, size %i\n", i, */
			      /* type, ~mask+1); */

		    if(i == 0) {
		    	/* BAR0 internal PITA registers */
			unsigned long ptr = (unsigned long)ioremap(curr, 256);
			/* enable memory access */
		    	/* printk("write to pita\n"); */
			writel(0x04000000, ptr + 0x1c);
			Can_pitapci_control[candev] = ptr;

		    }
		    if(i == 1) {
		    	/* BAR1 parallel I/O
		    	 * at address 0 are some EMS control registers
		    	 * at address 0x400 the first controller area 
		    	 * at address 0x600 the second controller area 
			 * registers are read as 32bit
			 *
			 * at adress 0 we can verify the card
			 * 0x55 0xaa 0x01 0xcb
			 */
			/* dump_CAN(curr, 4); */

			reset_CPC_PCI(curr);

			/* enable interrupts Int_0 */
			/* write to PITAs ICR register */
    			writel(0x00020000, Can_pitapci_control[candev] + 0x0);

			/* dump_CAN(curr + 0x400, 4); */
			if(controller_available(curr + 0x400, 4)) {
			    printk("CAN: at pos 1\n");
			    if(candev > 4) {
				printk("CAN: only 4 devices supported\n");
				break; /* the devices scan loop */
			    }
			    Base[candev]
			    = (unsigned long)ioremap(curr + 0x400, 32*4);
			    IOModel[candev] = 'm';
			    IRQ[candev] = irq;
			    candev++;
			} else {
			    printk("CAN: NO at pos 1\n");
			}
			/* dump_CAN(curr + 0x600, 4); */

			if(controller_available(curr + 0x600, 4)) {
			    printk("CAN: at pos 2\n");
			    if(candev > 4) {
				printk("CAN: only 4 devices supported\n");
				break; /* the devices scan loop */
			    }
			    /* share the board control register with prev ch */
    			    Can_pitapci_control[candev] = 
				Can_pitapci_control[candev - 1];
			    Base[candev]
			    = (unsigned long)ioremap(curr + 0x600, 32*4);
			    IOModel[candev] = 'm';
			    IRQ[candev] = irq;
			    candev++;
			} else {
			    printk("CAN: NO at pos 2\n");
			}
		    }

		}
            } /* EMS CPC-PCI */
        } /* for all devices */
    } /* for all busses */
    return 0;
}
示例#17
0
HPT_U32 pcicfg_read_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg)
{
	HPT_U32 v;
	if (pcibios_read_config_dword(bus, (dev<<3)|func, reg, (unsigned int *)&v)) return 0xffffffff;
	return v;
}
示例#18
0
static int initialize_pcicard( DEV *dev, int index )
    {
    dbg1("%s(): dev=%08X", __FUNCTION__, (uint)dev);
        {    
#if 0
        u32  PlxIntCsrPort, cport, rport, wtcport, rtr;
        int  irq;
        char bus, function;
        
        if( !pcibios_present() )
            {
            err( "PCI bios not present\n" );
            return -ENODEV;
            }
        if( pcibios_find_device( VENDOR_ID, DEVICE_ID, index, &bus, &function ) )
            {
            err( "PCI device not found\n" );
            return -ENODEV;
            }
        pcibios_read_config_dword( bus, function, 0x14, (int *)&rtr );
        pcibios_read_config_dword( bus, function, 0x18, (int *)&cport );
        pcibios_read_config_dword( bus, function, 0x1C, (int *)&rport );
        pcibios_read_config_dword( bus, function, 0x24, (int *)&wtcport );
        pcibios_read_config_dword( bus, function, 0x3C, &irq );
        PlxIntCsrPort = (rtr & 0xFFF0) + P9050_INTCSR;
        cport   &= 0xFFF0;
        rport   &= 0xFFF0;
        irq     &= 0x0F;
        outw( 0, PlxIntCsrPort );
        
        if( check_region(cport, 4) ) {
            err( "unable to register port 0x%X\n", cport );
            return -ENODEV;
            }
        if( check_region(rport, 4) ) {
            err( "unable to register port 0x%X\n", rport );
            return -ENODEV;
            }
        request_region( cport, 4, DRIVER_DEV_NAME );
        request_region( rport, 4, DRIVER_DEV_NAME );
        dev->cport   = cport;
        dev->rport   = rport;
        dev->wport   = rport;
        dev->wtcport = wtcport;
        dev->irq     = irq;
        dev->PlxIntCsrPort = PlxIntCsrPort;
#else
        u32  cport;
        u16  IntCsr;
        cport   = dev->cport;
        
#endif
        dev->ctl = 0x0D;
        SETCTL;
        SETCTL;
        dev->ctl = 0x16;
        SETCTL;
        SETCTL;
        dev->ctl = 0x02;
        SETCTL;
        SETCTL;
        dev->ctl = 0x16;
        SETCTL;
        IntCsr = inw(dev->PlxIntCsrPort);
        dbg1("? %s(): PlxIntCsrPort=%04X IntCsr=%04X", __FUNCTION__, dev->PlxIntCsrPort, IntCsr);
        IntCsr |= PLX_9050_INTR_ENABLE | PLX_9050_LINT1_ENABLE; // | PLX_9050_LINT2_ENABLE;
        outw(IntCsr, dev->PlxIntCsrPort);
        dbg1("? %s(): PlxIntCsrPort=%04X IntCsr=%04X", __FUNCTION__, dev->PlxIntCsrPort, IntCsr);
        
        if( request_irq(dev->irq, lpc_pci_interrupt, SA_SHIRQ, DRIVER_DEV_NAME, dev) ) 
            {
            err("unable to register IRQ%d\n", dev->irq);
#if 0
            release_region(rport, 4);
            release_region(cport, 4);
#endif
            return -ENODEV;
            }
        return 0;
        }
    }
示例#19
0
int DivasCardsDiscover(void)
{
	word wNumCards = 0, wDeviceIndex = 0;
	byte byBus, byFunc;
	word wPCIConsultation, PCItmp;
	dword j, i;
	unsigned int PCIserial;
	dia_card_t Card;
	byte *b;
	
	while (wDeviceIndex < 10)
	{
		wPCIConsultation = pcibios_find_device(PCI_VENDOR_ID_EICON, 
				PCI_DEVICE_ID_EICON_MAESTRAQ, 
				wDeviceIndex, 
				&byBus, &byFunc);

		if (wPCIConsultation == PCIBIOS_SUCCESSFUL)
		{

			dword dwRAM, dwDivasIOBase, dwCFG, dwCTL; 			
			byte byIRQ;
			
			printk(KERN_DEBUG "Divas: DIVA Server 4BRI Found\n");
			pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_2,(unsigned int *) &dwRAM);
			dwRAM &= 0xFFC00000;
			
			pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_1,(unsigned int *) &dwDivasIOBase);
			dwDivasIOBase &= 0xFFFFFF00;
			
			pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_0,(unsigned int *) &dwCFG);
			dwCFG &= 0xFFFFFF00;
			
			pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_3,(unsigned int *) &dwCTL);
			dwCTL &= 0xFFFFE000;
			

			pcibios_read_config_byte(byBus, byFunc, PCI_INTERRUPT_LINE, &byIRQ);
			/* Retrieve the serial number */

			pcibios_write_config_word(byBus,byFunc,0x4E,0x00FC);

			for (j=0, PCItmp=0; j<10000 && !PCItmp; j++)
			{
				pcibios_read_config_word(byBus,byFunc,0x4E, &PCItmp);
				PCItmp &= 0x8000;  // extract done flag
			}

			pcibios_read_config_dword(byBus,byFunc,0x50, &PCIserial);

		
			Card.memory[DIVAS_RAM_MEMORY] = ioremap(dwRAM, 0x400000);
			Card.memory[DIVAS_CTL_MEMORY] = ioremap(dwCTL, 0x2000);
			Card.memory[DIVAS_CFG_MEMORY] = ioremap(dwCFG, 0x100);
			Card.io_base=dwDivasIOBase;

			Card.irq = byIRQ;
			
			Card.card_type = DIA_CARD_TYPE_DIVA_SERVER_Q;
			Card.bus_type = DIA_BUS_TYPE_PCI;
	
			FPGA_Done = 0;

			/* Create four virtual card structures as we want to treat 
			   the 4Bri card as 4 Bri cards*/
			for(i=0;i<4;i++)
			{

				b=Card.memory[DIVAS_RAM_MEMORY];
				b+=(MQ_PROTCODE_OFFSET) * (i==0?0:1); 
				DPRINTF(("divas: offset = 0x%x", i* MQ_PROTCODE_OFFSET));
				Card.memory[DIVAS_RAM_MEMORY]=b;
 
				b = Card.memory[DIVAS_RAM_MEMORY];
				b += MQ_SM_OFFSET;
				Card.memory[DIVAS_SHARED_MEMORY] = b;

				Card.bus_num = byBus;
				Card.func_num = byFunc;
				Card.slot = -1;

			
				/* Fill in Name */
				Card.name[0] = 'D';
				Card.name[1] = 'I';
				Card.name[2] = 'V';
				Card.name[3] = 'A';
				Card.name[4] = 'S';
				Card.name[5] = 'Q';
				Card.name[6] = '0' + i;
				Card.name[7] = '\0';

				Card.serial = PCIserial;

			 	Card.card_id = wNumCards;

 				if (DivasCardNew(&Card) != 0)
				{
					// Force for loop to terminate
					i = 4;
					continue;
				}
				wNumCards++;

			}//for
		}
		wDeviceIndex++;
	}

	wDeviceIndex = 0;

	while (wDeviceIndex < 10)
	{
		wPCIConsultation = pcibios_find_device(PCI_VENDOR_ID_EICON, 
				PCI_DEVICE_ID_EICON_MAESTRA, 
				wDeviceIndex, 
				&byBus, &byFunc);

		if (wPCIConsultation == PCIBIOS_SUCCESSFUL)
		{
			dword dwPLXIOBase, dwDivasIOBase;
			byte byIRQ;

			printk(KERN_DEBUG "Divas: DIVA Server BRI (S/T) Found\n");
			pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_1, (unsigned int *) &dwPLXIOBase);
			dwPLXIOBase &= 0xFFFFFF80;

			pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_2, (unsigned int *) &dwDivasIOBase);
			dwDivasIOBase &= 0xFFFFFFFC;

			pcibios_read_config_byte(byBus, byFunc, PCI_INTERRUPT_LINE, &byIRQ);

			Card.card_id = wNumCards;
			Card.card_type = DIA_CARD_TYPE_DIVA_SERVER_B;
			Card.bus_type = DIA_BUS_TYPE_PCI;
			Card.irq = byIRQ;
			Card.reset_base = dwPLXIOBase;
			Card.io_base = dwDivasIOBase;
			Card.bus_num = byBus;
			Card.func_num = byFunc;
			Card.slot = -1;
			Card.name[0] = 'D';
			Card.name[1] = 'I';
			Card.name[2] = 'V';
			Card.name[3] = 'A';
			Card.name[4] = 'S';
			Card.name[5] = 'B';
			Card.name[6] = '\0';

			if (check_region(Card.io_base, 0x20))
			{
				printk(KERN_WARNING "Divas: DIVA I/O Base already in use 0x%x-0x%x\n", Card.io_base, Card.io_base + 0x1F);
				wDeviceIndex++;
				continue;
			}

			if (check_region(Card.reset_base, 0x80))
			{
				printk(KERN_WARNING "Divas: PLX I/O Base already in use 0x%x-0x%x\n", Card.reset_base, Card.reset_base + 0x7F);
				wDeviceIndex++;
				continue;
			}

			if (DivasCardNew(&Card) != 0)
			{
				wDeviceIndex++;
				continue;
			}
			wNumCards++;
		}

		wPCIConsultation = pcibios_find_device(PCI_VENDOR_ID_EICON, 
				PCI_DEVICE_ID_EICON_MAESTRAQ_U, 
				wDeviceIndex, 
				&byBus, &byFunc);

		if (wPCIConsultation == PCIBIOS_SUCCESSFUL)
		{
			dword dwPLXIOBase, dwDivasIOBase;
			byte byIRQ;

			printk(KERN_DEBUG "Divas: DIVA Server BRI (U) Found\n");

			pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_1, (unsigned int *) &dwPLXIOBase);
			dwPLXIOBase &= 0xFFFFFF80;

			pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_2, (unsigned int *) &dwDivasIOBase);
			dwDivasIOBase &= 0xFFFFFFFC;

			pcibios_read_config_byte(byBus, byFunc, PCI_INTERRUPT_LINE, &byIRQ);

			Card.card_id = wNumCards;
			Card.card_type = DIA_CARD_TYPE_DIVA_SERVER_B;
			Card.bus_type = DIA_BUS_TYPE_PCI;
			Card.irq = byIRQ;
			Card.reset_base = dwPLXIOBase;
			Card.io_base = dwDivasIOBase;
			Card.bus_num = byBus;
			Card.func_num = byFunc;
			Card.slot = -1;
			Card.name[0] = 'D';
			Card.name[1] = 'I';
			Card.name[2] = 'V';
			Card.name[3] = 'A';
			Card.name[4] = 'S';
			Card.name[5] = 'B';
			Card.name[6] = '\0';

			if (check_region(Card.io_base, 0x20))
			{
				printk(KERN_WARNING "Divas: DIVA I/O Base already in use 0x%x-0x%x\n", Card.io_base, Card.io_base + 0x1F);	
				wDeviceIndex++;
				continue;
			}

			if (check_region(Card.reset_base, 0x80))
			{
				printk(KERN_WARNING "Divas: PLX I/O Base already in use 0x%x-0x%x\n", Card.reset_base, Card.reset_base + 0x7F);
				wDeviceIndex++;
				continue;
			}

			if (DivasCardNew(&Card) != 0)
			{
				wDeviceIndex++;
				continue;
			}
			wNumCards++;
		}

		wDeviceIndex++;
	}

	wDeviceIndex = 0;

	while (wDeviceIndex < 10)
	{
		wPCIConsultation = pcibios_find_device(PCI_VENDOR_ID_EICON, 
				PCI_DEVICE_ID_EICON_MAESTRAP, 
				wDeviceIndex, 
				&byBus, &byFunc);

		if (wPCIConsultation == PCIBIOS_SUCCESSFUL)
		{
			dword dwRAM, dwREG, dwCFG;
			byte byIRQ;

			printk(KERN_DEBUG "Divas: DIVA Server PRI Found\n");

			pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_0, (unsigned int *) &dwRAM);
			dwRAM &= 0xFFFFF000;

			pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_2, (unsigned int *) &dwREG);
			dwREG &= 0xFFFFF000;
			
			pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_4, (unsigned int *) &dwCFG);
			dwCFG &= 0xFFFFF000;

			pcibios_read_config_byte(byBus, byFunc, PCI_INTERRUPT_LINE, &byIRQ);

			Card.memory[DIVAS_RAM_MEMORY] = ioremap(dwRAM, 0x10000);
			Card.memory[DIVAS_REG_MEMORY] = ioremap(dwREG, 0x4000);
			Card.memory[DIVAS_CFG_MEMORY] = ioremap(dwCFG, 0x1000);
			Card.memory[DIVAS_SHARED_MEMORY] = Card.memory[DIVAS_RAM_MEMORY] + DIVAS_SHARED_OFFSET;

/*			pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_1, (unsigned int *) &dwPLXIOBase);
			dwPLXIOBase &= 0xFFFFFFFc;

			pcibios_read_config_dword(byBus, byFunc, PCI_BASE_ADDRESS_2, (unsigned int *) &dwDivasIOBase);
			dwDivasIOBase &= 0xFFFFFF80;

			pcibios_read_config_byte(byBus, byFunc, PCI_INTERRUPT_LINE, &byIRQ);
*/
			Card.card_id = wNumCards;
			Card.card_type = DIA_CARD_TYPE_DIVA_SERVER;
			Card.bus_type = DIA_BUS_TYPE_PCI;
			Card.irq = byIRQ;
/*			Card.reset_base = dwPLXIOBase;
			Card.io_base = dwDivasIOBase;*/
			Card.bus_num = byBus;
			Card.func_num = byFunc;
			Card.slot = -1;
			Card.name[0] = 'D';
			Card.name[1] = 'I';
			Card.name[2] = 'V';
			Card.name[3] = 'A';
			Card.name[4] = 'S';
			Card.name[5] = 'P';
			Card.name[6] = '\0';

			if (DivasCardNew(&Card) != 0)
			{
				wDeviceIndex++;
				continue;
			}
			wNumCards++;
		}

		wDeviceIndex++;
	}


	printk(KERN_INFO "Divas: %d cards detected\n", wNumCards);

	if(wNumCards == 0)
	{
		return -1;
	}

	Divas_fops.ioctl = do_ioctl;
	Divas_fops.poll = do_poll;
	Divas_fops.read = do_read;
	Divas_fops.open = do_open;
	Divas_fops.release = do_release;

	Divas_major = register_chrdev(0, "Divas", &Divas_fops);

	if (Divas_major < 0)
	{
		printk(KERN_WARNING "Divas: Unable to register character driver\n");
		return -1;
	}

	return 0;
}
示例#20
0
int __init raven_init(void)
{
	unsigned int	devid;
	unsigned int	pci_membase;
	unsigned char	base_mod;

	/* Check to see if the Raven chip exists. */
	if ( _prep_type != _PREP_Motorola) {
		OpenPIC = NULL;
		return 0;
	}

	/* Check to see if this board is a type that might have a Raven. */
	if ((inb(MOTOROLA_CPUTYPE_REG) & 0xF0) != 0xE0) {
		OpenPIC = NULL;
		return 0;
	}

	/* Check the first PCI device to see if it is a Raven. */
	pcibios_read_config_dword(0, 0, PCI_VENDOR_ID, &devid);

	switch (devid & 0xffff0000) {
	case MPIC_RAVEN_ID:
		MotMPIC = MOT_RAVEN_PRESENT;
		break;
	case MPIC_HAWK_ID:
		MotMPIC = MOT_HAWK_PRESENT;
		break;
	default:
		OpenPIC = NULL;
		return 0;
	}


	/* Read the memory base register. */
	pcibios_read_config_dword(0, 0, PCI_BASE_ADDRESS_1, &pci_membase);

	if (pci_membase == 0) {
		OpenPIC = NULL;
		return 0;
	}

	/* Map the Raven MPIC registers to virtual memory. */
	OpenPIC = (struct OpenPIC *)ioremap(pci_membase+0xC0000000, 0x22000);

	OpenPIC_InitSenses = mvme2600_openpic_initsenses;
	OpenPIC_NumInitSenses = sizeof(mvme2600_openpic_initsenses);

	ppc_md.get_irq = chrp_get_irq;
	ppc_md.post_irq = chrp_post_irq;
	
	/* If raven is present on Motorola store the system config register
	 * for later use.
	 */
	ProcInfo = (unsigned long *)ioremap(0xfef80400, 4);

	/* This is a hack.  If this is a 2300 or 2400 mot board then there is
	 * no keyboard controller and we have to indicate that.
	 */
	base_mod = inb(MOTOROLA_BASETYPE_REG);
	if ((MotMPIC == MOT_HAWK_PRESENT) || (base_mod == 0xF9) ||
	    (base_mod == 0xFA) || (base_mod == 0xE1))
		prep_keybd_present = 0;

	return 1;
}
示例#21
0
__initfunc(int
setup_telespci(struct IsdnCard *card))
{
	int found=0;
	struct IsdnCardState *cs = card->cs;
	char tmp[64];
	u_char pci_bus, pci_device_fn, pci_irq;
	u_int pci_memaddr;

	strcpy(tmp, telespci_revision);
	printk(KERN_INFO "HiSax: Teles/PCI driver Rev. %s\n", HiSax_getrev(tmp));
	if (cs->typ != ISDN_CTYPE_TELESPCI)
		return (0);

#if CONFIG_PCI
	for (; pci_index < 0xff; pci_index++) {
		if (pcibios_find_device (0x11DE, 0x6120,
			pci_index, &pci_bus, &pci_device_fn)
			== PCIBIOS_SUCCESSFUL) {
			found = 1;
		} else {
			break;
		}
		pcibios_read_config_dword(pci_bus, pci_device_fn,
				PCI_BASE_ADDRESS_0, &pci_memaddr);
		pcibios_read_config_byte(pci_bus, pci_device_fn,
				PCI_INTERRUPT_LINE, &pci_irq);

		printk(KERN_INFO "Found: Zoran, base-address: 0x%x,"
			" irq: 0x%x\n", pci_memaddr, pci_irq);
		break;
	}
	if (!found) {
		printk(KERN_WARNING "TelesPCI: No PCI card found\n");
		return(0);
	}
	pci_index++;
	cs->hw.teles0.membase = (u_int) vremap(pci_memaddr, PAGE_SIZE);
	cs->irq = pci_irq;
#else
	printk(KERN_WARNING "HiSax: Teles/PCI and NO_PCI_BIOS\n");
	printk(KERN_WARNING "HiSax: Teles/PCI unable to config\n");
	return (0);
#endif /* CONFIG_PCI */

	/* Initialize Zoran PCI controller */
	writel(0x00000000, cs->hw.teles0.membase + 0x28);
	writel(0x01000000, cs->hw.teles0.membase + 0x28);
	writel(0x01000000, cs->hw.teles0.membase + 0x28);
	writel(0x7BFFFFFF, cs->hw.teles0.membase + 0x2C);
	writel(0x70000000, cs->hw.teles0.membase + 0x3C);
	writel(0x61000000, cs->hw.teles0.membase + 0x40);
	/* writel(0x00800000, cs->hw.teles0.membase + 0x200); */

	printk(KERN_INFO
	       "HiSax: %s config irq:%d mem:%x\n",
	       CardType[cs->typ], cs->irq,
	       cs->hw.teles0.membase);

	cs->readisac = &ReadISAC;
	cs->writeisac = &WriteISAC;
	cs->readisacfifo = &ReadISACfifo;
	cs->writeisacfifo = &WriteISACfifo;
	cs->BC_Read_Reg = &ReadHSCX;
	cs->BC_Write_Reg = &WriteHSCX;
	cs->BC_Send_Data = &hscx_fill_fifo;
	cs->cardmsg = &TelesPCI_card_msg;
	ISACVersion(cs, "TelesPCI:");
	if (HscxVersion(cs, "TelesPCI:")) {
		printk(KERN_WARNING
		 "TelesPCI: wrong HSCX versions check IO/MEM addresses\n");
		release_io_telespci(cs);
		return (0);
	}
	return (1);
}
示例#22
0
static int tc2550_pci_bios_detect(int *irq, int *iobase)
{
	int error;
	unsigned char pci_bus, pci_dev_fn;	/* PCI bus & device function */
	unsigned char pci_irq;	/* PCI interrupt line */
	unsigned int pci_base;	/* PCI I/O base address */
	unsigned short pci_vendor, pci_device;	/* PCI vendor & device IDs */


	/* We will have to change this if more than 1 PCI bus is present and the
	   tripace scsi host is not on the first bus (i.e., a PCI to PCI bridge,
	   which is not supported by bios32 right now anyway). */

	pci_bus = 0;

	for (pci_dev_fn = 0x0; pci_dev_fn < 0xff; pci_dev_fn++)
	{
		pcibios_read_config_word(pci_bus,
					 pci_dev_fn,
					 PCI_VENDOR_ID,
					 &pci_vendor);

		if (pci_vendor == 0x1190)
		{
			pcibios_read_config_word(pci_bus,
						 pci_dev_fn,
						 PCI_DEVICE_ID,
						 &pci_device);

			if (pci_device == 0xc731)
			{
				/* Break out once we have the correct device.  If othertrip 
				   PCI devices are added to this driver we will need to add
				   an or of the other PCI_DEVICE_ID here. */
				printk(KERN_INFO "Tripace TC-2550x based PCI SCSI Adapter detected\n");
				break;
			} else
			{
				/* If we can't finl an tripace scsi card we give up. */
				return 0;
			}
		}
	}

/* vendor id not found */

	if (pci_device != 0xc731)
	{
		printk(KERN_INFO "Tripace TC-2550x - No Host Adapter Detected \n");
		return (0);
	}
	/* We now have the appropriate device function for the tripace board so we
	   just read the PCI config info from the registers.  */

	if ((error = pcibios_read_config_dword(pci_bus,
					       pci_dev_fn,
					       PCI_BASE_ADDRESS_0,
					       &pci_base))
	    || (error = pcibios_read_config_byte(pci_bus,
						 pci_dev_fn,
						 PCI_INTERRUPT_LINE,
						 &pci_irq)))
	{
		printk(KERN_ERR "Tripace TC-2550x not initializing"
		       " due to error reading configuration space\n");
		return 0;
	} else
	{
		printk(KERN_INFO "TC-2550x PCI: IRQ = %u, I/O base = %X\n",
		       pci_irq, pci_base);

		/* Now we have the I/O base address and interrupt from the PCI
		   configuration registers.  
		 */

		*irq = pci_irq;
		*iobase = (pci_base & 0xfff8);
		CFG_BASE = *iobase;

		printk(KERN_INFO "TC-2550x Driver version 1.00.000 (904)\n");
		printk(KERN_INFO "TC-2550x: IRQ = %d, I/O base = 0x%X\n", *irq, *iobase);
		return 1;
	}
	return 0;
}
示例#23
0
__initfunc(int
	   setup_sct_quadro(struct IsdnCard *card))
{
	struct IsdnCardState *cs = card->cs;
	char tmp[64];
#if CONFIG_PCI
	u_char pci_bus = 0, pci_device_fn = 0, pci_irq = 0, pci_rev_id;
	u_int found = 0;
	u_int pci_ioaddr1, pci_ioaddr2, pci_ioaddr3, pci_ioaddr4, pci_ioaddr5;
#endif

	strcpy(tmp, sct_quadro_revision);
	printk(KERN_INFO "HiSax: T-Berkom driver Rev. %s\n", HiSax_getrev(tmp));
	if (cs->typ == ISDN_CTYPE_SCT_QUADRO) {
		cs->subtyp = SCT_1;	/* Preset */
	} else
		return (0);

	/* Identify subtype by para[0] */
	if (card->para[0] >= SCT_1 && card->para[0] <= SCT_4)
		cs->subtyp = card->para[0];
	else
		printk(KERN_WARNING "HiSax: %s: Invalid subcontroller in configuration, default to 1\n",
		       CardType[card->typ]);
#if CONFIG_PCI
	if (!pci_present()) {
		printk(KERN_ERR "bkm_a4t: no PCI bus present\n");
		return (0);
	}
	if ((dev_a8 = pci_find_device(PLX_VENDOR_ID, PLX_DEVICE_ID, dev_a8))) {
		u_int sub_sys_id = 0;

		pci_read_config_dword(dev_a8, PCI_SUBSYSTEM_VENDOR_ID,
			&sub_sys_id);
		if (sub_sys_id == ((SCT_SUBSYS_ID << 16) | SCT_SUBVEN_ID)) {
			found = 1;
			pci_ioaddr1 = dev_a8->base_address[ 1];
			pci_irq = dev_a8->irq;
			pci_bus = dev_a8->bus->number;
			pci_device_fn = dev_a8->devfn;
		}
	}
	if (!found) {
		printk(KERN_WARNING "HiSax: %s (%s): Card not found\n",
		       CardType[card->typ],
		       sct_quadro_subtypes[cs->subtyp]);
		return (0);
	}
	if (!pci_irq) {		/* IRQ range check ?? */
		printk(KERN_WARNING "HiSax: %s (%s): No IRQ\n",
		       CardType[card->typ],
		       sct_quadro_subtypes[cs->subtyp]);
		return (0);
	}
#ifdef ATTEMPT_PCI_REMAPPING
/* HACK: PLX revision 1 bug: PLX address bit 7 must not be set */
	pcibios_read_config_byte(pci_bus, pci_device_fn, PCI_REVISION_ID, &pci_rev_id);
	if ((pci_ioaddr1 & 0x80) && (pci_rev_id == 1)) {
		printk(KERN_WARNING "HiSax: %s (%s): PLX rev 1, remapping required!\n",
			CardType[card->typ],
			sct_quadro_subtypes[cs->subtyp]);
		/* Restart PCI negotiation */
		pcibios_write_config_dword(pci_bus, pci_device_fn,
			PCI_BASE_ADDRESS_1, (u_int) - 1);
		/* Move up by 0x80 byte */
		pci_ioaddr1 += 0x80;
		pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK;
		pcibios_write_config_dword(pci_bus, pci_device_fn,
			PCI_BASE_ADDRESS_1, pci_ioaddr1);
		dev_a8->base_address[ 1] = pci_ioaddr1;
	}
/* End HACK */
#endif
	pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_1, &pci_ioaddr1);
	pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_2, &pci_ioaddr2);
	pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_3, &pci_ioaddr3);
	pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_4, &pci_ioaddr4);
	pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_5, &pci_ioaddr5);
	if (!pci_ioaddr1 || !pci_ioaddr2 || !pci_ioaddr3 || !pci_ioaddr4 || !pci_ioaddr5) {
		printk(KERN_WARNING "HiSax: %s (%s): No IO base address(es)\n",
		       CardType[card->typ],
		       sct_quadro_subtypes[cs->subtyp]);
		return (0);
	}
	pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK;
	pci_ioaddr2 &= PCI_BASE_ADDRESS_IO_MASK;
	pci_ioaddr3 &= PCI_BASE_ADDRESS_IO_MASK;
	pci_ioaddr4 &= PCI_BASE_ADDRESS_IO_MASK;
	pci_ioaddr5 &= PCI_BASE_ADDRESS_IO_MASK;
	/* Take over */
	cs->irq = pci_irq;
	cs->irq_flags |= SA_SHIRQ;
	/* pci_ioaddr1 is unique to all subdevices */
	/* pci_ioaddr2 is for the fourth subdevice only */
	/* pci_ioaddr3 is for the third subdevice only */
	/* pci_ioaddr4 is for the second subdevice only */
	/* pci_ioaddr5 is for the first subdevice only */
	cs->hw.ax.plx_adr = pci_ioaddr1;
	/* Enter all ipac_base addresses */
	ipac_state[SCT_1].base = pci_ioaddr5 + 0x00;
	ipac_state[SCT_2].base = pci_ioaddr4 + 0x08;
	ipac_state[SCT_3].base = pci_ioaddr3 + 0x10;
	ipac_state[SCT_4].base = pci_ioaddr2 + 0x20;
	/* For isac and hscx control path */
	cs->hw.ax.base = ipac_state[cs->subtyp].base;
	/* For isac and hscx data path */
	cs->hw.ax.data_adr = cs->hw.ax.base + 4;
#else
	printk(KERN_WARNING "HiSax: %s (%s): NO_PCI_BIOS\n",
	       CardType[card->typ],
	       sct_quadro_subtypes[cs->subtyp]);
	printk(KERN_WARNING "HiSax: %s (%s): Unable to configure\n",
	       CardType[card->typ],
	       sct_quadro_subtypes[cs->subtyp]);
	return (0);
#endif				/* CONFIG_PCI */
	printk(KERN_INFO "HiSax: %s (%s) configured at 0x%.4X, 0x%.4X, 0x%.4X and IRQ %d\n",
	       CardType[card->typ],
	       sct_quadro_subtypes[cs->subtyp],
	       cs->hw.ax.plx_adr,
	       cs->hw.ax.base,
	       cs->hw.ax.data_adr,
	       cs->irq);

	test_and_set_bit(HW_IPAC, &cs->HW_Flags);

	/* Disable all currently not active ipacs */
	if (!is_ipac_active(SCT_1))
		set_ipac_active(SCT_1, 0);
	if (!is_ipac_active(SCT_2))
		set_ipac_active(SCT_2, 0);
	if (!is_ipac_active(SCT_3))
		set_ipac_active(SCT_3, 0);
	if (!is_ipac_active(SCT_4))
		set_ipac_active(SCT_4, 0);

	/* Perfom general reset (if possible) */
	reset_bkm(cs);

	cs->readisac = &ReadISAC;
	cs->writeisac = &WriteISAC;
	cs->readisacfifo = &ReadISACfifo;
	cs->writeisacfifo = &WriteISACfifo;

	cs->BC_Read_Reg = &ReadHSCX;
	cs->BC_Write_Reg = &WriteHSCX;
	cs->BC_Send_Data = &hscx_fill_fifo;
	cs->cardmsg = &BKM_card_msg;
	cs->irq_func = &bkm_interrupt_ipac;

	printk(KERN_INFO "HiSax: %s (%s): IPAC Version %d\n",
		CardType[card->typ],
		sct_quadro_subtypes[cs->subtyp],
		readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ID));
	return (1);
}
示例#24
0
/*
 * ide_init_triton() prepares the IDE driver for DMA operation.
 * This routine is called once, from ide.c during driver initialization,
 * for each triton chipset which is found (unlikely to be more than one).
 */
void ide_init_triton (byte bus, byte fn)
{
	int rc = 0, h;
	int dma_enabled = 0;
	unsigned short bmiba, pcicmd;
	unsigned int timings;

	printk("ide: Triton BM-IDE on PCI bus %d function %d\n", bus, fn);
	/*
	 * See if IDE and BM-DMA features are enabled:
	 */
	if ((rc = pcibios_read_config_word(bus, fn, 0x04, &pcicmd)))
		goto quit;
	if ((pcicmd & 1) == 0)  {
		printk("ide: Triton IDE ports are not enabled\n");
		goto quit;
	}
	if ((pcicmd & 4) == 0) {
		printk("ide: Triton BM-DMA feature is not enabled -- upgrade your BIOS\n");
	} else {
		/*
		 * Get the bmiba base address
		 */
		if ((rc = pcibios_read_config_word(bus, fn, 0x20, &bmiba)))
			goto quit;
		bmiba &= 0xfff0;	/* extract port base address */
		dma_enabled = 1;
	}

	/*
	 * See if ide port(s) are enabled
	 */
	if ((rc = pcibios_read_config_dword(bus, fn, 0x40, &timings)))
		goto quit;
	if (!(timings & 0x80008000)) {
		printk("ide: neither Triton IDE port is enabled\n");
		goto quit;
	}

	/*
	 * Save the dma_base port addr for each interface
	 */
	for (h = 0; h < MAX_HWIFS; ++h) {
		byte s_clks, r_clks;
		ide_hwif_t *hwif = &ide_hwifs[h];
		unsigned short time;
		if (hwif->io_base == 0x1f0) {
			time = timings & 0xffff;
			if ((timings & 0x8000) == 0)	/* interface enabled? */
				continue;
			hwif->chipset = ide_triton;
			if (dma_enabled)
				init_triton_dma(hwif, bmiba);
		} else if (hwif->io_base == 0x170) {
			time = timings >> 16;
			if ((timings & 0x8000) == 0)	/* interface enabled? */
				continue;
			hwif->chipset = ide_triton;
			if (dma_enabled)
				init_triton_dma(hwif, bmiba + 8);
		} else
			continue;
示例#25
0
文件: bkm_a8.c 项目: janfj/dd-wrt
int __init
setup_sct_quadro(struct IsdnCard *card)
{
#if CONFIG_PCI
    struct IsdnCardState *cs = card->cs;
    char tmp[64];
    u_char pci_rev_id;
    u_int found = 0;
    u_int pci_ioaddr1, pci_ioaddr2, pci_ioaddr3, pci_ioaddr4, pci_ioaddr5;

    strcpy(tmp, sct_quadro_revision);
    printk(KERN_INFO "HiSax: T-Berkom driver Rev. %s\n", HiSax_getrev(tmp));
    if (cs->typ == ISDN_CTYPE_SCT_QUADRO) {
        cs->subtyp = SCT_1;	/* Preset */
    } else
        return (0);

    /* Identify subtype by para[0] */
    if (card->para[0] >= SCT_1 && card->para[0] <= SCT_4)
        cs->subtyp = card->para[0];
    else {
        printk(KERN_WARNING "HiSax: %s: Invalid subcontroller in configuration, default to 1\n",
               CardType[card->typ]);
        return (0);
    }
    if ((cs->subtyp != SCT_1) && ((sub_sys_id != PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO) ||
                                  (sub_vendor_id != PCI_VENDOR_ID_BERKOM)))
        return (0);
    if (cs->subtyp == SCT_1) {
        if (!pci_present()) {
            printk(KERN_ERR "bkm_a4t: no PCI bus present\n");
            return (0);
        }
        while ((dev_a8 = pci_find_device(PCI_VENDOR_ID_PLX,
                                         PCI_DEVICE_ID_PLX_9050, dev_a8))) {

            pci_get_sub_vendor(dev_a8,sub_vendor_id);
            pci_get_sub_system(dev_a8,sub_sys_id);
            if ((sub_sys_id == PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO) &&
                    (sub_vendor_id == PCI_VENDOR_ID_BERKOM)) {
                if (pci_enable_device(dev_a8))
                    return(0);
                pci_ioaddr1 = pci_resource_start_io(dev_a8, 1);
                pci_irq = dev_a8->irq;
                pci_bus = dev_a8->bus->number;
                pci_device_fn = dev_a8->devfn;
                found = 1;
                break;
            }
        }
        if (!found) {
            printk(KERN_WARNING "HiSax: %s (%s): Card not found\n",
                   CardType[card->typ],
                   sct_quadro_subtypes[cs->subtyp]);
            return (0);
        }
#ifdef ATTEMPT_PCI_REMAPPING
        /* HACK: PLX revision 1 bug: PLX address bit 7 must not be set */
        pcibios_read_config_byte(pci_bus, pci_device_fn,
                                 PCI_REVISION_ID, &pci_rev_id);
        if ((pci_ioaddr1 & 0x80) && (pci_rev_id == 1)) {
            printk(KERN_WARNING "HiSax: %s (%s): PLX rev 1, remapping required!\n",
                   CardType[card->typ],
                   sct_quadro_subtypes[cs->subtyp]);
            /* Restart PCI negotiation */
            pcibios_write_config_dword(pci_bus, pci_device_fn,
                                       PCI_BASE_ADDRESS_1, (u_int) - 1);
            /* Move up by 0x80 byte */
            pci_ioaddr1 += 0x80;
            pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK;
            pcibios_write_config_dword(pci_bus, pci_device_fn,
                                       PCI_BASE_ADDRESS_1, pci_ioaddr1);
            get_pcibase(dev_a8, 1) = pci_ioaddr1;
        }
#endif /* End HACK */
    }
    if (!pci_irq) {		/* IRQ range check ?? */
        printk(KERN_WARNING "HiSax: %s (%s): No IRQ\n",
               CardType[card->typ],
               sct_quadro_subtypes[cs->subtyp]);
        return (0);
    }
    pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_1, &pci_ioaddr1);
    pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_2, &pci_ioaddr2);
    pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_3, &pci_ioaddr3);
    pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_4, &pci_ioaddr4);
    pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_5, &pci_ioaddr5);
    if (!pci_ioaddr1 || !pci_ioaddr2 || !pci_ioaddr3 || !pci_ioaddr4 || !pci_ioaddr5) {
        printk(KERN_WARNING "HiSax: %s (%s): No IO base address(es)\n",
               CardType[card->typ],
               sct_quadro_subtypes[cs->subtyp]);
        return (0);
    }
    pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK;
    pci_ioaddr2 &= PCI_BASE_ADDRESS_IO_MASK;
    pci_ioaddr3 &= PCI_BASE_ADDRESS_IO_MASK;
    pci_ioaddr4 &= PCI_BASE_ADDRESS_IO_MASK;
    pci_ioaddr5 &= PCI_BASE_ADDRESS_IO_MASK;
    /* Take over */
    cs->irq = pci_irq;
    cs->irq_flags |= SA_SHIRQ;
    /* pci_ioaddr1 is unique to all subdevices */
    /* pci_ioaddr2 is for the fourth subdevice only */
    /* pci_ioaddr3 is for the third subdevice only */
    /* pci_ioaddr4 is for the second subdevice only */
    /* pci_ioaddr5 is for the first subdevice only */
    cs->hw.ax.plx_adr = pci_ioaddr1;
    /* Enter all ipac_base addresses */
    switch(cs->subtyp) {
    case 1:
        cs->hw.ax.base = pci_ioaddr5 + 0x00;
        if (sct_alloc_io(pci_ioaddr1, 128))
            return(0);
        if (sct_alloc_io(pci_ioaddr5, 64))
            return(0);
        /* disable all IPAC */
        writereg(pci_ioaddr5, pci_ioaddr5 + 4,
                 IPAC_MASK, 0xFF);
        writereg(pci_ioaddr4 + 0x08, pci_ioaddr4 + 0x0c,
                 IPAC_MASK, 0xFF);
        writereg(pci_ioaddr3 + 0x10, pci_ioaddr3 + 0x14,
                 IPAC_MASK, 0xFF);
        writereg(pci_ioaddr2 + 0x20, pci_ioaddr2 + 0x24,
                 IPAC_MASK, 0xFF);
        break;
    case 2:
        cs->hw.ax.base = pci_ioaddr4 + 0x08;
        if (sct_alloc_io(pci_ioaddr4, 64))
            return(0);
        break;
    case 3:
        cs->hw.ax.base = pci_ioaddr3 + 0x10;
        if (sct_alloc_io(pci_ioaddr3, 64))
            return(0);
        break;
    case 4:
        cs->hw.ax.base = pci_ioaddr2 + 0x20;
        if (sct_alloc_io(pci_ioaddr2, 64))
            return(0);
        break;
    }
    /* For isac and hscx data path */
    cs->hw.ax.data_adr = cs->hw.ax.base + 4;

    printk(KERN_INFO "HiSax: %s (%s) configured at 0x%.4lX, 0x%.4lX, 0x%.4lX and IRQ %d\n",
           CardType[card->typ],
           sct_quadro_subtypes[cs->subtyp],
           cs->hw.ax.plx_adr,
           cs->hw.ax.base,
           cs->hw.ax.data_adr,
           cs->irq);

    test_and_set_bit(HW_IPAC, &cs->HW_Flags);

    cs->readisac = &ReadISAC;
    cs->writeisac = &WriteISAC;
    cs->readisacfifo = &ReadISACfifo;
    cs->writeisacfifo = &WriteISACfifo;

    cs->BC_Read_Reg = &ReadHSCX;
    cs->BC_Write_Reg = &WriteHSCX;
    cs->BC_Send_Data = &hscx_fill_fifo;
    cs->cardmsg = &BKM_card_msg;
    cs->irq_func = &bkm_interrupt_ipac;

    printk(KERN_INFO "HiSax: %s (%s): IPAC Version %d\n",
           CardType[card->typ],
           sct_quadro_subtypes[cs->subtyp],
           readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ID));
    return (1);
#else
    printk(KERN_ERR "HiSax: bkm_a8 only supported on PCI Systems\n");
#endif /* CONFIG_PCI */
}
示例#26
0
/******************************************************************************
    Module initialization functions
******************************************************************************/
dev_node_t *islpci_attach(dev_locator_t * loc)
{
    u32 io;
    u16 dev_id;
    u8 bus, devfn, irq, latency_tmr;
    struct pci_dev *pci_device;
    struct net_device *nw_device;
    dev_node_t *node;
    islpci_private *private_config;
    int rvalue;
    int dma_mask = 0xffffffff;
    char firmware[256];

    // perform some initial setting checks
    if (loc->bus != LOC_PCI)
        return NULL;
    bus = loc->b.pci.bus;
    devfn = loc->b.pci.devfn;

#if VERBOSE > SHOW_ERROR_MESSAGES 
    DEBUG(SHOW_FUNCTION_CALLS, "islpci_attach(bus %d, function %d)\n",
        bus, devfn);
#endif

    // get some pci settings for verification
    pcibios_read_config_dword(bus, devfn, PCI_BASE_ADDRESS_0, &io);
    pcibios_read_config_byte(bus, devfn, PCI_INTERRUPT_LINE, &irq);
    pcibios_read_config_word(bus, devfn, PCI_DEVICE_ID, &dev_id);

	// check whether the latency timer is set correctly
    pcibios_read_config_byte(bus, devfn, PCI_LATENCY_TIMER, &latency_tmr);
#if VERBOSE > SHOW_ERROR_MESSAGES 
	DEBUG( SHOW_TRACING, "latency timer: %x\n", latency_tmr );
#endif
	if( latency_tmr < PCIDEVICE_LATENCY_TIMER_MIN )
	{
		// set the latency timer
		pcibios_write_config_byte(bus, devfn, PCI_LATENCY_TIMER, 
			PCIDEVICE_LATENCY_TIMER_VAL );
	}

    if (io &= ~3, io == 0 || irq == 0)
    {
        DEBUG(SHOW_ERROR_MESSAGES, "The ISL38XX Ethernet interface was not "
        "assigned an %s.\n" KERN_ERR "  It will not be activated.\n",
        io == 0 ? "I/O address" : "IRQ");
        return NULL;
    }
    // get pci device information by loading the pci_dev structure
    if (pci_device = pci_find_slot(bus, devfn), pci_device == NULL)
    {
        // error reading the pci device structure
        DEBUG(SHOW_ERROR_MESSAGES, "ERROR: %s could not get PCI device "
            "information \n", DRIVER_NAME );
        return NULL;
    }

    // determine what the supported DMA memory region is
    while( pci_set_dma_mask( pci_device, dma_mask ) != 0 )
    {
        // range not supported, shift the mask and check again
        if( dma_mask >>=  1, dma_mask == 0 )
        {
            // mask is zero, DMA memory not supported by PCI
            DEBUG(SHOW_ERROR_MESSAGES, "DMA Memory not supported\n" );
            return NULL;
        }
    }

#if VERBOSE > SHOW_ERROR_MESSAGES 
    DEBUG(SHOW_TRACING, "DMA Memory support mask is 0x%x \n", dma_mask );
#endif

    // setup the network device interface and its structure
    if (nw_device = islpci_probe(NULL, pci_device, (long) io, (int) irq),
        nw_device == NULL)
    {
        // error configuring the driver as a network device
        DEBUG(SHOW_ERROR_MESSAGES, "ERROR: %s could not configure "
        "network device \n", DRIVER_NAME );
        return NULL;
    }

#ifdef WDS_LINKS
    mgt_indication_handler ( DEV_NETWORK, nw_device->name, DOT11_OID_WDSLINKADD, islpci_wdslink_add_hndl );
    mgt_indication_handler ( DEV_NETWORK, nw_device->name, DOT11_OID_WDSLINKREMOVE, islpci_wdslink_del_hndl );
#endif

    // save the interrupt request line and use the remapped device base address
    // as the device identification both for uniqueness and parameter passing
    // to the interrupt handler
    private_config = nw_device->priv;
    private_config->pci_irq = irq;
    private_config->pci_dev_id = dev_id;
    private_config->device_id = private_config->remapped_device_base;
	spin_lock_init( &private_config->slock );

    // request for the interrupt before uploading the firmware
    if (rvalue = request_irq(irq, &islpci_interrupt, SA_INTERRUPT | SA_SHIRQ,
        DRIVER_NAME, private_config), rvalue != 0)
    {
        // error, could not hook the handler to the irq
        DEBUG(SHOW_ERROR_MESSAGES, "ERROR: %s could not install "
            "IRQ-handler \n", DRIVER_NAME );
        return NULL;
    }

    // select the firmware file depending on the device id, take for default
    // the 3877 firmware file
    if( dev_id == PCIDEVICE_ISL3890 )
    	strcpy( firmware, ISL3890_IMAGE_FILE );
    else
    	strcpy( firmware, ISL3877_IMAGE_FILE );

#if VERBOSE > SHOW_ERROR_MESSAGES 
    DEBUG(SHOW_TRACING, "Device %x, firmware file: %s \n", dev_id, firmware );
#endif
	
    if (isl38xx_upload_firmware( firmware, private_config->remapped_device_base,
        private_config->device_host_address  ) == -1)
    {
        // error uploading the firmware
        DEBUG(SHOW_ERROR_MESSAGES, "ERROR: %s could not upload the "
        "firmware \n", DRIVER_NAME );
        return NULL;
    }

    // finally setup the node structure with the device information
    node = kmalloc(sizeof(dev_node_t), GFP_KERNEL);
    strcpy(node->dev_name, nw_device->name);
    node->major = 0;
    node->minor = 0;
    node->next = NULL;
    MOD_INC_USE_COUNT;
    return node;
}
示例#27
0
__initfunc(int
setup_diva(struct IsdnCard *card))
{
	int bytecnt;
	u_char val;
	struct IsdnCardState *cs = card->cs;
	char tmp[64];

	strcpy(tmp, Diva_revision);
	printk(KERN_INFO "HiSax: Eicon.Diehl Diva driver Rev. %s\n", HiSax_getrev(tmp));
	if (cs->typ != ISDN_CTYPE_DIEHLDIVA)
		return(0);
	cs->hw.diva.status = 0;
	if (card->para[1]) {
		cs->hw.diva.ctrl_reg = 0;
		cs->hw.diva.cfg_reg = card->para[1];
		val = readreg(cs->hw.diva.cfg_reg + DIVA_IPAC_ADR,
			cs->hw.diva.cfg_reg + DIVA_IPAC_DATA, IPAC_ID);
		printk(KERN_INFO "Diva: IPAC version %x\n", val);
		if (val == 1) {
			cs->subtyp = DIVA_IPAC_ISA;
			cs->hw.diva.ctrl = 0;
			cs->hw.diva.isac = card->para[1] + DIVA_IPAC_DATA;
			cs->hw.diva.hscx = card->para[1] + DIVA_IPAC_DATA;
			cs->hw.diva.isac_adr = card->para[1] + DIVA_IPAC_ADR;
			cs->hw.diva.hscx_adr = card->para[1] + DIVA_IPAC_ADR;
			test_and_set_bit(HW_IPAC, &cs->HW_Flags);
		} else {
			cs->subtyp = DIVA_ISA;
			cs->hw.diva.ctrl = card->para[1] + DIVA_ISA_CTRL;
			cs->hw.diva.isac = card->para[1] + DIVA_ISA_ISAC_DATA;
			cs->hw.diva.hscx = card->para[1] + DIVA_HSCX_DATA;
			cs->hw.diva.isac_adr = card->para[1] + DIVA_ISA_ISAC_ADR;
			cs->hw.diva.hscx_adr = card->para[1] + DIVA_HSCX_ADR;
		}
		cs->irq = card->para[0];
		bytecnt = 8;
	} else {
#if CONFIG_PCI
		u_char pci_bus, pci_device_fn, pci_irq;
		u_int pci_ioaddr;

		cs->subtyp = 0;
		for (; pci_index < 0xff; pci_index++) {
			if (pcibios_find_device(PCI_VENDOR_EICON_DIEHL,
			   PCI_DIVA20_ID, pci_index, &pci_bus, &pci_device_fn)
			   == PCIBIOS_SUCCESSFUL)
				cs->subtyp = DIVA_PCI;
			else if (pcibios_find_device(PCI_VENDOR_EICON_DIEHL,
			   PCI_DIVA20_ID, pci_index, &pci_bus, &pci_device_fn)
			   == PCIBIOS_SUCCESSFUL)
			   	cs->subtyp = DIVA_PCI;
			else
				break;
			/* get IRQ */
			pcibios_read_config_byte(pci_bus, pci_device_fn,
				PCI_INTERRUPT_LINE, &pci_irq);

			/* get IO address */
			pcibios_read_config_dword(pci_bus, pci_device_fn,
				PCI_BASE_ADDRESS_2, &pci_ioaddr);
			if (cs->subtyp)
				break;
		}
		if (!cs->subtyp) {
			printk(KERN_WARNING "Diva: No PCI card found\n");
			return(0);
		}
		pci_index++;
		if (!pci_irq) {
			printk(KERN_WARNING "Diva: No IRQ for PCI card found\n");
			return(0);
		}

		if (!pci_ioaddr) {
			printk(KERN_WARNING "Diva: No IO-Adr for PCI card found\n");
			return(0);
		}
		pci_ioaddr &= ~3; /* remove io/mem flag */
		cs->hw.diva.cfg_reg = pci_ioaddr;
		cs->hw.diva.ctrl = pci_ioaddr + DIVA_PCI_CTRL;
		cs->hw.diva.isac = pci_ioaddr + DIVA_PCI_ISAC_DATA;
		cs->hw.diva.hscx = pci_ioaddr + DIVA_HSCX_DATA;
		cs->hw.diva.isac_adr = pci_ioaddr + DIVA_PCI_ISAC_ADR;
		cs->hw.diva.hscx_adr = pci_ioaddr + DIVA_HSCX_ADR;
		cs->irq = pci_irq;
		bytecnt = 32;
#else
		printk(KERN_WARNING "Diva: cfgreg 0 and NO_PCI_BIOS\n");
		printk(KERN_WARNING "Diva: unable to config DIVA PCI\n");
		return (0);
#endif /* CONFIG_PCI */
	}

	printk(KERN_INFO
		"Diva: %s card configured at 0x%x IRQ %d\n",
		(cs->subtyp == DIVA_PCI) ? "PCI" :
		(cs->subtyp == DIVA_ISA) ? "ISA" : "IPAC",
		cs->hw.diva.cfg_reg, cs->irq);
	if (check_region(cs->hw.diva.cfg_reg, bytecnt)) {
		printk(KERN_WARNING
		       "HiSax: %s config port %x-%x already in use\n",
		       CardType[card->typ],
		       cs->hw.diva.cfg_reg,
		       cs->hw.diva.cfg_reg + bytecnt);
		return (0);
	} else {
		request_region(cs->hw.diva.cfg_reg, bytecnt, "diva isdn");
	}

	reset_diva(cs);
	cs->BC_Read_Reg  = &ReadHSCX;
	cs->BC_Write_Reg = &WriteHSCX;
	cs->BC_Send_Data = &hscx_fill_fifo;
	cs->cardmsg = &Diva_card_msg;
	if (cs->subtyp == DIVA_IPAC_ISA) {
		cs->readisac  = &ReadISAC_IPAC;
		cs->writeisac = &WriteISAC_IPAC;
		cs->readisacfifo  = &ReadISACfifo_IPAC;
		cs->writeisacfifo = &WriteISACfifo_IPAC;
		val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ID);
		printk(KERN_INFO "Diva: IPAC version %x\n", val);
	} else {
		cs->hw.diva.tl.function = (void *) diva_led_handler;
		cs->hw.diva.tl.data = (long) cs;
		init_timer(&cs->hw.diva.tl);
		cs->readisac  = &ReadISAC;
		cs->writeisac = &WriteISAC;
		cs->readisacfifo  = &ReadISACfifo;
		cs->writeisacfifo = &WriteISACfifo;
		ISACVersion(cs, "Diva:");
		if (HscxVersion(cs, "Diva:")) {
			printk(KERN_WARNING
		       "Diva: wrong HSCX versions check IO address\n");
			release_io_diva(cs);
			return (0);
		}
	}
	return (1);
}