static void
iteidefix(struct dkdev_ata *l)
{
unsigned v;
/* set PCI mode and 66Mhz reference clock, disable IT8212 RAID */
v = pcicfgread(l->tag, 0x50);
pcicfgwrite(l->tag, 0x50, v & ~0x83);
/* i/o configuration, enable channels, cables, IORDY */
v = pcicfgread(l->tag, 0x40);
pcicfgwrite(l->tag, 0x40, (v & ~0xffffff) | 0x36a0f3);
}
static void
cmdidefix(struct dkdev_ata *l)
{
unsigned v;
v = pcicfgread(l->tag, 0x80);
pcicfgwrite(l->tag, 0x80, (v & ~0xff) | 0x01);
v = pcicfgread(l->tag, 0x84);
pcicfgwrite(l->tag, 0x84, (v & ~0xff) | 0x01);
v = pcicfgread(l->tag, 0xa4);
pcicfgwrite(l->tag, 0xa4, (v & ~0xffff) | 0x328a);
v = pcicfgread(l->tag, 0xb4);
pcicfgwrite(l->tag, 0xb4, (v & ~0xffff) | 0x328a);
}
static void
apoidefix(struct dkdev_ata *l)
{
unsigned v;
/* enable primary and secondary channel */
v = pcicfgread(l->tag, 0x40) & ~0x03;
pcicfgwrite(l->tag, 0x40, v | 0x03);
}
int
EtherInit(unsigned char *myadr)
{
uint32_t pcicsr;
uint16_t val;
volatile struct ex_upd *upd;
#ifndef _STANDALONE
uint32_t id;
#endif
if (pcicheck()) {
printf("pcicheck failed\n");
return 0;
}
#ifndef _STANDALONE
pcicfgread(&mytag, 0, &id);
#endif
for (excard = &excards[0]; excard->did != -1; excard++) {
#ifdef _STANDALONE
if (pcifinddev(0x10b7, excard->did, &mytag) == 0)
goto found;
#else
if (id == (0x10b7 | (excard->did << 16)))
goto found;
#endif
}
printf("no ex\n");
return 0;
found:
pcicfgread(&mytag, 0x10, &iobase);
iobase &= ~3;
#ifndef _STANDALONE
dmamem = mapmem(DMABASE, DMASIZE);
if (!dmamem)
return 0;
#endif
/* enable bus mastering in PCI command register */
if (pcicfgread(&mytag, 0x04, (int *)&pcicsr)
|| pcicfgwrite(&mytag, 0x04, pcicsr | 4)) {
printf("cannot enable DMA\n");
return 0;
}
ex_reset();
if (excard->mii)
ether_medium = ETHERMEDIUM_MII;
else {
ex_probemedia();
if (ether_medium < 0)
return 0;
}
val = ex_read_eeprom(EEPROM_OEM_ADDR0);
myethaddr[0] = val >> 8;
myethaddr[1] = val & 0xff;
val = ex_read_eeprom(EEPROM_OEM_ADDR1);
myethaddr[2] = val >> 8;
myethaddr[3] = val & 0xff;
val = ex_read_eeprom(EEPROM_OEM_ADDR2);
myethaddr[4] = val >> 8;
myethaddr[5] = val & 0xff;
memcpy(myadr, myethaddr, 6);
upd = RECVBUF_VIRT;
upd->upd_nextptr = RECVBUF_PHYS;
upd->upd_pktstatus = 1500;
upd->upd_frags[0].fr_addr = RECVBUF_PHYS + 100;
upd->upd_frags[0].fr_len = 1500 | EX_FR_LAST;
ex_init();
#if defined(_STANDALONE) && !defined(SUPPORT_NO_NETBSD)
strncpy(bi_netif.ifname, "ex", sizeof(bi_netif.ifname));
bi_netif.bus = BI_BUS_PCI;
bi_netif.addr.tag = mytag;
BI_ADD(&bi_netif, BTINFO_NETIF, sizeof(bi_netif));
#endif
return 1;
}
void *
siisata_init(unsigned tag, void *data)
{
unsigned idreg;
int n, nchan, retries/*waitforspinup*/;
struct dkdev_ata *l;
l = alloc(sizeof(struct dkdev_ata));
memset(l, 0, sizeof(struct dkdev_ata));
l->iobuf = allocaligned(512, 16);
l->tag = tag;
idreg = pcicfgread(tag, PCI_ID_REG);
l->bar[0] = pciiobase + (pcicfgread(tag, 0x10) &~ 01);
l->bar[1] = pciiobase + (pcicfgread(tag, 0x14) &~ 01);
l->bar[2] = pciiobase + (pcicfgread(tag, 0x18) &~ 01);
l->bar[3] = pciiobase + (pcicfgread(tag, 0x1c) &~ 01);
l->bar[4] = pciiobase + (pcicfgread(tag, 0x20) &~ 01);
l->bar[5] = pcicfgread(tag, 0x24) &~ 0x3ff;
if ((PCI_PRODUCT(idreg) & 0xf) == 0x2) {
/* 3112/3512 */
l->chan[0].cmd = l->bar[0];
l->chan[0].ctl = l->chan[0].alt = l->bar[1] | 02;
l->chan[0].dma = l->bar[4] + 0x0;
l->chan[1].cmd = l->bar[2];
l->chan[1].ctl = l->chan[1].alt = l->bar[3] | 02;
l->chan[1].dma = l->bar[4] + 0x8;
nchan = 2;
}
else {
/* 3114 - assume BA5 access is possible XXX */
l->chan[0].cmd = l->bar[5] + 0x080;
l->chan[0].ctl = l->chan[0].alt = (l->bar[5] + 0x088) | 02;
l->chan[1].cmd = l->bar[5] + 0x0c0;
l->chan[1].ctl = l->chan[1].alt = (l->bar[5] + 0x0c8) | 02;
l->chan[2].cmd = l->bar[5] + 0x280;
l->chan[2].ctl = l->chan[2].alt = (l->bar[5] + 0x288) | 02;
l->chan[3].cmd = l->bar[5] + 0x2c0;
l->chan[3].ctl = l->chan[3].alt = (l->bar[5] + 0x2c8) | 02;
nchan = 4;
}
/* configure PIO transfer mode */
pcicfgwrite(tag, 0x80, 0x00);
pcicfgwrite(tag, 0x84, 0x00);
for (n = 0; n < nchan; n++) {
l->presense[n] = satapresense(l, n);
if (l->presense[n] == 0) {
/* wait some seconds to power-up the drive */
for (retries = 0; retries < sata_delay[n]; retries++) {
wakeup_drive(l, n);
printf("Waiting %2d seconds for powering up "
"port %d.\r", sata_delay[n] - retries, n);
delay(1000 * 1000);
if ((l->presense[n] = satapresense(l, n)) != 0)
break;
}
putchar('\n');
if (l->presense[n] == 0) {
DPRINTF(("port %d not present\n", n));
continue;
}
}
if (atachkpwr(l, n) != ATA_PWR_ACTIVE) {
/* drive is probably sleeping, wake it up */
for (retries = 0; retries < 20; retries++) {
wakeup_drive(l, n);
DPRINTF(("port %d spinning up...\n", n));
delay(1000 * 1000);
l->presense[n] = perform_atareset(l, n);
if (atachkpwr(l, n) == ATA_PWR_ACTIVE)
break;
}
} else {
/* check to see whether soft reset works */
DPRINTF(("port %d active\n", n));
for (retries = 0; retries < 20; retries++) {
l->presense[n] = perform_atareset(l, n);
if (l->presense[n] != 0)
break;
wakeup_drive(l, n);
DPRINTF(("port %d cold-starting...\n", n));
delay(1000 * 1000);
}
}
if (l->presense[n])
printf("port %d present\n", n);
}
return l;
}
