/* ***** Functions called during driver state changes ***** */
void
BCMATTACHFN(pcicore_attach)(void *pch, char *pvars, int state)
{
pcicore_info_t *pi = (pcicore_info_t *)pch;
si_t *sih = pi->sih;
if (!PCIE_GEN1(sih)) {
if ((BCM4360_CHIP_ID == CHIPID(sih->chip)) ||
(BCM43460_CHIP_ID == CHIPID(sih->chip)) ||
(BCM4350_CHIP_ID == CHIPID(sih->chip)) ||
(BCM4352_CHIP_ID == CHIPID(sih->chip)) ||
(BCM4335_CHIP_ID == CHIPID(sih->chip)))
pi->pcie_reqsize = PCIE_CAP_DEVCTRL_MRRS_1024B;
return;
}
if (PCIEGEN1_ASPM(sih)) {
if (((sih->boardvendor == VENDOR_APPLE) &&
((uint8)getintvar(pvars, "sromrev") == 4) &&
((uint8)getintvar(pvars, "boardrev") <= 0x71)) ||
((uint32)getintvar(pvars, "boardflags2") & BFL2_PCIEWAR_OVR)) {
pi->pcie_war_aspm_ovr = PCIE_ASPM_DISAB;
} else {
pi->pcie_war_aspm_ovr = PCIE_ASPM_ENAB;
}
}
pi->pcie_reqsize = PCIE_CAP_DEVCTRL_MRRS_128B;
if (BCM4331_CHIP_ID == CHIPID(sih->chip))
pi->pcie_reqsize = PCIE_CAP_DEVCTRL_MRRS_512B;
bzero(pi->pcie_configspace, PCI_CONFIG_SPACE_SIZE);
/* These need to happen in this order only */
pcie_war_polarity(pi);
pcie_war_serdes(pi);
pcie_war_aspm_clkreq(pi);
pcie_clkreq_upd(pi, state);
pcie_war_pmebits(pi);
/* Alter default TX drive strength setting */
if (sih->boardvendor == VENDOR_APPLE) {
if (sih->boardtype == 0x8d)
/* change the TX drive strength to max */
pcicore_pcieserdesreg(pch, MDIO_DEV_TXCTRL0, 0x18, 0xff, 0x7f);
else if (PCIE_DRIVE_STRENGTH_OVERRIDE(sih))
/* change the drive strength to 700mv */
pcicore_pcieserdesreg(pch, MDIO_DEV_TXCTRL0, 0x18, 0xff, 0x70);
}
}
/* ***** Functions called during driver state changes ***** */
void
pcicore_attach(void *pch, char *pvars, int state)
{
pcicore_info_t *pi = (pcicore_info_t *)pch;
si_t *sih = pi->sih;
/* Determine if this board needs override */
pi->pcie_war_aspm_ovr = ((uint32)getintvar(pvars, "boardflags2") & BFL2_PCIEWAR_OVR);
/* These need to happen in this order only */
pcie_war_polarity(pi);
pcie_war_serdes(pi);
pcie_war_aspm_clkreq(pi);
pcie_clkreq_upd(pi, state);
}
