static int axiemac_miiphy_write(const char *devname, uchar addr,
uchar reg, ushort val)
{
struct eth_device *dev = eth_get_dev();
debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val);
return phywrite(dev, addr, reg, val);
}
static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
int reg, u16 value)
{
struct zynq_gem_priv *priv = bus->priv;
debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
return phywrite(priv, addr, reg, value);
}
static int zynq_gem_miiphy_write(const char *devname, uchar addr,
uchar reg, ushort val)
{
struct eth_device *dev = eth_get_dev();
debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
return phywrite(dev, addr, reg, val);
}
void at91rm9200_emac_init_hw(at91rm9200_emac_softc_t *sc)
{
int i;
/* Configure shared pins for Ethernet, not GPIO */
PIOA_REG(PIO_PDR) = ( BIT7 | /* tx clock */
BIT8 | /* tx enable */
BIT9 | /* tx data 0 */
BIT10 | /* tx data 1 */
BIT11 | /* carrier sense */
BIT12 | /* rx data 0 */
BIT13 | /* rx data 1 */
BIT14 | /* rx error */
BIT15 | /* MII clock */
BIT16 ); /* MII data */
PIOB_REG(PIO_PDR) = ( BIT12 | /* tx data 2 */
BIT13 | /* tx data 3 */
BIT14 | /* tx error */
BIT15 | /* rx data 2 */
BIT16 | /* rx data 3 */
BIT17 | /* rx data valid */
BIT18 | /* rx collistion */
BIT19 ); /* rx clock */
PIOB_REG(PIO_BSR) = ( BIT12 | /* tx data 2 */
BIT13 | /* tx data 3 */
BIT14 | /* tx error */
BIT15 | /* rx data 2 */
BIT16 | /* rx data 3 */
BIT17 | /* rx data valid */
BIT18 | /* rx collistion */
BIT19 ); /* rx clock */
/* Enable the clock to the EMAC */
PMC_REG(PMC_PCER) |= PMC_PCR_PID_EMAC;
/* initialize our receive buffer descriptors */
for (i = 0; i < NUM_RXBDS-1; i++) {
rxbuf_hdrs[i].address = (unsigned long)(&rxbuf[i * RX_BUFFER_SIZE]);
rxbuf_hdrs[i].status = 0x00000000;
}
/* last one needs the wrapbit set as well */
rxbuf_hdrs[i].address = ((unsigned long)(&rxbuf[i * RX_BUFFER_SIZE]) |
RXBUF_ADD_WRAP);
rxbuf_hdrs[i].status = 0x00000000;
/* point to our receive buffer queue */
EMAC_REG(EMAC_RBQP) = (unsigned long)rxbuf_hdrs;
/* clear any left over status bits */
EMAC_REG(EMAC_RSR) &= ~(EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA);
/* set the MII clock divder to MCK/64 */
EMAC_REG(EMAC_CFG) &= EMAC_CFG_CLK_MASK;
EMAC_REG(EMAC_CFG) = (EMAC_CFG_CLK_64 | EMAC_CFG_BIG | EMAC_CFG_FD);
/* enable the MII interface */
EMAC_REG(EMAC_CTL) = EMAC_CTL_MPE;
#if csb637
{
int timeout;
uint32_t emac_link_status;
#if defined(PHY_DBG)
printk("EMAC: Getting Link Status.\n");
#endif
/* read the PHY ID registers */
emac_link_status = phyread(0x02);
emac_link_status = phyread(0x03);
/* Get the link status - wait for done with a timeout */
for (timeout = 10000 ; timeout ; ) {
for (i = 0; i < 100; i++)
;
emac_link_status = phyread(0x01);
if (!(emac_link_status & PHY_STAT_AUTO_NEG_ABLE)) {
#if defined(PHY_DBG)
printk("EMAC: PHY is unable to Auto-Negotatiate!\n");
#endif
timeout = 0;
break;
}
if (emac_link_status & PHY_STAT_AUTO_NEG_DONE) {
#if defined(PHY_DBG)
printk("EMAC: Auto-Negotiate Complete, Link = ");
#endif
break;
}
timeout-- ;
}
if (!timeout) {
#if defined(PHY_DBG)
printk(
"EMAC: Auto-Negotatiate Failed, Status = 0x%04lx!\n"
"EMAC: Initialization Halted.\n",
emac_link_status
);
#endif
/* if autonegotiation fails, just force to 10HD... */
emac_link_status = PHY_STAT_10BASE_HDX;
}
/* Set SPD and FD based on the return link status */
if (emac_link_status & (PHY_STAT_100BASE_X_FDX | PHY_STAT_100BASE_X_HDX)){
EMAC_REG(EMAC_CFG) |= EMAC_CFG_SPD;
#if defined(PHY_DBG)
printk("100MBIT, ");
#endif
} else {
EMAC_REG(EMAC_CFG) &= ~EMAC_CFG_SPD;
#if defined(PHY_DBG)
printk("10MBIT, ");
#endif
}
if (emac_link_status & (PHY_STAT_100BASE_X_FDX | PHY_STAT_10BASE_FDX)) {
EMAC_REG(EMAC_CFG) |= EMAC_CFG_FD;
#if defined(PHY_DBG)
printk("Full Duplex.\n");
#endif
} else {
EMAC_REG(EMAC_CFG) &= ~EMAC_CFG_FD;
#if defined(PHY_DBG)
printk("Half Duplex.\n");
#endif
}
/* Set PHY LED modes. Traffic Meter Mode for ACTLED
* Set Bit 6 - Traffic Mode on
*/
phywrite(0x1b, PHY_AUX_MODE2_TRAFFIC_LED);
}
#else
/* must be csb337 */
/* Set PHY LED2 to combined Link/Activity and enable pulse stretching */
phywrite( 18, 0x0d0a );
#endif
#if 0
EMAC_REG(EMAC_MAN) = (0x01 << 30 | /* Start of Frame Delimiter */
0x01 << 28 | /* Operation, 0x01 = Write */
0x00 << 23 | /* Phy Number */
0x14 << 18 | /* Phy Register */
0x02 << 16 | /* must be 0x02 */
0x0D0A); /* Write data (0x0000 if read) */
#endif
} /* at91rm9200_emac_init_hw() */
static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad,
int reg, u16 value)
{
debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
return phywrite(bus->priv, addr, reg, value);
}
/* Setting axi emac and phy to proper setting */
static int setup_phy(struct udevice *dev)
{
u16 temp;
u32 speed, emmc_reg, ret;
struct axidma_priv *priv = dev_get_priv(dev);
struct axi_regs *regs = priv->iobase;
struct phy_device *phydev = priv->phydev;
if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
/*
* In SGMII cases the isolate bit might set
* after DMA and ethernet resets and hence
* check and clear if set.
*/
ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp);
if (ret)
return 0;
if (temp & BMCR_ISOLATE) {
temp &= ~BMCR_ISOLATE;
ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp);
if (ret)
return 0;
}
}
if (phy_startup(phydev)) {
printf("axiemac: could not initialize PHY %s\n",
phydev->dev->name);
return 0;
}
if (!phydev->link) {
printf("%s: No link.\n", phydev->dev->name);
return 0;
}
switch (phydev->speed) {
case 1000:
speed = XAE_EMMC_LINKSPD_1000;
break;
case 100:
speed = XAE_EMMC_LINKSPD_100;
break;
case 10:
speed = XAE_EMMC_LINKSPD_10;
break;
default:
return 0;
}
/* Setup the emac for the phy speed */
emmc_reg = readl(®s->emmc);
emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
emmc_reg |= speed;
/* Write new speed setting out to Axi Ethernet */
writel(emmc_reg, ®s->emmc);
/*
* Setting the operating speed of the MAC needs a delay. There
* doesn't seem to be register to poll, so please consider this
* during your application design.
*/
udelay(1);
return 1;
}
