static void pic32_spi_hw_init(struct pic32_spi_priv *priv)
{
u32 val;
/* disable module */
pic32_spi_disable(priv);
val = readl(&priv->regs->ctrl);
/* enable enhanced fifo of 128bit deep */
val |= PIC32_SPI_CTRL_ENHBUF;
priv->fifo_depth = 16;
/* disable framing mode */
val &= ~PIC32_SPI_CTRL_FRMEN;
/* enable master mode */
val |= PIC32_SPI_CTRL_MSTEN;
/* select clk source */
val &= ~PIC32_SPI_CTRL_MCLKSEL;
/* set manual /CS mode */
val &= ~PIC32_SPI_CTRL_MSSEN;
writel(val, &priv->regs->ctrl);
/* clear rx overflow indicator */
writel(PIC32_SPI_STAT_RX_OV, &priv->regs->status.clr);
}
static int pic32_spi_unprepare_hardware(struct spi_master *master)
{
struct pic32_spi *pic32s = spi_master_get_devdata(master);
pic32_spi_disable(pic32s);
return 0;
}
static int pic32_spi_release_bus(struct udevice *slave)
{
struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
/* disable chip */
pic32_spi_disable(priv);
return 0;
}
static int pic32_spi_remove(struct platform_device *pdev)
{
struct pic32_spi *pic32s;
pic32s = platform_get_drvdata(pdev);
pic32_spi_disable(pic32s);
clk_disable_unprepare(pic32s->clk);
pic32_spi_dma_unprep(pic32s);
return 0;
}
static void pic32_spi_hw_init(struct pic32_spi *pic32s)
{
u32 ctrl;
/* disable hardware */
pic32_spi_disable(pic32s);
ctrl = readl(&pic32s->regs->ctrl);
/* enable enhanced fifo of 128bit deep */
ctrl |= CTRL_ENHBUF;
pic32s->fifo_n_byte = 16;
/* disable framing mode */
ctrl &= ~CTRL_FRMEN;
/* enable master mode while disabled */
ctrl |= CTRL_MSTEN;
/* set tx fifo threshold interrupt */
ctrl &= ~(0x3 << CTRL_TX_INT_SHIFT);
ctrl |= (TX_FIFO_HALF_EMPTY << CTRL_TX_INT_SHIFT);
/* set rx fifo threshold interrupt */
ctrl &= ~(0x3 << CTRL_RX_INT_SHIFT);
ctrl |= (RX_FIFO_NOT_EMPTY << CTRL_RX_INT_SHIFT);
/* select clk source */
ctrl &= ~CTRL_MCLKSEL;
/* set manual /CS mode */
ctrl &= ~CTRL_MSSEN;
writel(ctrl, &pic32s->regs->ctrl);
/* enable error reporting */
ctrl = CTRL2_TX_UR_EN | CTRL2_RX_OV_EN | CTRL2_FRM_ERR_EN;
writel(ctrl, &pic32s->regs->ctrl2_set);
}
