void gtp_set_int_value(int status)
{
long unsigned int config;
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC,0xFFFF);
pin_config_get(SUNXI_PINCTRL,irq_pin_name,&config);
if (1 != SUNXI_PINCFG_UNPACK_VALUE(config)){
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC,1);
pin_config_set(SUNXI_PINCTRL,irq_pin_name,config);
}
__gpio_set_value(CTP_IRQ_NUMBER, status);
}
static int sunxi_pin_resource_req(struct platform_device *pdev)
{
script_item_u *pin_list;
int pin_count;
int pin_index;
pr_warn("device [%s] pin resource request enter\n", dev_name(&pdev->dev));
/* get pin sys_config info */
pin_count = script_get_pio_list("lcd0", &pin_list);
if (pin_count == 0) {
/* "lcd0" have no pin configuration */
return -EINVAL;
}
/* request pin individually */
for (pin_index = 0; pin_index < pin_count; pin_index++) {
struct gpio_config *pin_cfg = &(pin_list[pin_index].gpio);
char pin_name[SUNXI_PIN_NAME_MAX_LEN];
unsigned long config;
if (IS_AXP_PIN(pin_cfg->gpio)) {
/* valid pin of axp-pinctrl,
* config pin attributes individually.
*/
sunxi_gpio_to_name(pin_cfg->gpio, pin_name);
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, pin_cfg->mul_sel);
pin_config_set(AXP_PINCTRL, pin_name, config);
if (pin_cfg->data != GPIO_DATA_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DAT, pin_cfg->data);
pin_config_set(AXP_PINCTRL, pin_name, config);
}
} else {
/* valid pin of sunxi-pinctrl,
* config pin attributes individually.
*/
sunxi_gpio_to_name(pin_cfg->gpio, pin_name);
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, pin_cfg->mul_sel);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
if (pin_cfg->pull != GPIO_PULL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_PUD, pin_cfg->pull);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg->drv_level != GPIO_DRVLVL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DRV, pin_cfg->drv_level);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg->data != GPIO_DATA_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DAT, pin_cfg->data);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
}
}
pr_debug("device [%s] pin resource request ok\n", dev_name(&pdev->dev));
return 0;
}
__s32 NAND_PIOFuncChange_REc(__u32 nand_index, __u32 en)
{
unsigned int ndfc_version;
script_item_u *pin_list;
int pin_count;
int pin_index;
ndfc_version = NAND_GetNdfcVersion();
if (ndfc_version == 1) {
printk("NAND_PIOFuncChange_EnDQScREc: invalid ndfc version!\n");
return 0;
}
/* get pin sys_config info */
if(nand_index == 0)
pin_count = script_get_pio_list("nand0", &pin_list);
else if(nand_index == 1)
pin_count = script_get_pio_list("nand1", &pin_list);
else {
pin_count = 0;
printk("NAND_PIOFuncChange_DQSc, wrong nand index %d\n", nand_index);
}
if (pin_count == 0) {
/* "lcd0" have no pin configuration */
return 0;
}
{
struct gpio_config *pin_cfg;
char pin_name[SUNXI_PIN_NAME_MAX_LEN];
unsigned long config;
/* change pin func from CE2 to REc */
pin_index = 17;
if (pin_index > pin_count) {
printk("NAND_PIOFuncChange_EnREc: pin_index error, %d/%d\n", pin_index, pin_count);
return -1;
}
pin_cfg = &(pin_list[pin_index].gpio);
sunxi_gpio_to_name(pin_cfg->gpio, pin_name);
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, pin_cfg->mul_sel);
if (en) {
if ((config & 0xffff) == 0x3)
printk("REc has already been enabled!\n");
else if ((config & 0xffff) == 0x2){
config &= ~(0xffff);
config |= 0x3;
pin_config_set(SUNXI_PINCTRL, pin_name, config);
} else {
printk("NAND_PIOFuncChange_EnREc: wrong pin func status: %d %d\n", pin_index, (__u32)(config & 0xffff));
}
} else {
if ((config & 0xffff) == 0x2)
printk("REc has already been disenabled!\n");
else if ((config & 0xffff) == 0x3){
config &= ~(0xffff);
config |= 0x3;
pin_config_set(SUNXI_PINCTRL, pin_name, config);
} else {
printk("NAND_PIOFuncChange_EnREc: wrong pin func status: %d %d\n", pin_index, (__u32)(config & 0xffff));
}
}
}
return 0;
}
void NAND_PIORequest(__u32 nand_index)
{
script_item_u *pin_list;
int pin_count;
int pin_index;
/* get pin sys_config info */
if(nand_index == 0)
{
pin_count = script_get_pio_list("nand0_para", &pin_list);
printk("pin count:%d \n",pin_count);
}
else if(nand_index == 1)
pin_count = script_get_pio_list("nand1_para", &pin_list);
else
return ;
if (pin_count == 0) {
/* "lcd0" have no pin configuration */
printk("pin count 0\n");
return ;
}
#if 0
/* get pin sys_config info */
if(nand_index == 0)
pin_count = script_get_pio_list("nand0", &pin_list);
else if(nand_index == 0)
pin_count = script_get_pio_list("nand1", &pin_list);
else
return ;
if (pin_count == 0) {
/* "lcd0" have no pin configuration */
printk("pin count 0\n");
return ;
}
#endif
/* request pin individually */
for (pin_index = 0; pin_index < pin_count; pin_index++) {
struct gpio_config *pin_cfg = &(pin_list[pin_index].gpio);
char pin_name[SUNXI_PIN_NAME_MAX_LEN];
unsigned long config;
/* valid pin of sunxi-pinctrl,
* config pin attributes individually.
*/
sunxi_gpio_to_name(pin_cfg->gpio, pin_name);
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, pin_cfg->mul_sel);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
if (pin_cfg->pull != GPIO_PULL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_PUD, pin_cfg->pull);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg->drv_level != GPIO_DRVLVL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DRV, pin_cfg->drv_level);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg->data != GPIO_DATA_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DAT, pin_cfg->data);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
}
return ;
}
int os_gpio_set(struct vfe_gpio_cfg *gpio_list, __u32 group_count_max)
{
#ifdef VFE_GPIO
int ret = 0;
struct gpio_config pin_cfg;
char pin_name[32];
__u32 config;
if(gpio_list == NULL)
return 0;
if(gpio_list->gpio == GPIO_INDEX_INVALID)
return 0;
pin_cfg.gpio = gpio_list->gpio;
pin_cfg.mul_sel = gpio_list->mul_sel;
pin_cfg.pull = gpio_list->pull;
pin_cfg.drv_level = gpio_list->drv_level;
pin_cfg.data = gpio_list->data;
if (!IS_AXP_PIN(pin_cfg.gpio)) {
/* valid pin of sunxi-pinctrl,
* config pin attributes individually.
*/
sunxi_gpio_to_name(pin_cfg.gpio, pin_name);
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, pin_cfg.mul_sel);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
if (pin_cfg.pull != GPIO_PULL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_PUD, pin_cfg.pull);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg.drv_level != GPIO_DRVLVL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DRV, pin_cfg.drv_level);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg.data != GPIO_DATA_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DAT, pin_cfg.data);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
} else if (IS_AXP_PIN(pin_cfg.gpio)) {
/* valid pin of axp-pinctrl,
* config pin attributes individually.
*/
sunxi_gpio_to_name(pin_cfg.gpio, pin_name);
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, pin_cfg.mul_sel);
pin_config_set(AXP_PINCTRL, pin_name, config);
if (pin_cfg.data != GPIO_DATA_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DAT, pin_cfg.data);
pin_config_set(AXP_PINCTRL, pin_name, config);
}
} else {
vfe_warn("invalid pin [%d] from sys-config\n", pin_cfg.gpio);
return -1;
}
return ret;
#else
return 0;
#endif
}
int fimc_is_companion_open(struct fimc_is_device_companion *device)
{
int ret = 0;
struct fimc_is_core *core;
/* Workaround for Host to use ISP-SPI. Will be removed later.*/
struct fimc_is_spi_gpio *spi_gpio;
static char companion_fw_name[100];
static char master_setf_name[100];
static char mode_setf_name[100];
static char fw_name[100];
static char setf_name[100];
BUG_ON(!device);
core = (struct fimc_is_core *)dev_get_drvdata(fimc_is_dev);
spi_gpio = &core->spi_gpio;
if (test_bit(FIMC_IS_COMPANION_OPEN, &device->state)) {
err("already open");
ret = -EMFILE;
goto p_err;
}
device->companion_status = FIMC_IS_COMPANION_OPENNING;
#if defined(CONFIG_PM_RUNTIME)
pm_runtime_get_sync(&device->pdev->dev);
#endif
ret = fimc_is_sec_fw_sel(core, &device->pdev->dev, fw_name, setf_name, 0);
if (ret < 0) {
err("failed to select firmware (%d)", ret);
goto p_err;
}
ret = fimc_is_sec_concord_fw_sel(core, &device->pdev->dev, companion_fw_name, master_setf_name, mode_setf_name, 0);
/* TODO: loading firmware */
fimc_is_s_int_comb_isp(core, false, INTMR2_INTMCIS22);
// Workaround for Host to use ISP-SPI. Will be removed later.
/* set pin output for Host to use SPI*/
pin_config_set(FIMC_IS_SPI_PINNAME, spi_gpio->spi_ssn,
PINCFG_PACK(PINCFG_TYPE_FUNC, FUNC_OUTPUT));
fimc_is_set_spi_config(spi_gpio, FIMC_IS_SPI_FUNC, false);
if (fimc_is_comp_is_valid(core) == 0) {
ret = fimc_is_comp_loadfirm(core);
if (ret) {
err("fimc_is_comp_loadfirm() fail");
goto p_err;
}
ret = fimc_is_comp_loadcal(core);
if (ret) {
err("fimc_is_comp_loadcal() fail");
}
if(core->fan53555_client != NULL)
fimc_is_power_binning(core);
ret = fimc_is_comp_loadsetf(core);
if (ret) {
err("fimc_is_comp_loadsetf() fail");
goto p_err;
}
}
// Workaround for Host to use ISP-SPI. Will be removed later.
/* Set SPI pins to low before changing pin function */
pin_config_set(FIMC_IS_SPI_PINNAME, spi_gpio->spi_sclk,
PINCFG_PACK(PINCFG_TYPE_DAT, 0));
pin_config_set(FIMC_IS_SPI_PINNAME, spi_gpio->spi_ssn,
PINCFG_PACK(PINCFG_TYPE_DAT, 0));
pin_config_set(FIMC_IS_SPI_PINNAME, spi_gpio->spi_miso,
PINCFG_PACK(PINCFG_TYPE_DAT, 0));
pin_config_set(FIMC_IS_SPI_PINNAME, spi_gpio->spi_mois,
PINCFG_PACK(PINCFG_TYPE_DAT, 0));
/* Set pin function for A5 to use SPI */
pin_config_set(FIMC_IS_SPI_PINNAME, spi_gpio->spi_ssn,
PINCFG_PACK(PINCFG_TYPE_FUNC, 2));
set_bit(FIMC_IS_COMPANION_OPEN, &device->state);
device->companion_status = FIMC_IS_COMPANION_OPENDONE;
fimc_is_companion_wakeup(device);
p_err:
info("[COMP:D] %s(%d)status(%d)\n", __func__, ret,device->companion_status);
return ret;
}
static int sunxi_arisc_pin_cfg(struct platform_device *pdev)
{
script_item_u script_val;
script_item_value_type_e type;
script_item_u *pin_list;
int pin_count = 0;
int pin_index = 0;
struct gpio_config *pin_cfg;
char pin_name[SUNXI_PIN_NAME_MAX_LEN];
unsigned long config;
ARISC_INF("device [%s] pin resource request enter\n", dev_name(&pdev->dev));
/*
* request arisc resources:
* p2wi/rsb gpio...
*/
/* get pin sys_config info */
#if defined CONFIG_ARCH_SUN8IW1P1
pin_count = script_get_pio_list ("s_p2twi0", &pin_list);
#elif (defined CONFIG_ARCH_SUN8IW3P1) || (defined CONFIG_ARCH_SUN8IW5P1) || (defined CONFIG_ARCH_SUN8IW6P1)
pin_count = script_get_pio_list ("s_rsb0", &pin_list);
#elif defined CONFIG_ARCH_SUN9IW1P1
pin_count = script_get_pio_list ("s_rsb0", &pin_list);
#else
#error "please select a platform\n"
#endif
if (pin_count == 0) {
/* "s_p2twi0" or "s_rsb0" have no pin configuration */
ARISC_WRN("arisc s_p2twi0/s_rsb0 have no pin configuration\n");
return -EINVAL;
}
/* request pin individually */
for (pin_index = 0; pin_index < pin_count; pin_index++) {
pin_cfg = &(pin_list[pin_index].gpio);
/* valid pin of sunxi-pinctrl, config pin attributes individually.*/
sunxi_gpio_to_name(pin_cfg->gpio, pin_name);
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, pin_cfg->mul_sel);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
if (pin_cfg->pull != GPIO_PULL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_PUD, pin_cfg->pull);
pin_config_set (SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg->drv_level != GPIO_DRVLVL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DRV, pin_cfg->drv_level);
pin_config_set (SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg->data != GPIO_DATA_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DAT, pin_cfg->data);
pin_config_set (SUNXI_PINCTRL, pin_name, config);
}
}
/*
* request arisc resources:
* uart gpio...
*/
type = script_get_item("s_uart0", "s_uart_used", &script_val);
if (SCIRPT_ITEM_VALUE_TYPE_INT != type) {
ARISC_WRN("sys_config.fex have no arisc s_uart0 config!");
script_val.val = 0;
}
if (script_val.val) {
pin_count = script_get_pio_list ("s_uart0", &pin_list);
if (pin_count == 0) {
/* "s_uart0" have no pin configuration */
ARISC_WRN("arisc s_uart0 have no pin configuration\n");
return -EINVAL;
}
/* request pin individually */
for (pin_index = 0; pin_index < pin_count; pin_index++) {
pin_cfg = &(pin_list[pin_index].gpio);
/* valid pin of sunxi-pinctrl, config pin attributes individually.*/
sunxi_gpio_to_name(pin_cfg->gpio, pin_name);
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, pin_cfg->mul_sel);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
if (pin_cfg->pull != GPIO_PULL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_PUD, pin_cfg->pull);
pin_config_set (SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg->drv_level != GPIO_DRVLVL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DRV, pin_cfg->drv_level);
pin_config_set (SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg->data != GPIO_DATA_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DAT, pin_cfg->data);
pin_config_set (SUNXI_PINCTRL, pin_name, config);
}
}
}
ARISC_INF("arisc uart debug config [%s] [%s] : %d\n", "s_uart0", "s_uart_used", script_val.val);
/*
* request arisc resources:
* jtag gpio...
*/
type = script_get_item("s_jtag0", "s_jtag_used", &script_val);
if (SCIRPT_ITEM_VALUE_TYPE_INT != type) {
ARISC_WRN("sys_config.fex have no arisc s_jtag0 config!");
script_val.val = 0;
}
if (script_val.val) {
pin_count = script_get_pio_list ("s_jtag0", &pin_list);
if (pin_count == 0) {
/* "s_jtag0" have no pin configuration */
ARISC_WRN("arisc s_jtag0 have no pin configuration\n");
return -EINVAL;
}
/* request pin individually */
for (pin_index = 0; pin_index < pin_count; pin_index++) {
pin_cfg = &(pin_list[pin_index].gpio);
/* valid pin of sunxi-pinctrl, config pin attributes individually.*/
sunxi_gpio_to_name(pin_cfg->gpio, pin_name);
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, pin_cfg->mul_sel);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
if (pin_cfg->pull != GPIO_PULL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_PUD, pin_cfg->pull);
pin_config_set (SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg->drv_level != GPIO_DRVLVL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DRV, pin_cfg->drv_level);
pin_config_set (SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg->data != GPIO_DATA_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DAT, pin_cfg->data);
pin_config_set (SUNXI_PINCTRL, pin_name, config);
}
}
}
ARISC_INF("arisc jtag debug config [%s] [%s] : %d\n", "s_jtag0", "s_jtag_used", script_val.val);
ARISC_INF("device [%s] pin resource request ok\n", dev_name(&pdev->dev));
return 0;
}