static int mddi_nt35560_lcd_on(struct platform_device *pdev)
{
printk("%s \n",__func__);
//Remux the reset pin to output
pinmux_config("LCD_RESET", PINMUX_CONFIG_ACTIVE);
pinmux_config("LCD_TE", PINMUX_CONFIG_ACTIVE);
//Reset (stay low for more than 3 ms)
gpio_set_value(GPIO_LCD_RESET, 0);
msleep(20);
gpio_set_value(GPIO_LCD_RESET, 1);
msleep(20);
//Sleep out
mddi_queue_register_write(0x1100, 0x00, FALSE, 0);
/*
* Spec sugggests 10ms or more.
* Reality indicates 100ms provides a good buffer
* for internal MTP programming.
*/
msleep(100);
//Display on
mddi_queue_register_write(0x2900, 0x00, FALSE, 0);
//Turn on Vsync on 700th line
mddi_queue_register_write(0x4400, 0x02, FALSE, 0);
mddi_queue_register_write(0x4401, 0xBC, FALSE, 0);
mddi_queue_register_write(0x3500, 0x00, FALSE, 0);
if (mddi_nt35560_pdata && mddi_nt35560_pdata->flip) {
uint32_t address_mode = 0;
if (mddi_nt35560_pdata->flip & MSM_PANEL_CONFIG_FLIP_VERTICAL)
address_mode |= 0x80;
if (mddi_nt35560_pdata->flip & MSM_PANEL_CONFIG_FLIP_HORIZONTAL)
address_mode |= 0x40;
mddi_queue_register_write(0x3600, address_mode, FALSE, 0);
}
return 0;
}
static int mddi_nt35560_lcd_off(struct platform_device *pdev)
{
printk("%s \n",__func__);
gpio_set_value(GPIO_LCD_RESET, 0);
mddi_queue_register_write(0x3400, 0x00, FALSE, 0);
//Display off
mddi_queue_register_write(0x2800, 0x00, FALSE, 0);
//Sleep
mddi_queue_register_write(0x1000, 0x00, FALSE, 0);
//Deep sleep
mddi_queue_register_write(0x4F00, 0x01, FALSE, 0);
//Remux the reset pin to input
pinmux_config("LCD_RESET", PINMUX_CONFIG_SLEEP);
pinmux_config("LCD_TE", PINMUX_CONFIG_SLEEP);
return 0;
}
void eic_irq_init(uint8_t pin, pinmux_t *pinmux, extint_t *extint)
{
pinmux_config(pin, pinmux);
/* Get a pointer to the module hardware instance */
Eic *const eic[EIC_INST_NUM] = EIC_INSTS;
Eic *const eics = eic[extint->channel/32];
uint32_t config_pos = (4 * (extint->channel % 8));
uint32_t new_config;
/* Determine the channel's new edge detection configuration */
new_config = (extint->detect << EIC_CONFIG_SENSE0_Pos) | EIC_CONFIG_FILTEN0;
/* Clear the existing and set the new channel configuration */
eics->CONFIG[extint->channel / 8].reg = (eics->CONFIG[extint->channel / 8].reg & \
((EIC_CONFIG_SENSE0_Msk | EIC_CONFIG_FILTEN0) << config_pos)) | \
(new_config << config_pos);
/* Set the channel's new wake up mode setting */
eics->WAKEUP.reg |= (1UL << extint->channel);
extint_enable_irq(extint->channel);
}
void usart_init(uint32_t baudrate)
{
Sercom *const hw = UART_MODULE;
pinmux_t config;
/* Get a pointer to the hardware module instance */
SercomUsart *const usart_hw = &(hw->USART);
while(usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST){
/* The module is busy resetting itself */
}
while(usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE){
/* Check the module is enabled */
}
/* Turn on module in PM */
PM->APBCMASK.reg |= UART_PM_MODULE;
/* Set up the GCLK for the module */
gclk_chan_config(UART_MODULE_GCLK, UART_GCLK);
gclk_enable(UART_MODULE_GCLK);
gclk_chan_config(SERCOM_GCLK_ID, UART_GCLK);
gclk_enable(SERCOM_GCLK_ID);
/* Configure the SERCOM pins according to the configuration */
config.dir = PORT_PIN_DIR_INPUT;
config.pull = PORT_PIN_PULLNONE;
config.mux_loc = UART_TX_MUX_PIN & 0xFFFF;
pinmux_config(UART_TX_PIN, &config);
config.mux_loc = UART_RX_MUX_PIN & 0xFFFF;
pinmux_config(UART_RX_PIN, &config);
/* Wait until synchronization is complete */
while(usart_hw->SYNCBUSY.reg);
/*Set baud val */
usart_hw->BAUD.reg = baudrate;
/* Wait until synchronization is complete */
while(usart_hw->SYNCBUSY.reg);
/* Set stop bits, character size and enable transceivers */
/* Write configuration to CTRLB */
usart_hw->CTRLB.reg = USART_STOPBITS_1 | SERCOM_USART_CTRLB_CHSIZE(0);
/* Wait until synchronization is complete */
while(usart_hw->SYNCBUSY.reg);
/* Write configuration to CTRLA */
usart_hw->CTRLA.reg = USART_TRANSFER_ASYNCHRONOUSLY | SERCOM_USART_CTRLA_MODE_USART_INT_CLK |\
USART_DATAORDER_LSB | UART_SERCOM_MUX_SETTING;
/* Wait until synchronization is complete */
while(usart_hw->SYNCBUSY.reg);
/* Write configuration to CTRLA */
usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN;
/* Wait until synchronization is complete */
while(usart_hw->SYNCBUSY.reg);
/* Write configuration to CTRLA */
usart_hw->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
}
