/** * \brief Process an interrupt request on the given PIO controller. * * \param p_pio PIO controller base address. * \param ul_id PIO controller ID. */ void pio_handler_process(Pio *p_pio, uint32_t ul_id) { uint32_t status; uint32_t i; /* Read PIO controller status */ status = pio_get_interrupt_status(p_pio); status &= pio_get_interrupt_mask(p_pio); /* Check pending events */ if (status != 0) { /* Find triggering source */ i = 0; while (status != 0) { /* Source is configured on the same controller */ if (gs_interrupt_sources[i].id == ul_id) { /* Source has PIOs whose statuses have changed */ if ((status & gs_interrupt_sources[i].mask) != 0) { gs_interrupt_sources[i].handler(gs_interrupt_sources[i].id, gs_interrupt_sources[i].mask); status &= ~(gs_interrupt_sources[i].mask); } } i++; } } }
void gpio_irq(Pio *p_pio, uint32_t ul_id) { uint32_t status; uint32_t i; /* Read PIO controller status */ status = pio_get_interrupt_status(p_pio); status &= pio_get_interrupt_mask(p_pio); /* Check pending events */ if (status != 0) { /* Find triggering source */ i = 0; while (status != 0) { /* Source is configured on the same controller */ if (gpio_irq_data[i].id == ul_id) { /* Source has PIOs whose statuses have changed */ if ((status & gpio_irq_data[i].mask) != 0) { void * arg = gpio_irq_data[i].arg; /* avoids undefined order of access to volatiles */ gpio_irq_data[i].handler(arg); status &= ~(gpio_irq_data[i].mask); } } i++; if (i >= MAX_INTERRUPT_SOURCES) { break; } } } }
//done void PIOA_Handler (void) { ButtonStatus = pio_get_interrupt_status(PIOA); ButtonStatus &= pio_get_interrupt_mask(PIOA); if(ButtonStatus&Push1 || ButtonStatus&Push2) xSemaphoreGiveFromISR(CMDFRAMEsem,NULL); else { sendDebugString("UpdateSemCalled\n"); xSemaphoreGiveFromISR(PIOAsem,NULL); } }
/** * \brief Initialize PIO interrupt management logic. * * \param p_pio PIO controller base address. * \param ul_irqn NVIC line number. * \param ul_priority PIO controller interrupts priority. */ void pio_handler_set_priority(Pio *p_pio, IRQn_Type ul_irqn, uint32_t ul_priority) { uint32_t bitmask = 0; bitmask = pio_get_interrupt_mask(p_pio); pio_disable_interrupt(p_pio, 0xFFFFFFFF); pio_get_interrupt_status(p_pio); NVIC_DisableIRQ(ul_irqn); NVIC_ClearPendingIRQ(ul_irqn); NVIC_SetPriority(ul_irqn, ul_priority); NVIC_EnableIRQ(ul_irqn); pio_enable_interrupt(p_pio, bitmask); }
/** * \brief Process an interrupt request on the given PIO controller. * * \param p_pio PIO controller base address. * \param ul_id PIO controller ID. */ void pio_handler_process(Pio *p_pio, uint32_t ul_id) { uint32_t status; uint32_t i; /* Read PIO controller status */ status = pio_get_interrupt_status(p_pio); status &= pio_get_interrupt_mask(p_pio); /* Check pending events */ if (status != 0) { /* Find triggering source */ i = 0; while (status != 0) { /* Source is configured on the same controller */ if (gs_interrupt_sources[i].id == ul_id) { /* Source has PIOs whose statuses have changed */ if ((status & gs_interrupt_sources[i].mask) != 0) { gs_interrupt_sources[i].handler(gs_interrupt_sources[i].id, gs_interrupt_sources[i].mask); status &= ~(gs_interrupt_sources[i].mask); } } i++; if (i >= MAX_INTERRUPT_SOURCES) { break; } } } /* Check capture events */ #if (SAM3S || SAM4S || SAM4E) if (pio_capture_enable_flag) { if (pio_capture_handler) { pio_capture_handler(p_pio); } } #endif }