/** * \brief Configures a list of Pin instances, each of which can either * hold a single pin or a group of pins, depending on the mask value; * all pins are configured by this function. The size of the array * must also be provided and is easily computed using ARRAY_SIZE * whenever its length is not known in advance. * * \param list Pointer to a list of _pin instances. * \param size Size of the _pin list (calculated using PIN_LISTSIZE). * * \return 1 if the pins have been configured properly; otherwise 0. */ uint8_t pio_configure(const struct _pin *pin_list, uint32_t size) { union _pio_cfg cfg; PioIo_group* pioiog; /* Configure pins */ while (size--) { /* Enable the PIO group if needed */ uint32_t periph_id = _pio_group_to_id(pin_list->group); assert(pin_list->group < PIO_GROUP_LENGTH); cfg.uint32_value = 0; pioiog = (PioIo_group*) _pio_configure_pins(pin_list, periph_id); if ( pin_list->attribute != PIO_DEFAULT) { cfg.bitfield.puen = (pin_list->attribute & PIO_PULLUP)? 1:0; cfg.bitfield.pden = (pin_list->attribute & PIO_PULLDOWN)? 1:0; cfg.bitfield.ifen = (pin_list->attribute & PIO_DEGLITCH)? 1:0; cfg.bitfield.ifscen = (pin_list->attribute & PIO_DEBOUNCE)? 1:0; cfg.bitfield.opd = (pin_list->attribute & PIO_OPENDRAIN)? 1:0; cfg.bitfield.schmitt =(pin_list->attribute & PIO_TRIGGER_DIS)? 1:0; switch (pin_list->attribute & PIO_DRVSTR_Msk) { case PIO_DRVSTR_HI: cfg.bitfield.drvstr = PIO_CFGR_DRVSTR_HI >> PIO_CFGR_DRVSTR_Pos; break; case PIO_DRVSTR_ME: cfg.bitfield.drvstr = PIO_CFGR_DRVSTR_ME >> PIO_CFGR_DRVSTR_Pos; break; case PIO_DRVSTR_LO: default: cfg.bitfield.drvstr = PIO_CFGR_DRVSTR_LO >> PIO_CFGR_DRVSTR_Pos; break; } switch (pin_list->attribute & PIO_EVTSEL_Msk) { case PIO_IT_HIGH_LEVEL: cfg.bitfield.evtsel = PIO_CFGR_EVTSEL_HIGH >> PIO_CFGR_EVTSEL_Pos; break; case PIO_IT_LOW_LEVEL: cfg.bitfield.evtsel = PIO_CFGR_EVTSEL_LOW >> PIO_CFGR_EVTSEL_Pos; break; case PIO_IT_BOTH_EDGE: cfg.bitfield.evtsel = PIO_CFGR_EVTSEL_BOTH >> PIO_CFGR_EVTSEL_Pos; break; case PIO_IT_RISE_EDGE: cfg.bitfield.evtsel = PIO_CFGR_EVTSEL_RISING >> PIO_CFGR_EVTSEL_Pos; break; case PIO_IT_FALL_EDGE: default: cfg.bitfield.evtsel = PIO_CFGR_EVTSEL_FALLING >> PIO_CFGR_EVTSEL_Pos; break; } } switch (pin_list->type){ case PIO_PERIPH_A: cfg.bitfield.func = PIO_CFGR_FUNC_PERIPH_A >> PIO_CFGR_FUNC_Pos; break; case PIO_PERIPH_B: cfg.bitfield.func = PIO_CFGR_FUNC_PERIPH_B >> PIO_CFGR_FUNC_Pos; break; case PIO_PERIPH_C: cfg.bitfield.func = PIO_CFGR_FUNC_PERIPH_C >> PIO_CFGR_FUNC_Pos; break; case PIO_PERIPH_D: cfg.bitfield.func = PIO_CFGR_FUNC_PERIPH_D >> PIO_CFGR_FUNC_Pos; break; case PIO_PERIPH_E: cfg.bitfield.func = PIO_CFGR_FUNC_PERIPH_E >> PIO_CFGR_FUNC_Pos; break; case PIO_PERIPH_F: cfg.bitfield.func = PIO_CFGR_FUNC_PERIPH_F >> PIO_CFGR_FUNC_Pos; break; case PIO_GENERIC: case PIO_INPUT: cfg.bitfield.dir = 0; break; case PIO_OUTPUT_0: cfg.bitfield.dir = 1; pio_clear(pin_list); break; case PIO_OUTPUT_1: cfg.bitfield.dir = 1; pio_set(pin_list); break; default: case PIO_PERIPH_G: return 0; } pioiog->PIO_MSKR = pin_list->mask; pioiog->PIO_CFGR = cfg.uint32_value; pmc_enable_peripheral(periph_id); ++pin_list; }
void board_init(void) { #ifndef CONF_BOARD_KEEP_WATCHDOG_AT_INIT /* Disable the watchdog */ WDT->WDT_MR = WDT_MR_WDDIS; #endif /* Initialize IOPORTs */ ioport_init(); /* Configure the pins connected to LED as output and set their * default initial state to high (LED off). */ ioport_set_pin_dir(LED0_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(LED0_GPIO, LED0_INACTIVE_LEVEL); ioport_set_pin_dir(LED1_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(LED1_GPIO, LED0_INACTIVE_LEVEL); /* Configure Push Button pins */ ioport_set_pin_input_mode(GPIO_PUSH_BUTTON_1, GPIO_PUSH_BUTTON_1_FLAGS, GPIO_PUSH_BUTTON_1_SENSE); #ifdef CONF_BOARD_UART_CONSOLE /* Configure UART pins */ ioport_set_pin_peripheral_mode(USART1_RXD_GPIO, USART1_RXD_FLAGS); MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4; ioport_set_pin_peripheral_mode(USART1_TXD_GPIO, USART1_TXD_FLAGS); #endif #ifdef CONF_BOARD_TWIHS0 ioport_set_pin_peripheral_mode(TWIHS0_DATA_GPIO, TWIHS0_DATA_FLAGS); ioport_set_pin_peripheral_mode(TWIHS0_CLK_GPIO, TWIHS0_CLK_FLAGS); #endif #ifdef CONF_BOARD_CAN0 /* Configure the CAN0 TX and RX pins. */ ioport_set_pin_peripheral_mode(PIN_CAN0_RX_IDX, PIN_CAN0_RX_FLAGS); ioport_set_pin_peripheral_mode(PIN_CAN0_TX_IDX, PIN_CAN0_TX_FLAGS); /* Configure the transiver0 RS & EN pins. */ ioport_set_pin_dir(PIN_CAN0_TR_RS_IDX, IOPORT_DIR_OUTPUT); ioport_set_pin_dir(PIN_CAN0_TR_EN_IDX, IOPORT_DIR_OUTPUT); #endif #ifdef CONF_BOARD_CAN1 /* Configure the CAN1 TX and RX pin. */ ioport_set_pin_peripheral_mode(PIN_CAN1_RX_IDX, PIN_CAN1_RX_FLAGS); ioport_set_pin_peripheral_mode(PIN_CAN1_TX_IDX, PIN_CAN1_TX_FLAGS); #endif #ifdef CONF_BOARD_SPI ioport_set_pin_peripheral_mode(SPI0_MISO_GPIO, SPI0_MISO_FLAGS); ioport_set_pin_peripheral_mode(SPI0_MOSI_GPIO, SPI0_MOSI_FLAGS); ioport_set_pin_peripheral_mode(SPI0_NPCS0_GPIO, SPI0_NPCS0_FLAGS); ioport_set_pin_peripheral_mode(SPI0_SPCK_GPIO, SPI0_SPCK_FLAGS); #endif #ifdef CONF_BOARD_QSPI ioport_set_pin_peripheral_mode(QSPI_QSCK_GPIO, QSPI_QSCK_FLAGS); ioport_set_pin_peripheral_mode(QSPI_QCS_GPIO, QSPI_QCS_FLAGS); ioport_set_pin_peripheral_mode(QSPI_QIO0_GPIO, QSPI_QIO0_FLAGS); ioport_set_pin_peripheral_mode(QSPI_QIO1_GPIO, QSPI_QIO1_FLAGS); ioport_set_pin_peripheral_mode(QSPI_QIO2_GPIO, QSPI_QIO2_FLAGS); ioport_set_pin_peripheral_mode(QSPI_QIO3_GPIO, QSPI_QIO3_FLAGS); #endif #ifdef CONF_BOARD_PWM_LED0 /* Configure PWM LED0 pin */ ioport_set_pin_peripheral_mode(PIN_PWM_LED0_GPIO, PIN_PWM_LED0_FLAGS); #endif #ifdef CONF_BOARD_PWM_LED1 /* Configure PWM LED1 pin */ ioport_set_pin_peripheral_mode(PIN_PWM_LED1_GPIO, PIN_PWM_LED1_FLAGS); #endif #ifdef CONF_BOARD_USART_RXD /* Configure USART RXD pin */ ioport_set_pin_peripheral_mode(USART0_RXD_GPIO, USART0_RXD_FLAGS); #endif #ifdef CONF_BOARD_USART_TXD /* Configure USART TXD pin */ ioport_set_pin_peripheral_mode(USART0_TXD_GPIO, USART0_TXD_FLAGS); #endif #ifdef CONF_BOARD_USART_SCK /* Configure USART synchronous communication SCK pin */ ioport_set_pin_peripheral_mode(PIN_USART0_SCK_IDX,PIN_USART0_SCK_FLAGS); #endif #ifdef CONF_BOARD_USART_CTS /* Configure USART synchronous communication CTS pin */ ioport_set_pin_peripheral_mode(PIN_USART0_CTS_IDX,PIN_USART0_CTS_FLAGS); #endif #ifdef CONF_BOARD_USART_RTS /* Configure USART RTS pin */ ioport_set_pin_peripheral_mode(PIN_USART0_RTS_IDX, PIN_USART0_RTS_FLAGS); #endif #ifdef CONF_BOARD_SD_MMC_HSMCI /* Configure HSMCI pins */ ioport_set_pin_peripheral_mode(PIN_HSMCI_MCCDA_GPIO, PIN_HSMCI_MCCDA_FLAGS); ioport_set_pin_peripheral_mode(PIN_HSMCI_MCCK_GPIO, PIN_HSMCI_MCCK_FLAGS); ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA0_GPIO, PIN_HSMCI_MCDA0_FLAGS); ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA1_GPIO, PIN_HSMCI_MCDA1_FLAGS); ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA2_GPIO, PIN_HSMCI_MCDA2_FLAGS); ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA3_GPIO, PIN_HSMCI_MCDA3_FLAGS); ioport_set_pin_peripheral_mode(SD_MMC_0_CD_GPIO, SD_MMC_0_CD_FLAGS); #endif #ifdef CONF_BOARD_ILI9488 /**LCD pin configure on EBI*/ pio_configure(PIN_EBI_RESET_PIO, PIN_EBI_RESET_TYPE, PIN_EBI_RESET_MASK, PIN_EBI_RESET_ATTRI); pio_configure(PIN_EBI_CDS_PIO, PIN_EBI_CDS_TYPE, PIN_EBI_CDS_MASK, PIN_EBI_CDS_ATTRI); pio_configure(PIN_EBI_DATAL_PIO, PIN_EBI_DATAL_TYPE, PIN_EBI_DATAL_MASK, PIN_EBI_DATAL_ATTRI); pio_configure(PIN_EBI_DATAH_0_PIO, PIN_EBI_DATAH_0_TYPE, PIN_EBI_DATAH_0_MASK, PIN_EBI_DATAH_0_ATTRI); pio_configure(PIN_EBI_DATAH_1_PIO, PIN_EBI_DATAH_1_TYPE, PIN_EBI_DATAH_1_MASK, PIN_EBI_DATAH_1_ATTRI); pio_configure(PIN_EBI_NWE_PIO, PIN_EBI_NWE_TYPE, PIN_EBI_NWE_MASK, PIN_EBI_NWE_ATTRI); pio_configure(PIN_EBI_NRD_PIO, PIN_EBI_NRD_TYPE, PIN_EBI_NRD_MASK, PIN_EBI_NRD_ATTRI); pio_configure(PIN_EBI_CS_PIO, PIN_EBI_CS_TYPE, PIN_EBI_CS_MASK, PIN_EBI_CS_ATTRI); pio_configure(PIN_EBI_BACKLIGHT_PIO, PIN_EBI_BACKLIGHT_TYPE, PIN_EBI_BACKLIGHT_MASK, PIN_EBI_BACKLIGHT_ATTRI); pio_set(PIN_EBI_BACKLIGHT_PIO, PIN_EBI_BACKLIGHT_MASK); #endif #if (defined CONF_BOARD_USB_PORT) # if defined(CONF_BOARD_USB_VBUS_DETECT) ioport_set_pin_dir(USB_VBUS_PIN, IOPORT_DIR_INPUT); # endif # if defined(CONF_BOARD_USB_ID_DETECT) ioport_set_pin_dir(USB_ID_PIN, IOPORT_DIR_INPUT); # endif #endif #ifdef CONF_BOARD_SDRAMC pio_configure_pin(SDRAM_BA0_PIO, SDRAM_BA0_FLAGS); pio_configure_pin(SDRAM_SDCK_PIO, SDRAM_SDCK_FLAGS); pio_configure_pin(SDRAM_SDCKE_PIO, SDRAM_SDCKE_FLAGS); pio_configure_pin(SDRAM_SDCS_PIO, SDRAM_SDCS_FLAGS); pio_configure_pin(SDRAM_RAS_PIO, SDRAM_RAS_FLAGS); pio_configure_pin(SDRAM_CAS_PIO, SDRAM_CAS_FLAGS); pio_configure_pin(SDRAM_SDWE_PIO, SDRAM_SDWE_FLAGS); pio_configure_pin(SDRAM_NBS0_PIO, SDRAM_NBS0_FLAGS); pio_configure_pin(SDRAM_NBS1_PIO, SDRAM_NBS1_FLAGS); pio_configure_pin(SDRAM_A2_PIO, SDRAM_A_FLAGS); pio_configure_pin(SDRAM_A3_PIO, SDRAM_A_FLAGS); pio_configure_pin(SDRAM_A4_PIO, SDRAM_A_FLAGS); pio_configure_pin(SDRAM_A5_PIO, SDRAM_A_FLAGS); pio_configure_pin(SDRAM_A6_PIO, SDRAM_A_FLAGS); pio_configure_pin(SDRAM_A7_PIO, SDRAM_A_FLAGS); pio_configure_pin(SDRAM_A8_PIO, SDRAM_A_FLAGS); pio_configure_pin(SDRAM_A9_PIO, SDRAM_A_FLAGS); pio_configure_pin(SDRAM_A10_PIO, SDRAM_A_FLAGS); pio_configure_pin(SDRAM_A11_PIO, SDRAM_A_FLAGS); pio_configure_pin(SDRAM_SDA10_PIO, SDRAM_SDA10_FLAGS); pio_configure_pin(SDRAM_D0_PIO, SDRAM_D_FLAGS); pio_configure_pin(SDRAM_D1_PIO, SDRAM_D_FLAGS); pio_configure_pin(SDRAM_D2_PIO, SDRAM_D_FLAGS); pio_configure_pin(SDRAM_D3_PIO, SDRAM_D_FLAGS); pio_configure_pin(SDRAM_D4_PIO, SDRAM_D_FLAGS); pio_configure_pin(SDRAM_D5_PIO, SDRAM_D_FLAGS); pio_configure_pin(SDRAM_D6_PIO, SDRAM_D_FLAGS); pio_configure_pin(SDRAM_D7_PIO, SDRAM_D_FLAGS); pio_configure_pin(SDRAM_D8_PIO, SDRAM_D_FLAGS); pio_configure_pin(SDRAM_D9_PIO, SDRAM_D_FLAGS); pio_configure_pin(SDRAM_D10_PIO, SDRAM_D_FLAGS); pio_configure_pin(SDRAM_D11_PIO, SDRAM_D_FLAGS); pio_configure_pin(SDRAM_D12_PIO, SDRAM_D_FLAGS); pio_configure_pin(SDRAM_D13_PIO, SDRAM_D_FLAGS); pio_configure_pin(SDRAM_D14_PIO, SDRAM_D_FLAGS); pio_configure_pin(SDRAM_D15_PIO, SDRAM_D_FLAGS); MATRIX->CCFG_SMCNFCS = CCFG_SMCNFCS_SDRAMEN; #endif #ifdef CONF_BOARD_CONFIG_MPU_AT_INIT _setup_memory_region(); #endif }