static int __init pit_timer_init(struct device_node *np) { struct clk *pit_clk; void __iomem *timer_base; unsigned long clk_rate; int irq, ret; timer_base = of_iomap(np, 0); if (!timer_base) { pr_err("Failed to iomap"); return -ENXIO; } /* * PIT0 and PIT1 can be chained to build a 64-bit timer, * so choose PIT2 as clocksource, PIT3 as clockevent device, * and leave PIT0 and PIT1 unused for anyone else who needs them. */ clksrc_base = timer_base + PITn_OFFSET(2); clkevt_base = timer_base + PITn_OFFSET(3); irq = irq_of_parse_and_map(np, 0); if (irq <= 0) return -EINVAL; pit_clk = of_clk_get(np, 0); if (IS_ERR(pit_clk)) return PTR_ERR(pit_clk); ret = clk_prepare_enable(pit_clk); if (ret) return ret; clk_rate = clk_get_rate(pit_clk); cycle_per_jiffy = clk_rate / (HZ); /* enable the pit module */ __raw_writel(~PITMCR_MDIS, timer_base + PITMCR); ret = pit_clocksource_init(clk_rate); if (ret) return ret; return pit_clockevent_init(clk_rate, irq); }
void __init pit_timer_init(struct clk *timer_clk, void __iomem *base, int irq) { timer_base = base; pit_cycle_per_jiffy = clk_get_rate(timer_clk)/(HZ); /* * Initialise to a known state (all timers off, and timing reset) */ __raw_writel(0x0, timer_base + PITMCR); __raw_writel(0, timer_base + PITOFFSET + PITTCTRL); __raw_writel(0xffffffff, timer_base + PITOFFSET + PITLDVAL); __raw_writel(PITTCTRL_TEN, timer_base + PITOFFSET + PITTCTRL); /* init and register the timer to the framework */ pit_clocksource_init(timer_clk); pit_clockevent_init(timer_clk); /* Make irqs happen */ setup_irq(irq, &pit_timer_irq); }