void pl011_init(struct pl011_data *pd, paddr_t pbase, uint32_t uart_clk,
uint32_t baud_rate)
{
vaddr_t base;
pd->base.pa = pbase;
pd->chip.ops = &pl011_ops;
base = io_pa_or_va(&pd->base);
/* Clear all errors */
io_write32(base + UART_RSR_ECR, 0);
/* Disable everything */
io_write32(base + UART_CR, 0);
if (baud_rate) {
uint32_t divisor = (uart_clk * 4) / baud_rate;
io_write32(base + UART_IBRD, divisor >> 6);
io_write32(base + UART_FBRD, divisor & 0x3f);
}
/* Configure TX to 8 bits, 1 stop bit, no parity, fifo disabled. */
io_write32(base + UART_LCR_H, UART_LCRH_WLEN_8);
/* Enable interrupts for receive and receive timeout */
io_write32(base + UART_IMSC, UART_IMSC_RXIM | UART_IMSC_RTIM);
/* Enable UART and RX/TX */
io_write32(base + UART_CR, UART_CR_UARTEN | UART_CR_TXE | UART_CR_RXE);
pl011_flush(&pd->chip);
}
void pl011_init(vaddr_t base, uint32_t uart_clk, uint32_t baud_rate)
{
if (baud_rate) {
uint32_t divisor = (uart_clk * 4) / baud_rate;
write32(divisor >> 6, base + UART_IBRD);
write32(divisor & 0x3f, base + UART_FBRD);
}
write32(0, base + UART_RSR_ECR);
/* Configure TX to 8 bits, 1 stop bit, no parity, fifo disabled. */
write32(UART_LCRH_WLEN_8, base + UART_LCR_H);
write32(UART_IMSC_RXIM, base + UART_IMSC);
/* Enable UART and TX */
write32(UART_CR_UARTEN | UART_CR_TXE | UART_CR_RXE, base + UART_CR);
pl011_flush(base);
}
void console_flush(void)
{
pl011_flush(CONSOLE_UART_BASE);
}
void console_flush(void)
{
pl011_flush(console_base());
}
