/*
* Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the MMU in a quick and dirty way.
*/
void bl31_plat_arch_setup(void)
{
plat_arm_interconnect_init();
plat_arm_interconnect_enter_coherency();
arm_configure_mmu_el3(BL31_RO_BASE,
BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE,
BL31_RO_BASE,
BL31_RO_LIMIT,
BL31_COHERENT_RAM_BASE,
BL31_COHERENT_RAM_LIMIT);
}
/*
* Perform the very early platform specific architectural setup here.
*/
void bl31_plat_arch_setup(void)
{
plat_arm_interconnect_init();
plat_arm_interconnect_enter_coherency();
arm_setup_page_tables(BL31_BASE,
BL31_END - BL31_BASE,
BL_CODE_BASE,
BL_CODE_END,
BL_RO_DATA_BASE,
BL_RO_DATA_END,
BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END);
enable_mmu_el3(0);
}
void bl31_early_platform_setup(bl31_params_t *from_bl2,
void *plat_params_from_bl2)
{
arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2);
/*
* Initialize Interconnect for this cluster during cold boot.
* No need for locks as no other CPU is active.
*/
plat_arm_interconnect_init();
/*
* Enable Interconnect coherency for the primary CPU's cluster.
* Earlier bootloader stages might already do this (e.g. Trusted
* Firmware's BL1 does it) but we can't assume so. There is no harm in
* executing this code twice anyway.
* Platform specific PSCI code will enable coherency for other
* clusters.
*/
plat_arm_interconnect_enter_coherency();
}
/*******************************************************************************
* Default implementation for sp_min_platform_setup2() for ARM platforms
******************************************************************************/
void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
/*
* Initialize Interconnect for this cluster during cold boot.
* No need for locks as no other CPU is active.
*/
plat_arm_interconnect_init();
/*
* Enable Interconnect coherency for the primary CPU's cluster.
* Earlier bootloader stages might already do this (e.g. Trusted
* Firmware's BL1 does it) but we can't assume so. There is no harm in
* executing this code twice anyway.
* Platform specific PSCI code will enable coherency for other
* clusters.
*/
plat_arm_interconnect_enter_coherency();
}
