static __init void register_address_space(phys_addr_t memsize)
{
int i;
phys_addr_t size;
size_t n;
struct mem_layout *layout;
enum family_type family;
register_non_ram();
family = platform_get_family();
for (i = 0; i < ARRAY_SIZE(layout_list); i++) {
if (layout_list[i].family == family)
break;
}
if (i == ARRAY_SIZE(layout_list)) {
n = ARRAY_SIZE(default_layout);
layout = default_layout;
} else {
n = layout_list[i].n;
layout = layout_list[i].layout;
}
for (i = 0; memsize != 0 && i < n; i++) {
size = min(memsize, layout[i].size);
register_ram(layout[i].phys, layout[i].alias, size);
memsize -= size;
}
}
/**
* register_address_space - register things in the address space
* @memsize: Number of bytes of RAM installed
*
* Takes the given number of bytes of RAM and registers as many of the regions,
* or partial regions, as it can. So, the default configuration might have
* two regions with 256 MiB each. If the memsize passed in on the command line
* is 384 MiB, it will register the first region with 256 MiB and the second
* with 128 MiB.
*/
static __init void register_address_space(phys_addr_t memsize)
{
int i;
phys_addr_t size;
size_t n;
struct mem_layout *layout;
enum family_type family;
/*
* Register all of the things that aren't available to the kernel as
* memory.
*/
register_non_ram();
/* Find the appropriate memory description */
family = platform_get_family();
for (i = 0; i < ARRAY_SIZE(layout_list); i++) {
if (layout_list[i].family == family)
break;
}
if (i == ARRAY_SIZE(layout_list)) {
n = ARRAY_SIZE(default_layout);
layout = default_layout;
} else {
n = layout_list[i].n;
layout = layout_list[i].layout;
}
for (i = 0; memsize != 0 && i < n; i++) {
size = min(memsize, layout[i].size);
register_ram(layout[i].phys, layout[i].alias, size);
memsize -= size;
}
}
static void platform_configure_usb(void)
{
u32 bcm1_usb2_ctl_value;
enum asic_type asic_type;
unsigned long flags;
spin_lock_irqsave(&usb_regs_lock, flags);
usb_users++;
if (usb_users != 1) {
spin_unlock_irqrestore(&usb_regs_lock, flags);
return;
}
asic_type = platform_get_asic();
switch (asic_type) {
case ASIC_ZEUS:
fs_update(0x0000, -15, 0x02, 0, 0);
bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
break;
case ASIC_CRONUS:
case ASIC_CRONUSLITE:
usb_eye_configure(0, CRT_SPARE_USB_DIVIDE_BY_9);
fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3,
QAM_FS_DISABLE_DIGITAL_STANDBY);
bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
break;
case ASIC_CALLIOPE:
fs_update(0x0000, -15, 0x02, QAM_FS_DISABLE_DIVIDE_BY_3,
QAM_FS_DISABLE_DIGITAL_STANDBY);
switch (platform_get_family()) {
case FAMILY_1500VZE:
break;
case FAMILY_1500VZF:
usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK |
CRT_SPARE_PORT1_SHIFT_JK |
CRT_SPARE_PORT2_FAST_EDGE |
CRT_SPARE_PORT1_FAST_EDGE, 0);
break;
default:
usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK |
CRT_SPARE_PORT1_SHIFT_JK, 0);
break;
}
bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK |
BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
break;
case ASIC_GAIA:
fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3,
QAM_FS_DISABLE_DIGITAL_STANDBY);
bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK |
BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
break;
default:
pr_err("Unknown ASIC type: %d\n", asic_type);
bcm1_usb2_ctl_value = 0;
break;
}
/* */
asic_write(0, usb2_strap);
/* */
asic_write(bcm1_usb2_ctl_value, usb2_control);
/* */
asic_write(USB_STBUS_OBC_STORE32_LOAD32, usb2_stbus_obc);
/* */
asic_write(USB2_STBUS_MESS_SIZE_2, usb2_stbus_mess_size);
/* */
asic_write(USB2_STBUS_CHUNK_SIZE_2, usb2_stbus_chunk_size);
spin_unlock_irqrestore(&usb_regs_lock, flags);
}
