u32 platform_s_timer_op( unsigned id, int op, u32 data )
{
u32 res = 0;
PREG TxTCR = ( PREG )tmr_tcr[ id ];
PREG TxTC = ( PREG )tmr_tc[ id ];
switch( op )
{
case PLATFORM_TIMER_OP_START:
*TxTCR = TMR_ENABLE | TMR_RESET;
*TxTCR = TMR_ENABLE;
break;
case PLATFORM_TIMER_OP_READ:
res = *TxTC;
break;
case PLATFORM_TIMER_OP_GET_MAX_DELAY:
res = platform_timer_get_diff_us( id, 0, 0xFFFFFFFF );
break;
case PLATFORM_TIMER_OP_GET_MIN_DELAY:
res = platform_timer_get_diff_us( id, 0, 1 );
break;
case PLATFORM_TIMER_OP_SET_CLOCK:
res = platform_timer_set_clock( id, data );
break;
case PLATFORM_TIMER_OP_GET_CLOCK:
res = platform_timer_get_clock( id );
break;
}
return res;
}
timer_data_type platform_s_timer_op( unsigned id, int op, timer_data_type data )
{
u32 res = 0;
switch( op )
{
case PLATFORM_TIMER_OP_START:
TIM_Cmd( tmr[ id ], ENABLE );
TIM_ResetCounter( tmr[ id ] );
break;
case PLATFORM_TIMER_OP_READ:
res = tmr[ id ]->TC;
break;
case PLATFORM_TIMER_OP_SET_CLOCK:
res = platform_timer_set_clock( id, data );
break;
case PLATFORM_TIMER_OP_GET_CLOCK:
res = platform_timer_get_clock( id );
break;
case PLATFORM_TIMER_OP_GET_MAX_CNT:
res = 0xFFFFFFFF;
break;
}
return res;
}
// Helper function: setup timers
static void platform_setup_timers()
{
unsigned i;
PREG TxTCR;
// Set base frequency to 1MHz, as we can't use a better resolution anyway
for( i = 0; i < 4; i ++ )
{
TxTCR = ( PREG )tmr_tcr[ i ];
*TxTCR = 0;
platform_timer_set_clock( i, 1000000ULL );
}
#if VTMR_NUM_TIMERS > 0
// Setup virtual timers here
// Timer 3 is allocated for virtual timers and nothing else in this case
T3TCR = TMR_RESET;
T3MR0 = 1000000ULL / VTMR_FREQ_HZ - 1;
T3IR = 0xFF;
// Set interrupt handle and eanble timer interrupt (and global interrupts)
T3MCR = 0x03; // interrupt on match with MR0 and clear on match
install_irq( TIMER3_INT, int_handler_tmr, HIGHEST_PRIORITY );
platform_cpu_set_global_interrupts( PLATFORM_CPU_ENABLE );
// Start timer
T3TCR = TMR_ENABLE;
#endif
}
// Helper function: setup timers
static void platform_setup_timers()
{
unsigned i;
// Power on clocks on APB1
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM2, ENABLE);
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM3, ENABLE);
// Set base frequency to 1MHz, as we can't use a better resolution anyway
for( i = 0; i < 4; i ++ )
platform_timer_set_clock( i, 1000000ULL );
}
static void timers_init()
{
unsigned i;
// Enable clocks.
RCC_APB2PeriphClockCmd( RCC_APB2Periph_TIM1, ENABLE );
RCC_APB1PeriphClockCmd( RCC_APB1Periph_TIM2, ENABLE );
RCC_APB1PeriphClockCmd( RCC_APB1Periph_TIM3, ENABLE );
RCC_APB1PeriphClockCmd( RCC_APB1Periph_TIM4, ENABLE );
RCC_APB1PeriphClockCmd( RCC_APB1Periph_TIM5, ENABLE );
// Configure timers
for( i = 0; i < NUM_TIMER; i ++ )
platform_timer_set_clock( i, TIM_STARTUP_CLOCK );
}
