void
platform_poweron() {
ot_u32 prescaler = 32;
/// Hardware turn-on stuff
SystemInit(); // comes from STLib, does lots of startup
platform_init_busclk(); // extra bus clock setup not in SystemInit()
platform_init_periphclk(); // Peripherals OpenTag cares about
platform_init_interruptor(); // Interrupts OpenTag cares about
systim_init((void*)&prescaler); // Initialize GPTIM (to 1024 Hz)
platform_init_gpio(); // Set up connections on the board
platform_init_spi(); // initialize command interface to radio
#if ( defined(RADIO_DEBUG) || (OT_FEATURE(MPIPE) == ENABLED) )
platform_uart_init();
#endif /* RADIO_DEBUG */
#if defined(RADIO_DEBUG)
debug_uart_init();
#endif /* RADIO_DEBUG */
rng_seed();
/// Restore vworm (following save on shutdown)
vworm_init();
# if (OT_FEATURE(MPIPE) == ENABLED)
/// Mpipe (message pipe) typically used for serial-line comm.
mpipe_init(NULL);
# endif
}
wiced_result_t bluetooth_wiced_init_config_uart( const platform_uart_config_t* bt_uart_config )
{
wiced_result_t result;
ring_buffer_init( (wiced_ring_buffer_t*) &rx_ring_buffer, (uint8_t*) rx_data, sizeof( rx_data ) );
result = platform_uart_init( wiced_bt_uart_driver, wiced_bt_uart_peripheral, bt_uart_config, (wiced_ring_buffer_t*) &rx_ring_buffer );
return result;
}
OSStatus MicoUartInitialize( mico_uart_t uart, const mico_uart_config_t* config, ring_buffer_t* optional_rx_buffer )
{
if ( uart >= MICO_UART_NONE )
return kUnsupportedErr;
#ifndef MICO_DISABLE_STDIO
/* Interface is used by STDIO. Uncomment MICO_DISABLE_STDIO to overcome this */
if ( uart == STDIO_UART )
{
return kGeneralErr;
}
#endif
return (OSStatus) platform_uart_init( &platform_uart_drivers[uart], &platform_uart_peripherals[uart], config, optional_rx_buffer );
}
void EVM_init()
{
platform_init_flags sFlags;
platform_init_config sConfig;
int32_t pform_status;
platform_info sPlatformInfo;
/* Initialise the UART
* You can choose what to initialise on the platform by setting the following
* flags. Things like the DDR, PLL, etc should have been set by the boot loader.
*/
memset( (void *) &sFlags, 0, sizeof(platform_init_flags));
memset( (void *) &sConfig, 0, sizeof(platform_init_config));
sFlags.pll = 0; /* PLLs for clocking */
sFlags.ddr = 1; /* External memory */
sFlags.tcsl = 1; /* Time stamp counter */
sFlags.phy = 1; /* Ethernet */
sFlags.ecc = 0; /* Memory ECC */
sConfig.pllm = 0; /* Use libraries default clock divisor */
pform_status = platform_init(&sFlags, &sConfig);
/* If we initialised the platform okay */
if (pform_status != Platform_EOK) {
/* Initialisation of the platform failed... die */
platform_write("Platform failed to initialise. Error code %d \n", pform_status);
platform_write("We will die in an infinite loop... \n");
while (1) {
(void) platform_led(1, PLATFORM_LED_ON, PLATFORM_USER_LED_CLASS);
(void) platform_delay(50000);
(void) platform_led(1, PLATFORM_LED_OFF, PLATFORM_USER_LED_CLASS);
(void) platform_delay(50000);
}
}
memset( (void *) &sPlatformInfo, 0, sizeof(platform_info));
memset( (void *) &gPlatformInfo, 0, sizeof(platform_info));
platform_get_info(&sPlatformInfo);
//platform_get_info(&sPlatformInfo);
platform_get_info(&gPlatformInfo);
number_of_cores = gPlatformInfo.cpu.core_count;
//MultiProc_setLocalId((Uint16) platform_get_coreid());
platform_uart_init();
platform_uart_set_baudrate(115200);
platform_write_configure (PLATFORM_WRITE_ALL);
platform_write("Board Name %s \n",sPlatformInfo.board_name);
//write_uart("\r\n\r\nBooting Hello World image from NAND flash via IBL over I2C 0x51 ...");
//MultiProc_setLocalId((Uint16) platform_get_coreid());
//CSL_init();
//Uint16 eventId0;
//IRQ_clear(eventId0);
//eventId0 = TIMER_getEventId(timer0Handle);
//IRQ_enable(eventId0);
//IRQ_globalEnable();
return;
}
//
// Initialize QMSS and CPPI
//
//RBE TODO: DO WE NEED QMSS AND CPPI ???
//If not also delete resourcemgr.c and in client.cfg the Program.sectMap-entries named .resmgr*
//
int Init_QMSS_CPPI()
{
int i;
QMSS_CFG_T qmss_cfg;
CPPI_CFG_T cppi_cfg;
/* Get information about the platform so we can use it in various places */
memset( (void *) &gPlatformInfo, 0, sizeof(platform_info));
(void) platform_get_info(&gPlatformInfo);
(void) platform_uart_init();
(void) platform_uart_set_baudrate(115200);
(void) platform_write_configure(PLATFORM_WRITE_ALL);
/* Clear the state of the User LEDs to OFF */
for (i=0; i < gPlatformInfo.led[PLATFORM_USER_LED_CLASS].count; i++) {
(void) platform_led(i, PLATFORM_LED_OFF, PLATFORM_USER_LED_CLASS);
}
/* Initialize the components required to run this application:
* (1) QMSS
* (2) CPPI
* (3) Packet Accelerator
*/
/* Initialize QMSS */
if (platform_get_coreid() == 0)
{
qmss_cfg.master_core = 1;
}
else
{
qmss_cfg.master_core = 0;
}
qmss_cfg.max_num_desc = MAX_NUM_DESC;
qmss_cfg.desc_size = MAX_DESC_SIZE;
qmss_cfg.mem_region = Qmss_MemRegion_MEMORY_REGION0;
if (res_mgr_init_qmss (&qmss_cfg) != 0)
{
logout ("Failed to initialize the QMSS subsystem \n");
goto main_exit;
}
else
{
logout ("QMSS successfully initialized \n");
}
/* Initialize CPPI */
if (platform_get_coreid() == 0)
{
cppi_cfg.master_core = 1;
}
else
{
cppi_cfg.master_core = 0;
}
cppi_cfg.dma_num = Cppi_CpDma_PASS_CPDMA;
cppi_cfg.num_tx_queues = NUM_PA_TX_QUEUES;
cppi_cfg.num_rx_channels = NUM_PA_RX_CHANNELS;
if (res_mgr_init_cppi (&cppi_cfg) != 0)
{
logout ("Failed to initialize CPPI subsystem \n");
goto main_exit;
}
else
{
logout ("CPPI successfully initialized \n");
}
main_exit:
return(0);
}
extern void __interrupt _c_int00()
{
/*-------------------------------------------------------------------------
* After a reset, the device should have invalidated caches. The caches will
* still be configured as they were prior to the reset. Since this code was
* loaded into L2, we will ensure that L2 is configured as all sram.
*------------------------------------------------------------------------*/
CACHE_setL2Size (CACHE_0KCACHE);
CACHE_setL1DSize(CACHE_L1_32KCACHE);
CACHE_setL1PSize(CACHE_L1_32KCACHE);
/*-------------------------------------------------------------------------
* Set up the stack pointer in b15.
* The stack pointer points 1 word past the top of the stack, so subtract
* 1 word from the size. also the sp must be aligned on an 8-byte boundary
*------------------------------------------------------------------------*/
__asm("\t MVKL\t\t __TI_STACK_END - 4, SP");
__asm("\t MVKH\t\t __TI_STACK_END - 4, SP");
__asm("\t AND\t\t ~7,SP,SP");
/*-------------------------------------------------------------------------
* Set up the global data page pointer in b14.
*------------------------------------------------------------------------*/
__asm("\t MVKL\t\t __TI_STATIC_BASE,DP");
__asm("\t MVKH\t\t __TI_STATIC_BASE,DP");
/*-------------------------------------------------------------------------
* disable cache for all addrs over 0x1000:0000
*------------------------------------------------------------------------*/
memset((void*)0x01848040, 0, 960);
/*-------------------------------------------------------------------------
* disable mpax registers 3 and above
*------------------------------------------------------------------------*/
memset((void*)0x08000018, 0, 104);
/*-------------------------------------------------------------------------
* disable msmc ses mpax registers except for the first one at each pri lev
*------------------------------------------------------------------------*/
if (DNUM == 0)
{
int i;
for (i=0; i < 16; i++)
memset((void*)(0x0bc00600 + (i * 0x40) + 8), 0, 0x38);
}
/*-------------------------------------------------------------------------
* Set up floating point registers
*------------------------------------------------------------------------*/
FADCR = 0; FMCR = 0;
/*-------------------------------------------------------------------------
* Setup platform specifics, i.e. uarts, ethernet, etc.
*------------------------------------------------------------------------*/
if (DNUM == 0)
{
/*---------------------------------------------------------------------
* Check if Boot time init configuration is loaded
*
* This code is reading l2 memory written by the host. The values were
* written before this code began running, so the cache invalidate at
* reset should ensure that when we read these values we will miss l1 and
* read directly from l2.
*--------------------------------------------------------------------*/
platform_init_config config;
config.pllm = 0; // Original configuraion : default 0 -> 1 GHz
if (init_config.magic_number == 0xBABEFACE)
config.pllm = init_config.dsp_pll_multiplier;
/* Platform initialization */
platform_init_flags flags;
flags.pll = 0x1;
flags.ddr = 0x1;
flags.tcsl = 0x1;
flags.phy = 0x0;
flags.ecc = 0x1;
platform_init(&flags, &config);
platform_uart_init();
platform_uart_set_baudrate(DEF_INIT_CONFIG_UART_BAUDRATE);
memset((void*)&flags, 0 , sizeof(platform_init_flags));
memset((void*)&config, 0, sizeof(platform_init_config));
flags.pll = 0;
flags.ddr = 0;
flags.tcsl = 1;
flags.phy = 1;
flags.ecc = 0;
platform_init(&flags, &config);
Init_MAC(0);
Init_MAC(1);
Init_Switch(1506);
}
/*-------------------------------------------------------------------------
* Once we write 0 to the boot magic addr, the host can proceed with the
* loading of another program that will subsequently run. We should ensure
* that the caches are written back and clean at this point so that a
* subsequent writeback opertation will not clobber the program loaded
* from the host. It is also clearly important that the loaded program
* did not write over the L2 area containing the remainder of this code.
*------------------------------------------------------------------------*/
BOOT_MAGIC_CONTENTS = 0;
CACHE_wbInvL1d((void*)(BOOT_MAGIC_ADDR & ~0x3f), 64, CACHE_WAIT);
wait_for_interrupt();
/*-------------------------------------------------------------------------
* We will now wait until an external entity writes the address to which we
* should jump
*------------------------------------------------------------------------*/
while (1)
{
/*---------------------------------------------------------------------
* invalidate the address so that we pick up the actual memory written by
* the external entity.
*--------------------------------------------------------------------*/
CACHE_invL1d((void*)(BOOT_MAGIC_ADDR & ~0x3f), 64, CACHE_WAIT);
void (*entry)() = (void (*)())(BOOT_MAGIC_CONTENTS);
/*---------------------------------------------------------------------
* If we have a non null pointer then we will branch to it. This
* essentially marks the end of this routine and the start of another,
* so we should ensure that the caches are written back and clean at
* this point so that the following program starts with a clean cache
* system.
*
* It is also clearly important that the loaded program did not write
* over the L2 area containing this reset code. Since this reset code
* is entirely resident in the last 1/4 of L2, this area should not
* contain initialized data or code in the following program.
*--------------------------------------------------------------------*/
if (entry)
{
flushCache();
(*entry)();
}
}
}
