/**
* @brief Low level HAL driver initialization.
*
* @notapi
*/
void hal_lld_init(void) {
/* Disabling PMC write protection. */
pmcDisableWP();
/* Enabling matrix clock */
pmcEnableH32MX();
pmcEnableH64MX();
/* Enabling write protection. */
pmcEnableWP();
#if defined(SAMA_DMA_REQUIRED)
dmaInit();
#endif
/* Advanced interrupt controller init */
aicInit();
}
/**
* @brief Board-specific initialization code.
*/
void boardInit(void) {
unsigned i;
/* Disabling PMC write protection. */
pmcDisableWP();
/* Enabling port clock. */
pmcEnablePIO();
/* Enabling write protection. */
pmcEnableWP();
_PIOA->S_PIO_WPMR = PIO_WPMR_WPKEY_PASSWD;
/* Configuring all PIO A pads with default configuration. */
#if SAMA_HAS_PIOA
_PIOA->PIO_PIO_[SAMA_PIOA].S_PIO_SIOSR = SAMA_DEFAULT_SIOSR;
_PIOA->PIO_PIO_[SAMA_PIOA].S_PIO_SIONR = SAMA_DEFAULT_SIONR;
_PIOA->PIO_PIO_[SAMA_PIOA].S_PIO_MSKR = SAMA_DEFAULT_MSKR;
_PIOA->PIO_PIO_[SAMA_PIOA].S_PIO_CFGR = SAMA_DEFAULT_CFGR;
#endif /* SAMA_HAS_PIOA */
/* Configuring all PIO B pads with default configuration. */
#if SAMA_HAS_PIOB
_PIOA->PIO_PIO_[SAMA_PIOB].S_PIO_SIOSR = SAMA_DEFAULT_SIOSR;
_PIOA->PIO_PIO_[SAMA_PIOB].S_PIO_SIONR = SAMA_DEFAULT_SIONR;
_PIOA->PIO_PIO_[SAMA_PIOB].S_PIO_MSKR = SAMA_DEFAULT_MSKR;
_PIOA->PIO_PIO_[SAMA_PIOB].S_PIO_CFGR = SAMA_DEFAULT_CFGR;
#endif /* SAMA_HAS_PIOB */
/* Configuring all PIO C pads with default configuration. */
#if SAMA_HAS_PIOC
_PIOA->PIO_PIO_[SAMA_PIOC].S_PIO_SIOSR = SAMA_DEFAULT_SIOSR;
_PIOA->PIO_PIO_[SAMA_PIOC].S_PIO_SIONR = SAMA_DEFAULT_SIONR;
_PIOA->PIO_PIO_[SAMA_PIOC].S_PIO_MSKR = SAMA_DEFAULT_MSKR;
_PIOA->PIO_PIO_[SAMA_PIOC].S_PIO_CFGR = SAMA_DEFAULT_CFGR;
#endif /* SAMA_HAS_PIOC */
/* Configuring all PIO D pads with default configuration. */
#if SAMA_HAS_PIOD
_PIOA->PIO_PIO_[SAMA_PIOD].S_PIO_SIOSR = SAMA_DEFAULT_SIOSR;
_PIOA->PIO_PIO_[SAMA_PIOD].S_PIO_SIONR = SAMA_DEFAULT_SIONR;
_PIOA->PIO_PIO_[SAMA_PIOD].S_PIO_MSKR = SAMA_DEFAULT_MSKR;
_PIOA->PIO_PIO_[SAMA_PIOD].S_PIO_CFGR = SAMA_DEFAULT_CFGR;
#endif /* SAMA_HAS_PIOD */
/* Initialize PIO registers for defined pads.*/
i = 0;
while (sama_inits[i].pio_id != -1) {
_PIOA->PIO_PIO_[sama_inits[i].pio_id].S_PIO_SIOSR = sama_inits[i].pio_msk;
_PIOA->PIO_PIO_[sama_inits[i].pio_id].S_PIO_MSKR = sama_inits[i].pio_msk;
_PIOA->PIO_PIO_[sama_inits[i].pio_id].S_PIO_CFGR = sama_inits[i].pio_cfg;
if(sama_inits[i].pio_ods == SAMA_PIO_HIGH) {
_PIOA->PIO_PIO_[sama_inits[i].pio_id].S_PIO_SODR = sama_inits[i].pio_msk;
}
else {
_PIOA->PIO_PIO_[sama_inits[i].pio_id].S_PIO_CODR = sama_inits[i].pio_msk;
}
i++;
}
}
/**
* @brief SAMA clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h.
* @note This function should be invoked just after the system reset.
*
* @special
*/
void sama_clock_init(void) {
#if !SAMA_NO_INIT
uint32_t mor, pllar, mckr, mainf;
/* Disabling PMC write protection. */
pmcDisableWP();
/*
* Enforcing the reset default configuration of clock tree.
*/
/* Setting Slow Clock source to OSCRC. */
SCKC->SCKC_CR = 0U;
/* Enabling MOSCRC. */
PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN);
while (!(PMC->PMC_SR & PMC_SR_MOSCRCS))
; /* Waits until MOSCRC is stable.*/
/* Switching Main Oscillator Source to MOSRC. */
mor = PMC->CKGR_MOR | CKGR_MOR_KEY_PASSWD;
mor &= ~CKGR_MOR_MOSCSEL;
mor |= SAMA_MOSC_MOSCRC;
PMC->CKGR_MOR = mor;
while (!(PMC->PMC_SR & PMC_SR_MOSCSELS))
; /* Waits until MOSCSEL has changed.*/
/* Switching Master Clock source to Main Clock. */
mckr = PMC->PMC_MCKR;
mckr &= ~PMC_MCKR_CSS_Msk;
mckr |= PMC_MCKR_CSS_MAIN_CLK;
PMC->PMC_MCKR = mckr;
while (!(PMC->PMC_SR & PMC_SR_MCKRDY))
; /* Waits until Master Clock is stable.*/
/* Counter Clock Source to MOSCRC. */
PMC->CKGR_MCFR &= ~CKGR_MCFR_CCSS;
/*
* Main oscillator configuration block.
*/
/* Setting Slow clock source. */
SCKC->SCKC_CR = SAMA_OSC_SEL;
while ((SAMA_OSC_SEL && !(PMC->PMC_SR & PMC_SR_OSCSELS)) ||
(!SAMA_OSC_SEL && (PMC->PMC_SR & PMC_SR_OSCSELS)))
; /* Waits until MOSCxxS switch is done.*/
mor = PMC->CKGR_MOR | CKGR_MOR_KEY_PASSWD;
#if SAMA_MOSCXT_ENABLED
mor |= CKGR_MOR_MOSCXTEN;
PMC->CKGR_MOR = mor;
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS))
; /* Waits until MOSCXT is stable.*/
/* Counter Clock Source to MOSCXT. */
PMC->CKGR_MCFR |= CKGR_MCFR_CCSS;
#else
mor &= ~CKGR_MOR_MOSCXTEN;
PMC->CKGR_MOR = mor;
#endif
PMC->CKGR_MCFR |= CKGR_MCFR_RCMEAS;
while (!(PMC->CKGR_MCFR & CKGR_MCFR_MAINFRDY))
;
mainf = CKGR_MCFR_MAINF(PMC->CKGR_MCFR);
/*
* @TODO: add mainf check and eventual clock source fallback. This mechanism
* should be activable through a switch.
*/
(void)mainf;
/* Switching Main Clock source. */
mor &= ~CKGR_MOR_MOSCSEL;
mor |= SAMA_MOSC_SEL;
PMC->CKGR_MOR = mor;
/* Eventually disabling MOSCRC. */
#if !SAMA_MOSCRC_ENABLED
PMC->CKGR_MOR &= ~ CKGR_MOR_MOSCRCEN;
#endif
/*
* PLLA configuration block.
*/
pllar = SAMA_PLLA_ONE | CKGR_PLLAR_PLLACOUNT(0x3F);
#if SAMA_ACTIVATE_PLLA
pllar |= CKGR_PLLAR_DIVA_BYPASS | SAMA_PLLA_MUL;
#endif
PMC->CKGR_PLLAR = pllar; /* Writing PLLA register. */
#if SAMA_ACTIVATE_PLLA
while (!(PMC->PMC_SR & PMC_SR_LOCKA))
; /* Waits until PLLA is locked. */
#endif
/*
* Master clock configuration block.
*/
mckr = PMC->PMC_MCKR;
mckr &= ~PMC_MCKR_CSS_Msk;
mckr |= SAMA_MCK_SEL;
PMC->PMC_MCKR = mckr;
while (!(PMC->PMC_SR & PMC_SR_MCKRDY))
; /* Waits until MCK is stable. */
mckr &= ~(PMC_MCKR_PRES_Msk | PMC_MCKR_MDIV_Msk | PMC_MCKR_H32MXDIV);
/* Note that prescaler and divider must be changed with separate accesses.*/
mckr |= SAMA_MCK_PRES;
mckr |= SAMA_MCK_MDIV;
mckr |= SAMA_H64MX_H32MX_DIV;
#if SAMA_PLLADIV2_EN
mckr |= PMC_MCKR_PLLADIV2;
#else
mckr &= ~PMC_MCKR_PLLADIV2;
#endif
PMC->PMC_MCKR = mckr;
while (!(PMC->PMC_SR & PMC_SR_MCKRDY))
; /* Waits until MCK is stable. */
/* Enabling write protection. */
pmcEnableWP();
#endif /* !SAMA_NO_INIT */
}
