static int power_init(void)
{
struct udevice *dev;
int ret;
ret = pmic_get("mc34708", &dev);
if (ret) {
printf("%s: mc34708 not found !\n", __func__);
return ret;
}
/* Set VDDGP to 1.110V for 800 MHz on SW1 */
pmic_clrsetbits(dev, REG_SW_0, SWx_VOLT_MASK_MC34708,
SWx_1_110V_MC34708);
/* Set VCC as 1.30V on SW2 */
pmic_clrsetbits(dev, REG_SW_1, SWx_VOLT_MASK_MC34708,
SWx_1_300V_MC34708);
/* Set global reset timer to 4s */
pmic_clrsetbits(dev, REG_POWER_CTL2, TIMER_MASK_MC34708,
TIMER_4S_MC34708);
return ret;
}
int exynos_power_init(void)
{
struct udevice *dev;
int ret;
ret = pmic_get("max77686", &dev);
if (!ret) {
/* TODO([email protected]): Move into the clock/pmic API */
ret = pmic_clrsetbits(dev, MAX77686_REG_PMIC_32KHZ, 0,
MAX77686_32KHCP_EN);
if (ret)
return ret;
ret = pmic_clrsetbits(dev, MAX77686_REG_PMIC_BBAT, 0,
MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V);
if (ret)
return ret;
} else {
ret = pmic_get("s5m8767-pmic", &dev);
/* TODO([email protected]): Use driver model to access clock */
#ifdef CONFIG_PMIC_S5M8767
if (!ret)
s5m8767_enable_32khz_cp(dev);
#endif
}
if (ret == -ENODEV)
return 0;
ret = regulators_enable_boot_on(false);
if (ret)
return ret;
ret = exynos_set_regulator("vdd_mif", 1100000);
if (ret)
return ret;
/*
* This would normally be 1.3V, but since we are running slowly 1.1V
* is enough. For spring it helps reduce CPU temperature and avoid
* hangs with the case open. 1.1V is minimum voltage borderline for
* chained bootloaders.
*/
ret = exynos_set_regulator("vdd_arm", 1100000);
if (ret)
return ret;
ret = exynos_set_regulator("vdd_int", 1012500);
if (ret)
return ret;
ret = exynos_set_regulator("vdd_g3d", 1200000);
if (ret)
return ret;
return 0;
}
static int pm8916_gpio_set_direction(struct udevice *dev, unsigned offset,
bool input, int value)
{
struct pm8916_gpio_bank *priv = dev_get_priv(dev);
uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
int ret;
/* Disable the GPIO */
ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL,
REG_EN_CTL_ENABLE, 0);
if (ret < 0)
return ret;
/* Select the mode */
if (input)
ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL,
REG_CTL_MODE_INPUT);
else
ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL,
REG_CTL_MODE_INOUT | (value ? 1 : 0));
if (ret < 0)
return ret;
/* Set the right pull (no pull) */
ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_PULL_CTL,
REG_DIG_PULL_NO_PU);
if (ret < 0)
return ret;
/* Configure output pin drivers if needed */
if (!input) {
/* Select the VIN - VIN0, pin is input so it doesn't matter */
ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_VIN_CTL,
REG_DIG_VIN_VIN0);
if (ret < 0)
return ret;
/* Set the right dig out control */
ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_OUT_CTL,
REG_DIG_OUT_CTL_CMOS |
REG_DIG_OUT_CTL_DRIVE_L);
if (ret < 0)
return ret;
}
/* Enable the GPIO */
return pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL, 0,
REG_EN_CTL_ENABLE);
}
static int reg_set_enable(struct udevice *dev, bool enable)
{
int reg = dev->driver_data;
return pmic_clrsetbits(dev->parent, addr_ctl[reg], LDO_EN_MASK,
enable ? LDO_EN_MASK : 0);
}
int exynos_power_init(void)
{
struct udevice *dev;
int ret;
ret = pmic_get("max77686", &dev);
if (!ret) {
/* TODO([email protected]): Move into the clock/pmic API */
ret = pmic_clrsetbits(dev, MAX77686_REG_PMIC_32KHZ, 0,
MAX77686_32KHCP_EN);
if (ret)
return ret;
ret = pmic_clrsetbits(dev, MAX77686_REG_PMIC_BBAT, 0,
MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V);
if (ret)
return ret;
} else {
ret = pmic_get("s5m8767-pmic", &dev);
/* TODO([email protected]): Use driver model to access clock */
#ifdef CONFIG_PMIC_S5M8767
if (!ret)
s5m8767_enable_32khz_cp(dev);
#endif
}
if (ret == -ENODEV)
return 0;
ret = regulators_enable_boot_on(false);
if (ret)
return ret;
ret = exynos_set_regulator("vdd_mif", 1100000);
if (ret)
return ret;
ret = exynos_set_regulator("vdd_arm", 1300000);
if (ret)
return ret;
ret = exynos_set_regulator("vdd_int", 1012500);
if (ret)
return ret;
ret = exynos_set_regulator("vdd_g3d", 1200000);
if (ret)
return ret;
return 0;
}
static int _buck_set_enable(struct udevice *pmic, int buck, bool enable)
{
uint mask;
int ret;
buck--;
mask = 1 << buck;
if (enable) {
ret = pmic_clrsetbits(pmic, REG_DCDC_ILMAX, 0, 3 << (buck * 2));
if (ret)
return ret;
ret = pmic_clrsetbits(pmic, REG_DCDC_UV_ACT, 1 << buck, 0);
if (ret)
return ret;
}
return pmic_clrsetbits(pmic, REG_DCDC_EN, mask, enable ? mask : 0);
}
static int pmic_tps65910_probe(struct udevice *dev)
{
/* use I2C control interface instead of I2C smartreflex interface to
* access smartrefelex registers VDD1_OP_REG, VDD1_SR_REG, VDD2_OP_REG
* and VDD2_SR_REG
*/
return pmic_clrsetbits(dev, TPS65910_REG_DEVICE_CTRL, 0,
TPS65910_I2C_SEL_MASK);
}
int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma)
{
uint i;
for (i = 0; i < ARRAY_SIZE(rk818_chrg_cur_input_array); i++)
if (current_ma <= rk818_chrg_cur_input_array[i])
break;
return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_ILIM_SEL_MASK, i);
}
static int switch_set_enable(struct udevice *dev, bool enable)
{
int sw = dev->driver_data - 1;
uint mask;
mask = 1 << (sw + 5);
return pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask,
enable ? mask : 0);
}
static int ldo_set_enable(struct udevice *dev, bool enable)
{
int ldo = dev->driver_data - 1;
uint mask;
mask = 1 << ldo;
return pmic_clrsetbits(dev->parent, REG_LDO_EN, mask,
enable ? mask : 0);
}
static int pm8916_gpio_set_value(struct udevice *dev, unsigned offset,
int value)
{
struct pm8916_gpio_bank *priv = dev_get_priv(dev);
uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
/* Set the output value of the gpio */
return pmic_clrsetbits(dev->parent, gpio_base + REG_CTL,
REG_CTL_OUTPUT_MASK, !!value);
}
static int reg_set_value(struct udevice *dev, int uvolt)
{
int reg = dev->driver_data;
int val;
val = check_volt_table(voltage_map, uvolt);
if (val < 0)
return val;
return pmic_clrsetbits(dev->parent, addr_vol[reg], LDO_VOL_MASK, val);
}
int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt)
{
uint i;
for (i = 0; i < ARRAY_SIZE(rk818_chrg_shutdown_vsel_array); i++)
if (uvolt <= rk818_chrg_shutdown_vsel_array[i])
break;
return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_CHG_SD_VSEL_MASK,
i);
}
static int _buck_set_value(struct udevice *pmic, int buck, int uvolt)
{
const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck - 1);
int mask = info->vsel_mask;
int val;
if (info->vsel_reg == -1)
return -ENOSYS;
val = (uvolt - info->min_uv) / info->step_uv;
debug("%s: reg=%x, mask=%x, val=%x\n", __func__, info->vsel_reg, mask,
val);
return pmic_clrsetbits(pmic, info->vsel_reg, mask, val);
}
static int ldo_set_value(struct udevice *dev, int uvolt)
{
int ldo = dev->driver_data - 1;
const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo);
int mask = info->vsel_mask;
int val;
if (info->vsel_reg == -1)
return -ENOSYS;
val = (uvolt - info->min_uv) / info->step_uv;
debug("%s: reg=%x, mask=%x, val=%x\n", __func__, info->vsel_reg, mask,
val);
return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val);
}
int power_init_board(void)
{
struct udevice *dev;
int reg, ver;
int ret;
ret = pmic_get("rn5t567", &dev);
if (ret)
return ret;
ver = pmic_reg_read(dev, RN5T567_LSIVER);
reg = pmic_reg_read(dev, RN5T567_OTPVER);
printf("PMIC: RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);
/* set judge and press timer of N_OE to minimal values */
pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
return 0;
}
int s5m8767_enable_32khz_cp(struct udevice *dev)
{
return pmic_clrsetbits(dev, S5M8767_EN32KHZ_CP, 0, 1 << 1);
}
