/**
* If the PLL settings are in place switch the CPU core frequency to the max. value
*/
static int pcm038_power_init(void)
{
uint32_t spctl0;
int ret;
spctl0 = get_pll_spctl10();
/* PLL registers already set to their final values? */
if (spctl0 == SPCTL0_VAL && MPCTL0 == MPCTL0_VAL) {
console_flush();
ret = pmic_power();
if (ret == 0) {
/* wait for required power level to run the CPU at 400 MHz */
udelay(100000);
CSCR = CSCR_VAL_FINAL;
PCDR0 = 0x130410c3;
PCDR1 = 0x09030911;
/* Clocks have changed. Notify clients */
clock_notifier_call_chain();
} else {
printf("Failed to initialize PMIC. Will continue with low CPU speed\n");
}
}
/* clock gating enable */
GPCR = 0x00050f08;
return 0;
}
static int pcm038_power_init(void)
{
int ret;
printf("initialising PLLs\n");
console_flush();
ret = pmic_power();
if (ret) {
printf("Failed to initialize PMIC. Will continue with low CPU speed\n");
return 0;
}
/* wait for good power level */
udelay(100000);
#define CSCR_VAL CSCR_USB_DIV(3) | \
CSCR_SD_CNT(3) | \
CSCR_MSHC_SEL | \
CSCR_H264_SEL | \
CSCR_SSI1_SEL | \
CSCR_SSI2_SEL | \
CSCR_MCU_SEL | \
CSCR_ARM_SRC_MPLL | \
CSCR_SP_SEL | \
CSCR_ARM_DIV(0) | \
CSCR_FPM_EN | \
CSCR_SPEN | \
CSCR_MPEN
/*
* pll clock initialization - see section 3.4.3 of the i.MX27 manual
*/
MPCTL0 = IMX_PLL_PD(0) |
IMX_PLL_MFD(51) |
IMX_PLL_MFI(7) |
IMX_PLL_MFN(35); /* MPLL = 399 MHz */
SPCTL0 = IMX_PLL_PD(1) |
IMX_PLL_MFD(12) |
IMX_PLL_MFI(9) |
IMX_PLL_MFN(3); /* SPLL = 240 MHz */
/*
* ARM clock = (399 MHz / 2) / (ARM divider = 1) = 200 MHz
* AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz
* System clock (HCLK) = 133 MHz
*/
pll_wait();
CSCR = CSCR_VAL | CSCR_AHB_DIV(1) | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART;
pll_wait();
/* clock gating enable */
GPCR = 0x00050f08;
PCDR0 = 0x130410c3;
PCDR1 = 0x09030911;
/* Clocks have changed. Notify clients */
clock_notifier_call_chain();
return 0;
}
