void pmic_voltage_init(void)
{
t_regulator_voltage volt;
/* Enable 4 mc13783 output voltages */
pmic_write_reg(REG_ARBITRATION_SWITCHERS, (1 << 5), (1 << 5));
/* Set mc13783 DVS speed 25mV each 4us */
pmic_write_reg(REG_SWITCHERS_4, (0 << 6), (3 << 6));
if (cpu_is_mx31())
volt.sw1a = SW1A_1_625V;
else
volt.sw1a = SW1A_1_425V;
pmic_power_regulator_set_voltage(SW_SW1A, volt);
volt.sw1a = SW1A_1_25V;
pmic_power_switcher_set_dvs(SW_SW1A, volt);
if (cpu_is_mx32()) {
volt.sw1a = SW1A_0_975V;
pmic_power_switcher_set_stby(SW_SW1A, volt);
}
volt.sw1b = SW1A_1_25V;
pmic_power_switcher_set_dvs(SW_SW1B, volt);
volt.sw1b = SW1A_1_25V;
pmic_power_switcher_set_stby(SW_SW1B, volt);
}
static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
unsigned int tod_reg_val = 0;
unsigned int day_reg_val = 0;
unsigned int mask, value;
unsigned long time;
if (rtc_valid_tm(&alrm->time))
return -1;
rtc_tm_to_time(&alrm->time, &time);
tod_reg_val = time % 86400;
day_reg_val = time / 86400;
mask = BITFMASK(RTCALARM_TIME);
value = BITFVAL(RTCALARM_TIME, tod_reg_val);
CHECK_ERROR(pmic_write_reg(REG_RTC_ALARM, value, mask));
mask = BITFMASK(RTCALARM_DAY);
value = BITFVAL(RTCALARM_DAY, day_reg_val);
CHECK_ERROR(pmic_write_reg(REG_RTC_DAY_ALARM, value, mask));
return 0;
}
void pmic_init(unsigned bus)
{
/*
* Don't need to set up VDD_CORE - already done - by OTP
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
*/
/* Restore PMIC POR defaults, in case kernel changed 'em */
pmic_slam_defaults(bus);
/* First set VDD_CPU to 1.2V, then enable the VDD_CPU regulator. */
pmic_write_reg(bus, 0x00, 0x50, 1);
/* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */
pmic_write_reg(bus, 0x06, 0x28, 1);
/*
* First set +1.2V_GEN_AVDD to 1.2V, then enable the +1.2V_GEN_AVDD
* regulator.
*/
pmic_write_reg(bus, 0x12, 0x10, 1);
/*
* Panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set
* the value (register 0x20 bit 4)
*/
pmic_write_reg(bus, 0x0c, 0x07, 0);
pmic_write_reg(bus, 0x20, 0x10, 1);
}
static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
unsigned int tod_reg_val = 0;
unsigned int day_reg_val, day_reg_val2 = 0;
unsigned int mask, value;
unsigned long time;
if (rtc_valid_tm(tm))
return -1;
rtc_tm_to_time(tm, &time);
tod_reg_val = time % 86400;
day_reg_val = time / 86400;
do {
mask = BITFMASK(RTC_DAY);
value = BITFVAL(RTC_DAY, day_reg_val);
CHECK_ERROR(pmic_write_reg(REG_RTC_DAY, value, mask));
mask = BITFMASK(RTC_TIME);
value = BITFVAL(RTC_TIME, tod_reg_val);
CHECK_ERROR(pmic_write_reg(REG_RTC_TIME, value, mask));
mask = BITFMASK(RTC_DAY);
CHECK_ERROR(pmic_read_reg(REG_RTC_DAY, &value, mask));
day_reg_val2 = BITFEXT(value, RTC_DAY);
} while (day_reg_val != day_reg_val2);
return 0;
}
/*
* Battery low cancel_suspend
* cancel suspend mode
*/
static void battery_low_suspend_cancel (void)
{
int rc;
pmic_event_callback_t bat_event_callback;
/*
* interrupt restore
*/
pmic_event_for_resume ();
/*
* restore alarm
*/
if (pre_alarm [0] == 1) {
pre_alarm [0] = 0;
rc = pmic_write_reg (REG_RTC_ALARM, pre_alarm [1], 0x01FFFF);
if (rc == 0) {
rc = pmic_write_reg (REG_RTC_DAY_ALARM, pre_alarm [2], 0x007FFF);
}
if (rc != 0) {
printk ("battery_low_resume: restore TODA/DAYA error %d\n", rc);
}
bat_event_callback.func = battery_poll_callback;
bat_event_callback.param = (void *)0;
pmic_event_unsubscribe (EVENT_TODAI, bat_event_callback);
}
}
/*
* PMIC alarm set
*/
static int battery_set_alarm (void)
{
int rc;
unsigned int toda, daya;
/*
* wakeup after check interval
*/
rc = pmic_read_reg (REG_RTC_TIME, &toda, 0x01FFFF);
if (rc == 0) {
rc = pmic_read_reg (REG_RTC_DAY, &daya, 0x007FFF);
}
if (rc != 0) {
printk ("battery_set_alarm: get TODA/DAYA error %d\n", rc);
return -1;
}
toda += batt_poll_interval;
if ((24 * 60 * 60) <= toda) {
toda -= (24 * 60 * 60);
daya++;
}
rc = pmic_write_reg (REG_RTC_ALARM, toda, 0x01FFFF);
if (rc == 0) {
rc = pmic_write_reg (REG_RTC_DAY_ALARM, daya, 0x007FFF);
}
if (rc != 0) {
printk ("battery_set_alarm: set TODA/DAYA error %d\n", rc);
return -1;
}
return 0;
}
/* Called during ship mode */
void gpio_watchdog_low(void)
{
printk(KERN_CRIT "Halting ...\n");
/* configure the PMIC for WDIRESET */
pmic_write_reg(REG_POWER_CTL2, (0 << WDIRESET_LSH), (1 << WDIRESET_LSH));
/* Turn on RESTARTEN */
pmic_write_reg(REG_POWER_CTL2, (1 << RESTARTEN_LSH), (1 << RESTARTEN_LSH));
/* Free WDOG as ALT2 */
mxc_free_iomux(MX50_PIN_WDOG, IOMUX_CONFIG_ALT2);
/* Re-request as GPIO */
mxc_request_iomux(MX50_PIN_WDOG, IOMUX_CONFIG_ALT1);
/* Pad settings */
mxc_iomux_set_pad(MX50_PIN_WDOG, PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE |
PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE);
/* Enumerate */
gpio_request(IOMUX_TO_GPIO(MX50_PIN_WDOG), "wdog");
/* Direction output */
gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_WDOG), 0);
/* Set low */
gpio_set_value(IOMUX_TO_GPIO(MX50_PIN_WDOG), 0);
}
static int pmic_calibrate_coulomb_counter(void)
{
int ret;
unsigned int value;
/* set scaler */
CHECK_ERROR(pmic_write_reg(REG_ACC1,
0x1, BITFMASK(ACC1_ONEC)));
CHECK_ERROR(pmic_write_reg(
REG_ACC0, ACC_CALIBRATION, ACC_CONTROL_BIT_MASK));
msleep(ACC_CALIBRATION_DURATION_MSECS);
ret = pmic_read_reg(REG_ACC0, &value, BITFMASK(ACC_CCOUT));
if (ret != 0)
return -1;
value = BITFEXT(value, ACC_CCOUT);
pr_debug("calibrate value = %x\n", value);
coulomb_counter_calibration = (int)((s16)((u16) value));
pr_debug("coulomb_counter_calibration = %d\n",
coulomb_counter_calibration);
return 0;
}
void pmic_voltage_init(void)
{
t_regulator_voltage volt;
/* Enable 4 mc13783 output voltages */
pmic_write_reg(REG_ARBITRATION_SWITCHERS, 1, (1 << 5));
/* Enable mc13783 voltage ready signal */
pmic_write_reg(REG_INTERRUPT_MASK_1, 0, (1 << 11));
/* Set mc13783 DVS speed 25mV each 4us */
pmic_write_reg(REG_SWITCHERS_4, 1, (1 << 6));
pmic_write_reg(REG_SWITCHERS_4, 0, (1 << 7));
volt.sw1a = SW1A_1_625V;
pmic_power_regulator_set_voltage(SW_SW1A, volt);
volt.sw1a = SW1A_1_25V;
pmic_power_switcher_set_dvs(SW_SW1A, volt);
volt.sw1b = SW1A_1_25V;
pmic_power_switcher_set_dvs(SW_SW1B, volt);
volt.sw1b = SW1A_1_25V;
pmic_power_switcher_set_stby(SW_SW1B, volt);
}
static int mc34708_regulator_init(struct mc34708 *mc34708)
{
unsigned int value, register_mask;
pmic_read_reg(REG_MC34708_IDENTIFICATION, &value, 0xffffff);
pr_info("PMIC MC34708 ID:0x%x\n", value);
/* enable standby controll for mode0 regulators */
pmic_read_reg(REG_MC34708_MODE_0, &value, 0xffffff);
value &= ~(REG_MODE_0_ALL_MASK | USB_EN_MASK);
value |= REG_MODE_0_ALL_MASK;
pmic_write_reg(REG_MC34708_MODE_0, value, 0xffffff);
/* enable standby controll for mode0 regulators */
pmic_read_reg(REG_MC34708_SW_1_2_OP, &value, 0xffffff);
value &= ~REG_SW_1_2_MASK;
value |= REG_SW_1_2_VALUE;
pmic_write_reg(REG_MC34708_SW_1_2_OP, value, 0xffffff);
/* enable standby controll for mode0 regulators */
pmic_read_reg(REG_MC34708_SW_3_4_5_OP, &value, 0xffffff);
value &= ~REG_SW_3_4_5_MASK;
value |= REG_SW_3_4_5_VALUE;
pmic_write_reg(REG_MC34708_SW_3_4_5_OP, value, 0xffffff);
/* enable standby controll for mode0 regulators */
pmic_read_reg(REG_MC34708_SWBST, &value, 0xffffff);
value &= ~REG_SWBST_MODE_MASK;
value |= REG_SWBST_MODE_VALUE;
pmic_write_reg(REG_MC34708_SWBST, value, 0xffffff);
/* clear SWHOLD bit to enable USB MUX */
pmic_read_reg(REG_MC34708_USB_CONTROL, &value, 0xffffff);
value &= ~SWHOLD_MASK;
pmic_write_reg(REG_MC34708_USB_CONTROL, value, 0xffffff);
pr_info("Initializing mc34708 regulators for mx50 rdp.\n");
mc34708_register_regulator(mc34708, MC34708_SW1A, &sw1a_init);
mc34708_register_regulator(mc34708, MC34708_SW1B, &sw1b_init);
mc34708_register_regulator(mc34708, MC34708_SW2, &sw2_init);
mc34708_register_regulator(mc34708, MC34708_SW3, &sw3_init);
mc34708_register_regulator(mc34708, MC34708_SW4A, &sw4a_init);
mc34708_register_regulator(mc34708, MC34708_SW4B, &sw4b_init);
mc34708_register_regulator(mc34708, MC34708_SW5, &sw5_init);
mc34708_register_regulator(mc34708, MC34708_SWBST, &swbst_init);
mc34708_register_regulator(mc34708, MC34708_VPLL, &vpll_init);
mc34708_register_regulator(mc34708, MC34708_VREFDDR, &vrefddr_init);
mc34708_register_regulator(mc34708, MC34708_VDAC, &vdac_init);
mc34708_register_regulator(mc34708, MC34708_VUSB, &vusb_init);
mc34708_register_regulator(mc34708, MC34708_VUSB2, &vusb2_init);
mc34708_register_regulator(mc34708, MC34708_VGEN1, &vgen1_init);
mc34708_register_regulator(mc34708, MC34708_VGEN2, &vgen2_init);
regulator_has_full_constraints();
return 0;
}
static int enable_lcd_vdd(void)
{
uint8_t data;
/* Set 1.20V to power AVDD_DSI_CSI */
pmic_write_reg(I2CPWR_BUS, TI65913_LDO5_VOLTAGE,
VSEL_1200, 1);
pmic_write_reg(I2CPWR_BUS, TI65913_LDO5_CTRL,
TI65913_MODE_ACTIVE_ON, 1);
/*
* Enable VDD_LCD
*
* Use different GPIO based on board id
*/
switch (board_id()) {
case BOARD_ID_PROTO_0:
/* Select PMIC GPIO_6's primary function */
pmic_read_reg(I2CPWR_BUS, TI65913_PAD2, &data);
pmic_write_reg(I2CPWR_BUS, TI65913_PAD2,
PAD2_GPIO_6_PRIMARY(data), 0);
/* Set PMIC_GPIO_6 as output */
pmic_read_reg(I2CPWR_BUS, TI65913_GPIO_DATA_DIR, &data);
pmic_write_reg(I2CPWR_BUS, TI65913_GPIO_DATA_DIR,
TI65913_GPIO_6_OUTPUT, 0);
/* Set PMIC_GPIO_6 output high */
pmic_read_reg(I2CPWR_BUS, TI65913_GPIO_DATA_OUT, &data);
pmic_write_reg(I2CPWR_BUS, TI65913_GPIO_DATA_OUT,
TI65913_GPIO_6_HIGH, 1);
break;
case BOARD_ID_PROTO_1:
case BOARD_ID_PROTO_3:
gpio_set(EN_VDD_LCD, 1);
break;
default: /* unknown board */
return -1;
}
/* wait for 2ms */
mdelay(2);
/* Enable PP1800_LCDIO to panel */
gpio_set(EN_VDD18_LCD, 1);
/* wait for 1ms */
mdelay(1);
/* Set panel EN and RST signals */
gpio_set(LCD_EN, 1); /* enable */
/* wait for min 10ms */
mdelay(10);
gpio_set(LCD_RST_L, 1); /* clear reset */
/* wait for min 3ms */
mdelay(3);
return 0;
}
int pmic_light_init_reg(void)
{
CHECK_ERROR(pmic_write_reg(REG_LED_CTL0, 0, PMIC_ALL_BITS));
CHECK_ERROR(pmic_write_reg(REG_LED_CTL1, 0, PMIC_ALL_BITS));
CHECK_ERROR(pmic_write_reg(REG_LED_CTL2, 0, PMIC_ALL_BITS));
CHECK_ERROR(pmic_write_reg(REG_LED_CTL3, 0, PMIC_ALL_BITS));
return 0;
}
static int mc34708_regulator_init(struct mc34708 *mc34708)
{
unsigned int value;
pmic_read_reg(REG_MC34708_IDENTIFICATION, &value, 0xffffff);
pr_info("PMIC MC34708 ID:0x%x\n", value);
/* setting switch operating mode for SW1/2 regulators */
pmic_read_reg(REG_MC34708_SW_1_2_OP, &value, 0xffffff);
value &= ~REG_SW_1_2_MASK;
value |= REG_SW_1_2_VALUE;
pmic_write_reg(REG_MC34708_SW_1_2_OP, value, 0xffffff);
/* setting switch operating mode for SW3/4/5 regulators */
pmic_read_reg(REG_MC34708_SW_3_4_5_OP, &value, 0xffffff);
value &= ~REG_SW_3_4_5_MASK;
value |= REG_SW_3_4_5_VALUE;
pmic_write_reg(REG_MC34708_SW_3_4_5_OP, value, 0xffffff);
/* setting switch operating mode for SWBST regulators */
pmic_read_reg(REG_MC34708_SWBST, &value, 0xffffff);
value &= ~REG_SWBST_MODE_MASK;
value |= REG_SWBST_MODE_VALUE;
pmic_write_reg(REG_MC34708_SWBST, value, 0xffffff);
/* clear SWHOLD bit to enable USB MUX */
pmic_read_reg(REG_MC34708_USB_CONTROL, &value, 0xffffff);
value &= ~SWHOLD_MASK;
pmic_write_reg(REG_MC34708_USB_CONTROL, value, 0xffffff);
/* enable WDI reset*/
pmic_read_reg(REG_MC34708_POWER_CTL2, &value, 0xffffff);
value |= 0x1000;
pmic_write_reg(REG_MC34708_POWER_CTL2, value, 0xffffff);
mc34708_register_regulator(mc34708, MC34708_SW1A, &sw1a_init);
mc34708_register_regulator(mc34708, MC34708_SW1B, &sw1b_init);
mc34708_register_regulator(mc34708, MC34708_SW2, &sw2_init);
mc34708_register_regulator(mc34708, MC34708_SW3, &sw3_init);
mc34708_register_regulator(mc34708, MC34708_SW4A, &sw4a_init);
mc34708_register_regulator(mc34708, MC34708_SW4B, &sw4b_init);
mc34708_register_regulator(mc34708, MC34708_SW5, &sw5_init);
mc34708_register_regulator(mc34708, MC34708_SWBST, &swbst_init);
mc34708_register_regulator(mc34708, MC34708_VPLL, &vpll_init);
mc34708_register_regulator(mc34708, MC34708_VREFDDR, &vrefddr_init);
mc34708_register_regulator(mc34708, MC34708_VDAC, &vdac_init);
mc34708_register_regulator(mc34708, MC34708_VUSB, &vusb_init);
mc34708_register_regulator(mc34708, MC34708_VUSB2, &vusb2_init);
mc34708_register_regulator(mc34708, MC34708_VGEN1, &vgen1_init);
mc34708_register_regulator(mc34708, MC34708_VGEN2, &vgen2_init);
regulator_has_full_constraints();
return 0;
}
static int mc13892_regulator_init(struct mc13892 *mc13892)
{
unsigned int value;
pmic_event_callback_t power_key_event;
int register_mask;
pr_info("Initializing regulators for MX53 EVK \n");
/* subscribe PWRON1 event to enable ON_OFF key */
power_key_event.param = NULL;
power_key_event.func = (void *)power_on_evt_handler;
pmic_event_subscribe(EVENT_PWRONI, power_key_event);
/* Bit 4 DRM: keep VSRTC and CLK32KMCU on for all states */
#if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE)
value = BITFVAL(DRM, 1);
register_mask = BITFMASK(DRM);
pmic_write_reg(REG_POWER_CTL0, value, register_mask);
#endif
/* Set the STANDBYSECINV bit, so that STANDBY pin is
* interpreted as active low.
*/
value = BITFVAL(STANDBYSECINV, 1);
register_mask = BITFMASK(STANDBYSECINV);
pmic_write_reg(REG_POWER_CTL2, value, register_mask);
/* Disable coin cell charger since the cell is not rechargeable */
value = BITFVAL(COINCHEN, 0) | BITFVAL(VCOIN, VCOIN_3_0V);
register_mask = BITFMASK(COINCHEN) | BITFMASK(VCOIN);
pmic_write_reg(REG_POWER_CTL0, value, register_mask);
mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init);
mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init);
mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init);
mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init);
mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init);
mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init);
mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init);
mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init);
mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init);
mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init);
mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init);
mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init);
mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init);
mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init);
mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init);
mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init);
mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init);
mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init);
mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init);
mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init);
mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init);
return 0;
}
void pmic_init(unsigned bus)
{
/* Restore PMIC POR defaults, in case kernel changed 'em */
pmic_slam_defaults(bus);
/* A44: Set VDD_CPU to 1.0V. */
pmic_write_reg(bus, TI65913_SMPS12_VOLTAGE, 0x38, 0);
pmic_write_reg(bus, TI65913_SMPS12_CTRL, 0x01, 1);
printk(BIOS_DEBUG, "PMIC init done\n");
}
/*!
* This is the suspend of power management for the mc13783 ADC API.
* It supports SAVE and POWER_DOWN state.
*
* @param pdev the device
* @param state the state
*
* @return This function returns 0 if successful.
*/
static int pmic_adc_suspend(struct platform_device *pdev, pm_message_t state)
{
unsigned int reg_value = 0;
suspend_flag = 1;
CHECK_ERROR(pmic_write_reg(REG_ADC_0, DEF_ADC_0, PMIC_ALL_BITS));
CHECK_ERROR(pmic_write_reg(REG_ADC_1, reg_value, PMIC_ALL_BITS));
CHECK_ERROR(pmic_write_reg(REG_ADC_2, reg_value, PMIC_ALL_BITS));
CHECK_ERROR(pmic_write_reg(REG_ADC_3, DEF_ADC_3, PMIC_ALL_BITS));
CHECK_ERROR(pmic_write_reg(REG_ADC_4, reg_value, PMIC_ALL_BITS));
return 0;
};
int pmic_light_init_reg(void)
{
if (yoshi_button_green_led)
return 0;
CHECK_ERROR(pmic_write_reg(REG_LED_CTL0, 0, PMIC_ALL_BITS));
CHECK_ERROR(pmic_write_reg(REG_LED_CTL1, 0, PMIC_ALL_BITS));
CHECK_ERROR(pmic_write_reg(REG_LED_CTL2, 0, PMIC_ALL_BITS));
CHECK_ERROR(pmic_write_reg(REG_LED_CTL3, 0, PMIC_ALL_BITS));
return 0;
}
static int pmic_start_coulomb_counter(void)
{
/* set scaler */
CHECK_ERROR(pmic_write_reg(REG_ACC1,
ACC_COULOMB_PER_LSB * ACC_ONEC_VALUE, BITFMASK(ACC1_ONEC)));
CHECK_ERROR(pmic_write_reg(
REG_ACC0, ACC_START_COUNTER, ACC_CONTROL_BIT_MASK));
coulomb_counter_start_time_msecs = jiffies_to_msecs(jiffies);
pr_debug("coulomb counter start time %u\n",
coulomb_counter_start_time_msecs);
return 0;
}
static int mc13892_regulator_init(struct mc13892 *mc13892)
{
unsigned int value;
pmic_event_callback_t power_key_event;
int register_mask;
printk("Initializing regulators for 3-stack.\n");
if (mxc_cpu_is_rev(CHIP_REV_2_0) < 0)
sw2_init.constraints.state_mem.uV = 1100000;
/* subscribe PWRON1 event to enable ON_OFF key */
power_key_event.param = NULL;
power_key_event.func = (void *)power_on_evt_handler;
pmic_event_subscribe(EVENT_PWRONI, power_key_event);
/* Bit 4 DRM: keep VSRTC and CLK32KMCU on for all states */
pmic_read_reg(REG_POWER_CTL0, &value, 0xffffff);
value |= 0x000010;
pmic_write_reg(REG_POWER_CTL0, value, 0xffffff);
/* Set the STANDBYSECINV bit, so that STANDBY pin is
* interpreted as active low.
*/
value = BITFVAL(STANDBYSECINV, 1);
register_mask = BITFMASK(STANDBYSECINV);
pmic_write_reg(REG_POWER_CTL2, value, register_mask);
mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init);
mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init);
mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init);
mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init);
mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init);
mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init);
mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init);
mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init);
mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init);
mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init);
mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init);
mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init);
mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init);
mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init);
mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init);
mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init);
mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init);
mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init);
mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init);
mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init);
mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init);
return 0;
}
/*
* This function resets the system. It is called by machine_restart().
*
* @param mode indicates different kinds of resets
*/
void arch_reset(char mode)
{
unsigned long reg;
unsigned long reg_1 = 0xffffffff;
doze_disable();
reg = __raw_readl(MXC_CCM_CGR0);
reg |= (MXC_CCM_CGR0_ESDHC1_MASK | MXC_CCM_CGR0_ESDHC2_MASK |
MXC_CCM_CGR0_ESDHC3_MASK | MXC_CCM_CGR0_CSPI1_MASK |
MXC_CCM_CGR0_CSPI2_MASK);
__raw_writel(reg, MXC_CCM_CGR0);
reg = __raw_readl(MXC_CCM_CGR3);
reg |= MXC_CCM_CGR3_IIM_MASK;
__raw_writel(reg, MXC_CCM_CGR3);
printk(KERN_INFO "MX35 arch_reset\n");
if (in_interrupt() || kernel_oops_counter) {
mxc_wd_reset();
return;
}
local_irq_enable();
/* Clear out bit #1 in MEMA */
pmic_write_reg(REG_MEM_A, (0 << 1), (1 << 1));
/* Turn on bit #1 */
pmic_write_reg(REG_MEM_A, (1 << 1), (1 << 1));
/* Turn off VSD */
pmic_write_reg(REG_MODE_1, (0 << 18), (1 << 18));
cpufreq_suspended = 1;
set_cpu_freq(512000000);
mdelay(100);
peri_pll_enable();
__raw_writel(reg_1, MXC_CCM_CGR0);
__raw_writel(reg_1, MXC_CCM_CGR1);
__raw_writel(reg_1, MXC_CCM_CGR2);
__raw_writel(reg_1, MXC_CCM_CGR3);
mdelay(100);
/* Memory Hold Mode */
mx35_power_off();
}
int pmic_light_init_reg(void)
{
#ifdef CONFIG_MACH_LUIGI_LAB126
if (luigi_button_green_led)
return 0;
#endif
CHECK_ERROR(pmic_write_reg(REG_LED_CTL0, 0, PMIC_ALL_BITS));
CHECK_ERROR(pmic_write_reg(REG_LED_CTL1, 0, PMIC_ALL_BITS));
CHECK_ERROR(pmic_write_reg(REG_LED_CTL2, 0, PMIC_ALL_BITS));
CHECK_ERROR(pmic_write_reg(REG_LED_CTL3, 0, PMIC_ALL_BITS));
return 0;
}
/*!
* This function sets the accessory voltage
* on Atlas GPO3
*/
static void accessory_regulator_gpo3_voltage(int enable)
{
int ret = 0;
pr_debug("%s: %d\n", __func__, enable);
if (enable) {
ret = pmic_write_reg(REG_POWER_MISC, (GPO3_DISABLE << GPO3_LSH),
(GPO3_MASK << GPO3_LSH));
}
else {
ret = pmic_write_reg(REG_POWER_MISC, (GPO3_ENABLE << GPO3_LSH),
(GPO3_MASK << GPO3_LSH));
}
}
PMIC_STATUS mc13892_bklit_set_hi_current(enum lit_channel channel, int mode)
{
unsigned int mask;
unsigned int value;
int reg;
switch (channel) {
case LIT_MAIN:
value = BITFVAL(BIT_HC_MAIN, mode);
mask = BITFMASK(BIT_HC_MAIN);
reg = REG_LED_CTL0;
break;
case LIT_AUX:
value = BITFVAL(BIT_HC_AUX, mode);
mask = BITFMASK(BIT_HC_AUX);
reg = REG_LED_CTL0;
break;
case LIT_KEY:
value = BITFVAL(BIT_HC_KEY, mode);
mask = BITFMASK(BIT_HC_KEY);
reg = REG_LED_CTL1;
break;
default:
return PMIC_PARAMETER_ERROR;
}
CHECK_ERROR(pmic_write_reg(reg, value, mask));
return PMIC_SUCCESS;
}
static int __init accessory_port_init(void)
{
int err = 0, irq = gpio_accessory_get_irq();
printk(KERN_DEBUG "Initializing MX50 Yoshi Accessory Port\n");
err = request_irq(irq, accessory_port_irq, IRQF_DISABLED, "MX50_Accessory", NULL);
if (err != 0) {
printk(KERN_ERR "IRQF_DISABLED: Could not get IRQ %d\n", irq);
return err;
}
disable_irq(irq);
/* Set the correct IRQ trigger based on accessory charger state */
if (gpio_accessory_charger_detected())
set_irq_type(irq, IRQF_TRIGGER_FALLING);
else
set_irq_type(irq, IRQF_TRIGGER_RISING);
enable_irq(irq);
/* always enable Apollo while device is running */
accessory_charger_enable();
if (mx50_accessory_sysdev_ctrl_init() < 0)
printk(KERN_ERR "mx50_accessory: Could not create sysfs interface\n");
register_reboot_notifier(&mx50_accessory_reboot_nb);
pmic_write_reg(REG_MODE_0, VIOHI_EN << VIOHI_EN_LSH, VIOHI_EN_MASK << VIOHI_EN_LSH);
return err;
}
static int mc13892_gpo_disable(struct regulator *reg)
{
unsigned int register_val = 0, register_mask = 0;
unsigned int register1;
int gpo = reg->id;
switch (gpo) {
case MC13892_GPO1:
register_val = BITFVAL(GPO1_EN, GPO1_EN_DISABLE);
register_mask = BITFMASK(GPO1_EN);
break;
case MC13892_GPO2:
register_val = BITFVAL(GPO2_EN, GPO2_EN_DISABLE);
register_mask = BITFMASK(GPO2_EN);
break;
case MC13892_GPO3:
register_val = BITFVAL(GPO3_EN, GPO3_EN_DISABLE);
register_mask = BITFMASK(GPO3_EN);
break;
case MC13892_GPO4:
register_val = BITFVAL(GPO4_EN, GPO4_EN_DISABLE);
register_mask = BITFMASK(GPO4_EN);
break;
default:
return -EINVAL;
};
register1 = REG_POWER_MISC;
return (pmic_write_reg(register1, register_val, register_mask));
}
static int mc13892_sw_dvs_set_voltage(struct regulator *reg, int uV)
{
unsigned int register_val = 0, register_mask = 0;
unsigned int register1 = 0;
int voltage, sw = reg->id, mV = uV / 1000, hi;
hi = mc13892_get_sw_hi_bit(sw);
voltage = mc13892_get_voltage_value(hi, mV);
switch (sw) {
case MC13892_SW1:
register1 = REG_SW_0;
register_val = BITFVAL(SW1_DVS, voltage);
register_mask = BITFMASK(SW1_DVS);
break;
case MC13892_SW2:
register1 = REG_SW_1;
register_val = BITFVAL(SW2_DVS, voltage);
register_mask = BITFMASK(SW2_DVS);
break;
default:
return -EINVAL;
}
return (pmic_write_reg(register1, register_val, register_mask));
}
static int mxc_rtc_ioctl(struct device *dev, unsigned int cmd,
unsigned long arg)
{
switch (cmd) {
case RTC_AIE_OFF:
pr_debug("alarm off\n");
CHECK_ERROR(pmic_write_reg(REG_RTC_ALARM, 0x100000, 0x100000));
return 0;
case RTC_AIE_ON:
pr_debug("alarm on\n");
CHECK_ERROR(pmic_write_reg(REG_RTC_ALARM, 0, 0x100000));
return 0;
}
return -ENOIOCTLCMD;
}
static int mc13892_vsd_set_voltage(struct regulator *reg, int uV)
{
unsigned int register_val = 0, register_mask = 0;
unsigned int register1;
int voltage, mV = uV / 1000;
if ((mV >= 1800) && (mV < 2000))
voltage = VSD_1_8V;
else if ((mV >= 2000) && (mV < 2600))
voltage = VSD_2_0V;
else if ((mV >= 2600) && (mV < 2700))
voltage = VSD_2_6V;
else if ((mV >= 2700) && (mV < 2800))
voltage = VSD_2_7V;
else if ((mV >= 2800) && (mV < 2900))
voltage = VSD_2_8V;
else if ((mV >= 2900) && (mV < 3000))
voltage = VSD_2_9V;
else if ((mV >= 3000) && (mV < 3150))
voltage = VSD_3_0V;
else
voltage = VSD_3_15V;
register_val = BITFVAL(VSD, voltage);
register_mask = BITFMASK(VSD);
register1 = REG_SETTING_1;
return (pmic_write_reg(register1, register_val, register_mask));
}
static void pmic_slam_defaults(unsigned bus)
{
int i;
for (i = 0; i < AS3722_INIT_REG_LEN; i++)
pmic_write_reg(bus, init_list[i].reg, init_list[i].val);
}
PMIC_STATUS mc13892_bklit_set_blink_p(enum lit_channel channel, int period)
{
unsigned int mask;
unsigned int value;
int reg;
switch (channel) {
case LIT_RED:
value = BITFVAL(BIT_BP_RED, period);
mask = BITFMASK(BIT_BP_RED);
reg = REG_LED_CTL2;
break;
case LIT_GREEN:
value = BITFVAL(BIT_BP_GREEN, period);
mask = BITFMASK(BIT_BP_GREEN);
reg = REG_LED_CTL2;
break;
case LIT_BLUE:
value = BITFVAL(BIT_BP_BLUE, period);
mask = BITFMASK(BIT_BP_BLUE);
reg = REG_LED_CTL3;
break;
default:
return PMIC_PARAMETER_ERROR;
}
CHECK_ERROR(pmic_write_reg(reg, value, mask));
return PMIC_SUCCESS;
}
