void speaker_init(uint8_t time) {
/* SB600 RRG.
* Options_0 - RW - 8 bits - [PM_Reg: 60h].
* SpkrEn, bit[5]=1b, Setting this bit will configure GPIO2 to be speaker output.
*/
#ifdef __PRE_RAM__
pmio_write(0x60, (pmio_read(0x60) | (1<<5)));
#else
pm_iowrite(0x60, (pm_ioread(0x60) | (1<<5)));
#endif /* __PRE_RAM__ */
/* SB600 RRG.
* Tmr1CntrlWord - RW - 8 bits - [IO_Reg: 43h].
* ModeSelect, bit[3:1]=011b, Square wave output.
* CmmandSelect, bit[5:4]=11b, Read/write least, and then most significant byte.
* CounterSelect, bit[7:6]=10b, Select counter 2.
*/
outb(0xb6, 0x43);
/* SB600 RRG.
* TimerCh2- RW - 8 bits - [IO_Reg: 42h].
*/
outb(time, 0x42);
}
/*
* SB600 VFSMAF (VID/FID System Management Action Field) is 010b by default.
* RPR 2.3.3 C-state and VID/FID change for the K8 platform.
*/
static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
{
u8 byte;
byte = pmio_read(0x9a);
byte &= ~0x34;
if (dual_core())
byte |= 0x34;
else
byte |= 0x04;
pmio_write(0x9a, byte);
byte = pmio_read(0x8f);
byte &= ~0x30;
byte |= 0x20;
pmio_write(0x8f, byte);
pmio_write(0x8b, 0x01);
pmio_write(0x8a, 0x90);
if(get_sb600_revision() > 0x13)
pmio_write(0x88, 0x10);
else
pmio_write(0x88, 0x06);
byte = pmio_read(0x7c);
byte &= ~0x01;
byte |= 0x01;
pmio_write(0x7c, byte);
/* Must be 0 for K8 platform. */
byte = pmio_read(0x68);
byte &= ~0x01;
pmio_write(0x68, byte);
/* Must be 0 for K8 platform. */
byte = pmio_read(0x8d);
byte &= ~(1<<6);
pmio_write(0x8d, byte);
byte = pmio_read(0x61);
byte &= ~0x04;
pmio_write(0x61, byte);
byte = pmio_read(0x42);
byte &= ~0x04;
pmio_write(0x42, byte);
if (get_sb600_revision() == 0x14) {
pmio_write(0x89, 0x10);
byte = pmio_read(0x52);
byte |= 0x80;
pmio_write(0x52, byte);
}
}
static void sb800_pmio_por_init(void)
{
u8 byte, i;
printk(BIOS_INFO, "sb800_pmio_por_init()\n");
byte = pmio_read(0xD2);
byte |= 3 << 4;
pmio_write(0xD2, byte);
byte = pmio_read(0x5D);
byte &= 3;
byte |= 1;
pmio_write(0x5D, byte);
/* Watch Dog Timer Control
* Set watchdog time base to 0xfec000f0 to avoid SCSI card boot failure.
* But I don't find WDT is enabled in SMBUS 0x41 bit3 in CIM.
*/
pmio_write(0x6c, 0xf0);
pmio_write(0x6d, 0x00);
pmio_write(0x6e, 0xc0);
pmio_write(0x6f, 0xfe);
/* rpr2.15: Enabling Spread Spectrum */
byte = pmio_read(0x42);
byte |= 1 << 7;
pmio_write(0x42, byte);
/* TODO: Check if it is necessary. IDE reset */
byte = pmio_read(0xB2);
byte |= 1 << 0;
pmio_write(0xB2, byte);
for (i=0; i<sizeof(pm_table)/sizeof(struct pm_entry); i++) {
byte = pmio_read(pm_table[i].port);
byte &= pm_table[i].mask;
byte |= pm_table[i].bit;
pmio_write(pm_table[i].port, byte);
}
pmio_write(0x00, 0x0E);
pmio_write(0x01, 0x00);
pmio_write(0x02, 0x4F);
pmio_write(0x03, 0x4A);
}
/*
* Add any south bridge setting.
*/
static void sb800_pci_cfg(void)
{
device_t dev;
u8 byte;
/* SMBus Device, BDF:0-20-0 */
dev = PCI_DEV(0, 0x14, 0);//pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
/* Enable watchdog decode timer */
byte = pci_read_config8(dev, 0x41);
byte |= (1 << 3);
pci_write_config8(dev, 0x41, byte);
/* rpr 7.4. Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
* generated PCIRST#. */
byte = pmio_read(0xF0);
byte |= (1 << 2);
pmio_write(0xF0, byte);
/* IDE Device, BDF:0-20-1 */
dev = PCI_DEV(0, 0x14, 1);//pci_locate_device(PCI_ID(0x1002, 0x439C), 0);
/* Enable IDE Explicit prefetch, 0x63[0] clear */
byte = pci_read_config8(dev, 0x63);
byte &= 0xfe;
pci_write_config8(dev, 0x63, byte);
/* LPC Device, BDF:0-20-3 */
/* The code below is ported from old chipset. It is not
* metioned in RPR. But I keep them. The registers and the
* comments are compatible. */
dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
/* Enabling LPC DMA function. */
byte = pci_read_config8(dev, 0x40);
byte |= (1 << 2);
pci_write_config8(dev, 0x40, byte);
/* Disabling LPC TimeOut. 0x48[7] clear. */
byte = pci_read_config8(dev, 0x48);
byte &= 0x7f;
pci_write_config8(dev, 0x48, byte);
/* Disabling LPC MSI Capability, 0x78[1] clear. */
byte = pci_read_config8(dev, 0x78);
byte &= 0xfd;
pci_write_config8(dev, 0x78, byte);
/* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */
dev = PCI_DEV(0, 0x11, 0);//pci_locate_device(PCI_ID(0x1002, 0x4390), 0);
/* rpr7.12 SATA MSI and D3 Power State Capability. */
byte = pci_read_config8(dev, 0x40);
byte |= 1 << 0;
pci_write_config8(dev, 0x40, byte);
if (get_sb800_revision() <= 0x12)
pci_write_config8(dev, 0x34, 0x70); /* set 0x61 to 0x70 if S1 is not supported. */
else
pci_write_config8(dev, 0x34, 0x50); /* set 0x61 to 0x50 if S1 is not supported. */
byte &= ~(1 << 0);
pci_write_config8(dev, 0x40, byte);
}
/***************************************
* Legacy devices are mapped to LPC space.
* Serial port 0
* KBC Port
* ACPI Micro-controller port
* LPC ROM size
* This function does not change port 0x80 decoding.
* Console output through any port besides 0x3f8 is unsupported.
* If you use FWH ROMs, you have to setup IDSEL.
***************************************/
static void sb800_lpc_init(void)
{
u8 reg8;
device_t dev;
//dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */
dev = PCI_DEV(0, 0x14, 0);
/* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!!
* This bit has no meaning if debug strap is not enabled. So if the
* board keeps rebooting and the code fails to reach here, we could
* disable the debug strap first. */
reg8 = pmio_read(0x44+3);
reg8 |= 1 << 7;
pmio_write(0x44+3, reg8);
/* Enable lpc controller */
reg8 = pmio_read(0xEC);
reg8 |= 1 << 0;
pmio_write(0xEC, reg8);
dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */
/* Decode port 0x3f8-0x3ff (Serial 0) */
//#warning Serial port decode on LPC is hardcoded to 0x3f8
reg8 = pci_read_config8(dev, 0x44);
reg8 |= 1 << 6;
pci_write_config8(dev, 0x44, reg8);
/* Decode port 0x60 & 0x64 (PS/2 keyboard) and port 0x62 & 0x66 (ACPI)*/
reg8 = pci_read_config8(dev, 0x47);
reg8 |= (1 << 5) | (1 << 6);
pci_write_config8(dev, 0x47, reg8);
/* SuperIO, LPC ROM */
reg8 = pci_read_config8(dev, 0x48);
/* Decode ports 0x2e-0x2f, 0x4e-0x4f (SuperI/O configuration) */
reg8 |= (1 << 1) | (1 << 0);
/* Decode variable LPC ROM address ranges 1&2 (see register 0x68-0x6b, 0x6c-0x6f) */
reg8 |= (1 << 3) | (1 << 4);
/* Decode port 0x70-0x73 (RTC) */
reg8 |= 1 << 6;
pci_write_config8(dev, 0x48, reg8);
}
void sb800_clk_output_48Mhz(void)
{
/* AcpiMMioDecodeEn */
u8 reg8;
reg8 = pmio_read(0x24);
reg8 |= 1;
reg8 &= ~(1 << 1);
pmio_write(0x24, reg8);
*(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
*(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
}
static void
amdsbwd_probe_sb7xx(device_t dev, struct resource *pmres, uint32_t *addr)
{
uint32_t val;
int i;
/* Report cause of previous reset for user's convenience. */
val = pmio_read(pmres, AMDSB_PM_RESET_STATUS0);
if (val != 0)
amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val);
val = pmio_read(pmres, AMDSB_PM_RESET_STATUS1);
if (val != 0)
amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val);
if ((val & AMDSB_WD_RST_STS) != 0)
device_printf(dev, "Previous Reset was caused by Watchdog\n");
/* Find base address of memory mapped WDT registers. */
for (*addr = 0, i = 0; i < 4; i++) {
*addr <<= 8;
*addr |= pmio_read(pmres, AMDSB_PM_WDT_BASE_MSB - i);
}
/* Set watchdog timer tick to 1s. */
val = pmio_read(pmres, AMDSB_PM_WDT_CTRL);
val &= ~AMDSB_WDT_RES_MASK;
val |= AMDSB_WDT_RES_10MS;
pmio_write(pmres, AMDSB_PM_WDT_CTRL, val);
/* Enable watchdog device (in stopped state). */
val = pmio_read(pmres, AMDSB_PM_WDT_CTRL);
val &= ~AMDSB_WDT_DISABLE;
pmio_write(pmres, AMDSB_PM_WDT_CTRL, val);
/*
* XXX TODO: Ensure that watchdog decode is enabled
* (register 0x41, bit 3).
*/
device_set_desc(dev, "AMD SB600/SB7xx Watchdog Timer");
}
/*
* RPR 2.6 C-state and VID/FID change for the K8 platform.
*/
static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
{
u8 byte;
byte = pmio_read(0x80);
if (dual_core())
byte |= 1 << 2 | 1 << 1;
byte |= 1 << 3;
byte |= 1 << 4;
byte &= ~(1 << 7);
pmio_write(0x80, byte);
byte = pmio_read(0x7E);
byte |= 1 << 6;
byte &= ~(1 << 2);
pmio_write(0x7E, byte);
pmio_write(0x94, 0x01);
byte = pmio_read(0x89);
byte |= 1 << 4;
pmio_write(0x89, byte);
byte = pmio_read(0x9b);
byte &= ~(7 << 4);
byte |= 1 << 4;
pmio_write(0x9b, byte);
pmio_write(0x99, 0x10);
pmio_write(0x9A, 0x00);
pmio_write(0x96, 0x10);
pmio_write(0x97, 0x00);
byte = pmio_read(0x81);
byte &= ~(1 << 1);
pmio_write(0x81, byte);
}
void sb800_lpc_port80(void)
{
u8 byte;
device_t dev;
/* Enable LPC controller */
byte = pmio_read(0xEC);
byte |= 1 << 0;
pmio_write(0xEC, byte);
/* Enable port 80 LPC decode in pci function 3 configuration space. */
dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
byte = pci_read_config8(dev, 0x4a);
byte |= 1 << 5; /* enable port 80 */
pci_write_config8(dev, 0x4a, byte);
}
static void
amdsbwd_probe_sb8xx(device_t dev, struct resource *pmres, uint32_t *addr)
{
uint32_t val;
int i;
/* Report cause of previous reset for user's convenience. */
val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS0);
if (val != 0)
amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val);
val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS1);
if (val != 0)
amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val);
if ((val & AMDSB8_WD_RST_STS) != 0)
device_printf(dev, "Previous Reset was caused by Watchdog\n");
/* Find base address of memory mapped WDT registers. */
for (*addr = 0, i = 0; i < 4; i++) {
*addr <<= 8;
*addr |= pmio_read(pmres, AMDSB8_PM_WDT_EN + 3 - i);
}
*addr &= ~0x07u;
/* Set watchdog timer tick to 1s. */
val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL);
val &= ~AMDSB8_WDT_RES_MASK;
val |= AMDSB8_WDT_1HZ;
pmio_write(pmres, AMDSB8_PM_WDT_CTRL, val);
#ifdef AMDSBWD_DEBUG
val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL);
amdsbwd_verbose_printf(dev, "AMDSB8_PM_WDT_CTRL value = %#02x\n", val);
#endif
/*
* Enable watchdog device (in stopped state)
* and decoding of its address.
*/
val = pmio_read(pmres, AMDSB8_PM_WDT_EN);
val &= ~AMDSB8_WDT_DISABLE;
val |= AMDSB8_WDT_DEC_EN;
pmio_write(pmres, AMDSB8_PM_WDT_EN, val);
#ifdef AMDSBWD_DEBUG
val = pmio_read(pmres, AMDSB8_PM_WDT_EN);
device_printf(dev, "AMDSB8_PM_WDT_EN value = %#02x\n", val);
#endif
device_set_desc(dev, "AMD SB8xx Watchdog Timer");
}
/*
* Compliant with CIM_48's sbPciCfg.
* Add any south bridge setting.
*/
static void sb600_pci_cfg(void)
{
device_t dev;
u8 byte;
/* SMBus Device, BDF:0-20-0 */
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
/* Enable the hidden revision ID, available after A13. */
byte = pci_read_config8(dev, 0x70);
byte |= (1 << 8);
pci_write_config8(dev, 0x70, byte);
/* rpr2.20 Disable Timer IRQ Enhancement for proper operation of the 8254 timer, 0xae[5]. */
byte = pci_read_config8(dev, 0xae);
byte |= (1 << 5);
pci_write_config8(dev, 0xae, byte);
/* Enable watchdog decode timer */
byte = pci_read_config8(dev, 0x41);
byte |= (1 << 3);
pci_write_config8(dev, 0x41, byte);
/* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
* generated PCIRST#. */
byte = pmio_read(0x65);
byte |= (1 << 4);
pmio_write(0x65, byte);
/*For A13 and above. */
if (get_sb600_revision() > 0x12) {
/* rpr2.16 C-State Reset, PMIO 0x9f[7]. */
byte = pmio_read(0x9f);
byte |= (1 << 7);
pmio_write(0x9f, byte);
/* rpr2.17 PCI Clock Period will increase to 30.8ns. 0x53[7]. */
byte = pmio_read(0x53);
byte |= (1 << 7);
pmio_write(0x53, byte);
}
/* IDE Device, BDF:0-20-1 */
dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0);
/* Enable IDE Explicit prefetch, 0x63[0] clear */
byte = pci_read_config8(dev, 0x63);
byte &= 0xfe;
pci_write_config8(dev, 0x63, byte);
/* LPC Device, BDF:0-20-3 */
dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
/* rpr7.2 Enabling LPC DMA function. */
byte = pci_read_config8(dev, 0x40);
byte |= (1 << 2);
pci_write_config8(dev, 0x40, byte);
/* rpr7.3 Disabling LPC TimeOut. 0x48[7] clear. */
byte = pci_read_config8(dev, 0x48);
byte &= 0x7f;
pci_write_config8(dev, 0x48, byte);
/* rpr7.5 Disabling LPC MSI Capability, 0x78[1] clear. */
byte = pci_read_config8(dev, 0x78);
byte &= 0xfd;
pci_write_config8(dev, 0x78, byte);
/* SATA Device, BDF:0-18-0, Non-Raid-5 SATA controller */
dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0);
/* rpr6.8 Disabling SATA MSI Capability, for A13 and above, 0x42[7]. */
if (0x12 < get_sb600_revision()) {
u32 reg32;
reg32 = pci_read_config32(dev, 0x40);
reg32 |= (1 << 23);
pci_write_config32(dev, 0x40, reg32);
}
/* EHCI Device, BDF:0-19-5, ehci usb controller */
dev = pci_locate_device(PCI_ID(0x1002, 0x4386), 0);
/* rpr5.10 Disabling USB EHCI MSI Capability. 0x50[6]. */
byte = pci_read_config8(dev, 0x50);
byte |= (1 << 6);
pci_write_config8(dev, 0x50, byte);
/* OHCI0 Device, BDF:0-19-0, ohci usb controller #0 */
dev = pci_locate_device(PCI_ID(0x1002, 0x4387), 0);
/* rpr5.11 Disabling USB OHCI MSI Capability. 0x40[12:8]=0x1f. */
byte = pci_read_config8(dev, 0x41);
byte |= 0x1f;
pci_write_config8(dev, 0x41, byte);
}
/* sbPmioPorInitTable, Pre-initializing PMIO register space
* The power management (PM) block is resident in the PCI/LPC/ISA bridge.
* The PM regs are accessed via IO mapped regs 0xcd6 and 0xcd7.
* The index address is first programmed into IO reg 0xcd6.
* Read or write values are accessed through IO reg 0xcd7.
*/
static void sb600_pmio_por_init(void)
{
u8 byte;
printk(BIOS_INFO, "sb600_pmio_por_init()\n");
/* K8KbRstEn, KB_RST# control for K8 system. */
byte = pmio_read(0x66);
byte |= 0x20;
pmio_write(0x66, byte);
/* RPR2.3.4 S3/S4/S5 Function for the K8 Platform. */
byte = pmio_read(0x52);
byte &= 0xc0;
byte |= 0x08;
pmio_write(0x52, byte);
/* C state enable and SLP enable in C states. */
byte = pmio_read(0x67);
byte |= 0x6;
pmio_write(0x67, byte);
/* CIM sets 0x0e, but bit2 is for P4 system. */
byte = pmio_read(0x68);
byte &= 0xf0;
byte |= 0x0c;
pmio_write(0x68, byte);
/* Watch Dog Timer Control
* Set watchdog time base to 0xfec000f0 to avoid SCSI card boot failure.
* But I don't find WDT is enabled in SMBUS 0x41 bit3 in CIM.
*/
pmio_write(0x6c, 0xf0);
pmio_write(0x6d, 0x00);
pmio_write(0x6e, 0xc0);
pmio_write(0x6f, 0xfe);
/* rpr2.14: Enables HPET periodical mode */
byte = pmio_read(0x9a);
byte |= 1 << 7;
pmio_write(0x9a, byte);
byte = pmio_read(0x9f);
byte |= 1 << 5;
pmio_write(0x9f, byte);
byte = pmio_read(0x9e);
byte |= (1 << 6) | (1 << 7);
pmio_write(0x9e, byte);
/* rpr2.14: Hides SM bus controller Bar1 where stores HPET MMIO base address */
/* We have to clear this bit here, otherwise the kernel hangs. */
byte = pmio_read(0x55);
byte |= 1 << 7;
byte |= 1 << 1;
pmio_write(0x55, byte);
/* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridge */
byte = pmio_read(0x52);
byte |= 1 << 6;
pmio_write(0x52, byte);
/* rpr2.22: PLL Reset */
byte = pmio_read(0x86);
byte |= 1 << 7;
pmio_write(0x86, byte);
/* rpr2.3.3 */
/* This provides 16us delay before the assertion of LDTSTP# when C3 is entered.
* The delay will allow USB DMA to go on in a continuous manner
*/
pmio_write(0x89, 0x10);
/* Set this bit to allow pop-up request being latched during the minimum LDTSTP# assertion time */
byte = pmio_read(0x52);
byte |= 1 << 7;
pmio_write(0x52, byte);
/* rpr2.15: ASF Remote Control Action */
byte = pmio_read(0x9f);
byte |= 1 << 6;
pmio_write(0x9f, byte);
/* rpr2.19: Enabling Spread Spectrum */
byte = pmio_read(0x42);
byte |= 1 << 7;
pmio_write(0x42, byte);
}
/* sbDevicesPorInitTable */
static void sb800_devices_por_init(void)
{
device_t dev;
u8 byte;
printk(BIOS_INFO, "sb800_devices_por_init()\n");
/* SMBus Device, BDF:0-20-0 */
printk(BIOS_INFO, "sb800_devices_por_init(): SMBus Device, BDF:0-20-0\n");
dev = PCI_DEV(0, 0x14, 0);//pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
if (dev == PCI_DEV_INVALID) {
die("SMBUS controller not found\n");
/* NOT REACHED */
}
printk(BIOS_INFO, "SMBus controller enabled, sb revision is A%x\n",
get_sb800_revision());
/* sbPorAtStartOfTblCfg */
/* rpr 4.1.Set A-Link bridge access address.
* This is an I/O address. The I/O address must be on 16-byte boundry. */
//pci_write_config32(dev, 0xf0, AB_INDX);
pmio_write(0xE0, AB_INDX & 0xFF);
pmio_write(0xE1, (AB_INDX >> 8) & 0xFF);
pmio_write(0xE2, (AB_INDX >> 16) & 0xFF);
pmio_write(0xE3, (AB_INDX >> 24) & 0xFF);
/* To enable AB/BIF DMA access, a specific register inside the BIF register space needs to be configured first. */
/* 4.2:Enables the SB800 to send transactions upstream over A-Link Express interface. */
axcfg_reg(0x04, 1 << 2, 1 << 2);
//axindxc_reg(0x21, 0xff, 0);
/* 4.15:Enabling Non-Posted Memory Write for the K8 Platform */
axindxc_reg(0x10, 1 << 9, 1 << 9);
/* END of sbPorAtStartOfTblCfg */
/* sbDevicesPorInitTables */
/* set smbus iobase */
//pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
/* The base address of SMBUS is set in a different way with sb700. */
byte = (SMBUS_IO_BASE & 0xFF) | 1;
pmio_write(0x2c, byte & 0xFF);
pmio_write(0x2d, SMBUS_IO_BASE >> 8);
/* AcpiMMioDecodeEn */
byte = pmio_read(0x24);
byte |= 1;
byte &= ~(1 << 1);
pmio_write(0x24, byte);
/* enable smbus controller interface */
//byte = pci_read_config8(dev, 0xd2);
//byte |= (1 << 0);
//pci_write_config8(dev, 0xd2, byte);
/* KB2RstEnable */
//pci_write_config8(dev, 0x40, 0x44);
/* Enable ISA Address 0-960K decoding */
//pci_write_config8(dev, 0x48, 0x0f);
/* Enable ISA Address 0xC0000-0xDFFFF decode */
//pci_write_config8(dev, 0x49, 0xff);
/* Enable decode cycles to IO C50, C51, C52 GPM controls. */
//byte = pci_read_config8(dev, 0x41);
//byte &= 0x80;
//byte |= 0x33;
//pci_write_config8(dev, 0x41, byte);
/* Legacy DMA Prefetch Enhancement, CIM masked it. */
/* pci_write_config8(dev, 0x43, 0x1); */
/* clear any lingering errors, so the transaction will run */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
/* IDE Device, BDF:0-20-1 */
printk(BIOS_INFO, "sb800_devices_por_init(): IDE Device, BDF:0-20-1\n");
dev = PCI_DEV(0, 0x14, 1);//pci_locate_device(PCI_ID(0x1002, 0x439C), 0);
/* Disable prefetch */
byte = pci_read_config8(dev, 0x63);
byte |= 0x1;
pci_write_config8(dev, 0x63, byte);
/* LPC Device, BDF:0-20-3 */
printk(BIOS_INFO, "sb800_devices_por_init(): LPC Device, BDF:0-20-3\n");
dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
/* DMA enable */
pci_write_config8(dev, 0x40, 0x04);
/* LPC Sync Timeout */
pci_write_config8(dev, 0x49, 0xFF);
/* Set LPC ROM size, it has been done in sb800_lpc_init().
* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB;
* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB
* pci_write_config16(dev, 0x68, 0x000e)
* pci_write_config16(dev, 0x6c, 0xfff0);*/
/* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */
pci_write_config8(dev, 0x7C, 0x05);
/* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
*/
printk(BIOS_INFO, "sb800_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
dev = PCI_DEV(0, 0x14, 4);//pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
/* Arbiter enable. */
pci_write_config8(dev, 0x43, 0xff);
/* Set PCDMA request into hight priority list. */
/* pci_write_config8(dev, 0x49, 0x1) */ ;
pci_write_config8(dev, 0x40, 0x26);
pci_write_config8(dev, 0x0d, 0x40);
pci_write_config8(dev, 0x1b, 0x40);
/* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */
pci_write_config8(dev, 0x50, 0x01);
/* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */
printk(BIOS_INFO, "sb800_devices_por_init(): SATA Device, BDF:0-18-0\n");
dev = PCI_DEV(0, 0x11, 0);//pci_locate_device(PCI_ID(0x1002, 0x4390), 0);
/*PHY Global Control*/
pci_write_config16(dev, 0x86, 0x2C00);
}
/*
* Compliant with CIM_48's sbPciCfg.
* Add any south bridge setting.
*/
static void sb700_pci_cfg()
{
device_t dev;
u8 byte;
/* SMBus Device, BDF:0-20-0 */
//dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
dev = _pci_make_tag(0, 20, 0);
#if 1
/* Enable watchdog decode timer */
printk_info("enable watchdog decode timer\n");
byte = pci_read_config8(dev, 0x41);
byte |= (1 << 3);
pci_write_config8(dev, 0x41, byte);
/* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
* generated PCIRST#. */
byte = pmio_read(0x65);
byte |= (1 << 4);
pmio_write(0x65, byte);
#endif
/* IDE Device, BDF:0-20-1 */
//dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0);
dev = _pci_make_tag(0, 20, 1);
/* Enable IDE Explicit prefetch, 0x63[0] clear */
printk_info("enable IDE explicit prefetch\n");
byte = pci_read_config8(dev, 0x63);
byte &= 0xfe;
pci_write_config8(dev, 0x63, byte);
/* LPC Device, BDF:0-20-3 */
//dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
dev = _pci_make_tag(0, 20, 3);
/* rpr7.2 Enabling LPC DMA function. */
printk_info("enabling lpc dma function\n");
byte = pci_read_config8(dev, 0x40);
byte |= (1 << 2);
pci_write_config8(dev, 0x40, byte);
/* rpr7.3 Disabling LPC TimeOut. 0x48[7] clear. */
printk_info("disable lpc timeout\n");
byte = pci_read_config8(dev, 0x48);
byte &= 0x7f;
pci_write_config8(dev, 0x48, byte);
/* rpr7.5 Disabling LPC MSI Capability, 0x78[1] clear. */
printk_info("disable LPC MSI Capability\n");
byte = pci_read_config8(dev, 0x78);
byte &= 0xfd;
pci_write_config8(dev, 0x78, byte);
#ifdef ENABLE_SATA
/* SATA Device, BDF:0-18-0, Non-Raid-5 SATA controller */
//dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0);
dev = _pci_make_tag(0, 17, 0);
/* rpr7.12 SATA MSI and D3 Power State Capability.
* TODO: We assume S1 is supported. What if it isn't support? */
byte = pci_read_config8(dev, 0x40);
byte |= 1 << 0;
pci_write_config8(dev, 0x40, byte);
if (get_sb700_revision() <= 0x12)
pci_write_config8(dev, 0x34, 0x70);
else
pci_write_config8(dev, 0x34, 0x50);
byte &= ~(1 << 0);
pci_write_config8(dev, 0x40, byte);
#endif
/* TODO: There are several pairs of USB devices.
* Two 4396s, two 4397s, two 4398s.
* The code below only set one of each two. The other
* will be done in sb700_usb.c after all.
* So we don't take the trouble to set them both. */
/* EHCI Device, BDF:0-19-2, ehci usb controller */
//dev = pci_locate_device(PCI_ID(0x1002, 0x4396), 0);
dev = _pci_make_tag(0, 19, 2);
/* rpr6.16 Disabling USB EHCI MSI Capability. 0x50[6]. */
byte = pci_read_config8(dev, 0x50);
byte |= (1 << 6);
pci_write_config8(dev, 0x50, byte);
//lycheng add disabling usb ohci and ehci msi capability
/* EHCI Device, BDF:0-18-2, ehci usb controller */
//dev = pci_locate_device(PCI_ID(0x1002, 0x4396), 0);
dev = _pci_make_tag(0, 18, 2);
/* rpr6.16 Disabling USB EHCI MSI Capability. 0x50[6]. */
byte = pci_read_config8(dev, 0x50);
byte |= (1 << 6);
pci_write_config8(dev, 0x50, byte);
/* OHCI0 Device, BDF:0-19-0, ohci usb controller #0 */
//dev = pci_locate_device(PCI_ID(0x1002, 0x4387), 0);
dev = _pci_make_tag(0, 19, 0);
/* rpr5.11 Disabling USB OHCI MSI Capability. 0x40[12:8]=0x1f. */
printk_info("disable USB OHCI MSI Capability\n");
byte = pci_read_config8(dev, 0x41);
byte |= 0x3;
pci_write_config8(dev, 0x41, byte);
dev = _pci_make_tag(0, 18, 0);
/* rpr5.11 Disabling USB OHCI MSI Capability. 0x40[12:8]=0x1f. */
printk_info("disable USB OHCI MSI Capability\n");
byte = pci_read_config8(dev, 0x41);
byte |= 0x3;
pci_write_config8(dev, 0x41, byte);
/* OHCI0 Device, BDF:0-19-1, ohci usb controller #0 */
//dev = pci_locate_device(PCI_ID(0x1002, 0x4398), 0);
dev = _pci_make_tag(0, 19, 1);
byte = pci_read_config8(dev, 0x41);
byte |= 0x3;
pci_write_config8(dev, 0x41, byte);
dev = _pci_make_tag(0, 18, 1);
byte = pci_read_config8(dev, 0x41);
byte |= 0x3;
pci_write_config8(dev, 0x41, byte);
/* OHCI0 Device, BDF:0-20-5, ohci usb controller #0 */
//dev = pci_locate_device(PCI_ID(0x1002, 0x4399), 0);
dev = _pci_make_tag(0, 20, 5);
byte = pci_read_config8(dev, 0x41);
byte |= 0x3;
pci_write_config8(dev, 0x41, byte);
}
void sb700_pmio_por_init(void)
{
u8 byte;
#if 1
printk_info("sb700_pmio_por_init()\n");
/* K8KbRstEn, KB_RST# control for K8 system. */
byte = pmio_read(0x66);
byte |= 0x20;
pmio_write(0x66, byte);
/* RPR2.31 PM_TURN_OFF_MSG during ASF Shutdown. */
if (get_sb700_revision() <= 0x12) {
byte = pmio_read(0x65);
byte &= ~(1 << 7);
pmio_write(0x65, byte);
byte = pmio_read(0x75);
byte &= 0xc0;
byte |= 0x05;
pmio_write(0x75, byte);
byte = pmio_read(0x52);
byte &= 0xc0;
byte |= 0x08;
pmio_write(0x52, byte);
} else {
byte = pmio_read(0xD7);
byte |= 1 << 0;
pmio_write(0xD7, byte);
byte = pmio_read(0x65);
byte |= 1 << 7;
pmio_write(0x65, byte);
byte = pmio_read(0x75);
byte &= 0xc0;
byte |= 0x01;
pmio_write(0x75, byte);
byte = pmio_read(0x52);
byte &= 0xc0;
byte |= 0x02;
pmio_write(0x52, byte);
}
pmio_write(0x6c, 0xf0);
pmio_write(0x6d, 0x00);
pmio_write(0x6e, 0xc0);
pmio_write(0x6f, 0xfe);
/* rpr2.19: Enabling Spread Spectrum */
printk_info("Enabling Spread Spectrum\n");
byte = pmio_read(0x42);
byte |= 1 << 7;
pmio_write(0x42, byte);
/* TODO: Check if it is necessary. IDE reset */
byte = pmio_read(0xB2);
byte |= 1 << 0;
pmio_write(0xB2, byte);
#endif
}
// TechNexion's Post Code Initially.
void technexion_post_code_init(void)
{
uint8_t reg8_data;
device_t dev = 0;
// SMBus Module and ACPI Block (Device 20, Function 0)
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM), 0);
// LED[bit0]:GPIO0
// This is reference SB600 RRG 4.1.1 GPIO
reg8_data = pmio_read(0x60);
reg8_data |= (1 << 7); // 1: GPIO if not used by SATA
pmio_write(0x60, reg8_data);
reg8_data = pci_read_config8(dev, 0x80);
reg8_data = ((reg8_data | (1 << 0)) & ~(1 << 4));
pci_write_config8(dev, 0x80, reg8_data);
// LED[bit1]:GPIO1
// This is reference SB600 RRG 4.1.1 GPIO
reg8_data = pci_read_config8(dev, 0x80);
reg8_data = ((reg8_data | (1 << 1)) & ~(1 << 5));
pci_write_config8(dev, 0x80, reg8_data);
// LED[bit2]:GPIO4
// This is reference SB600 RRG 4.1.1 GPIO
reg8_data = pmio_read(0x5e);
reg8_data &= ~(1 << 7); // 0: GPIO if not used by SATA
pmio_write(0x5e, reg8_data);
reg8_data = pci_read_config8(dev, 0xa8);
reg8_data |= (1 << 0);
pci_write_config8(dev, 0xa8, reg8_data);
reg8_data = pci_read_config8(dev, 0xa9);
reg8_data &= ~(1 << 0);
pci_write_config8(dev, 0xa9, reg8_data);
// LED[bit3]:GPIO6
// This is reference SB600 RRG 4.1.1 GPIO
reg8_data = pmio_read(0x60);
reg8_data |= (1 << 7); // 1: GPIO if not used by SATA
pmio_write(0x60, reg8_data);
reg8_data = pci_read_config8(dev, 0xa8);
reg8_data |= (1 << 2);
pci_write_config8(dev, 0xa8, reg8_data);
reg8_data = pci_read_config8(dev, 0xa9);
reg8_data &= ~(1 << 2);
pci_write_config8(dev, 0xa9, reg8_data);
// LED[bit4]:GPIO7
// This is reference SB600 RRG 4.1.1 GPIO
reg8_data = pci_read_config8(dev, 0xa8);
reg8_data |= (1 << 3);
pci_write_config8(dev, 0xa8, reg8_data);
reg8_data = pci_read_config8(dev, 0xa9);
reg8_data &= ~(1 << 3);
pci_write_config8(dev, 0xa9, reg8_data);
// LED[bit5]:GPIO8
// This is reference SB600 RRG 4.1.1 GPIO
reg8_data = pci_read_config8(dev, 0xa8);
reg8_data |= (1 << 4);
pci_write_config8(dev, 0xa8, reg8_data);
reg8_data = pci_read_config8(dev, 0xa9);
reg8_data &= ~(1 << 4);
pci_write_config8(dev, 0xa9, reg8_data);
// LED[bit6]:GPIO10
// This is reference SB600 RRG 4.1.1 GPIO
reg8_data = pci_read_config8(dev, 0xab);
reg8_data = ((reg8_data | (1 << 0)) & ~(1 << 1));
pci_write_config8(dev, 0xab, reg8_data);
// LED[bit7]:GPIO66
// This is reference SB600 RRG 4.1.1 GPIO
reg8_data = pmio_read(0x68);
reg8_data &= ~(1 << 5); // 0: GPIO
pmio_write(0x68, reg8_data);
reg8_data = pci_read_config8(dev, 0x7e);
reg8_data = ((reg8_data | (1 << 1)) & ~(1 << 5));
pci_write_config8(dev, 0x7e, reg8_data);
}