static void INLINE ks7037_update(void) {
WORD value;
// 0x7000
value = 0x0F;
control_bank(info.prg.rom[0].max.banks_4k)
ks7037_prg_7000 = prg_chip_byte_pnt(0, value << 12);
// 0x8000 - 0x9000
value = ks7037.reg[6];
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 0, value);
prg.rom_8k[0] = prg_chip_byte_pnt(prg.rom_chip[0], mapper.rom_map_to[0] << 13);
// 0xA000
value = 0xFC;
control_bank(info.prg.rom[0].max.banks_4k)
prg.rom_8k[1] = prg_chip_byte_pnt(prg.rom_chip[0], value << 12);
// 0xB000
ks7037_prg_B000 = &prg.ram_plus_8k[1 << 12];
// 0xC000 - 0xD000
value = ks7037.reg[7];
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 2, value);
prg.rom_8k[2] = prg_chip_byte_pnt(prg.rom_chip[0], mapper.rom_map_to[2] << 13);
// mirroring
ntbl.bank_1k[0] = &ntbl.data[(ks7037.reg[2] & 0x01) * 0x400];
ntbl.bank_1k[1] = &ntbl.data[(ks7037.reg[4] & 0x01) * 0x400];
ntbl.bank_1k[2] = &ntbl.data[(ks7037.reg[3] & 0x01) * 0x400];
ntbl.bank_1k[3] = &ntbl.data[(ks7037.reg[5] & 0x01) * 0x400];
}
void extcl_cpu_wr_mem_BB(WORD address, BYTE value) {
BYTE save = value;
DBWORD bank;
if ((address & 0x9000) == 0x8000) {
value = value & 0x03;
control_bank(info.prg.rom[0].max.banks_8k)
bb_prg_6000 = prg_chip_byte_pnt(0, value << 13);
bb.reg = value;
value = save;
} else {
value = value & 0x01;
}
control_bank(info.chr.rom[0].max.banks_8k);
bank = value << 13;
chr.bank_1k[0] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[1] = chr_chip_byte_pnt(0, bank | 0x0400);
chr.bank_1k[2] = chr_chip_byte_pnt(0, bank | 0x0800);
chr.bank_1k[3] = chr_chip_byte_pnt(0, bank | 0x0C00);
chr.bank_1k[4] = chr_chip_byte_pnt(0, bank | 0x1000);
chr.bank_1k[5] = chr_chip_byte_pnt(0, bank | 0x1400);
chr.bank_1k[6] = chr_chip_byte_pnt(0, bank | 0x1800);
chr.bank_1k[7] = chr_chip_byte_pnt(0, bank | 0x1C00);
}
void map_prg_rom_8k_update(void) {
BYTE i;
for (i = 0; i < 4; ++i) {
prg.rom_8k[i] = prg_chip_byte_pnt(0, mapper.rom_map_to[i] << 13);
}
}
BYTE extcl_save_mapper_BB(BYTE mode, BYTE slot, FILE *fp) {
save_slot_ele(mode, slot, bb.reg);
if (mode == SAVE_SLOT_READ) {
bb_prg_6000 = prg_chip_byte_pnt(0, bb.reg << 13);
}
return (EXIT_OK);
}
void map_init_BB(void) {
EXTCL_CPU_WR_MEM(BB);
EXTCL_CPU_RD_MEM(BB);
EXTCL_SAVE_MAPPER(BB);
mapper.internal_struct[0] = (BYTE *) &bb;
mapper.internal_struct_size[0] = sizeof(bb);
{
BYTE value = 0xFF;
control_bank(info.prg.rom[0].max.banks_32k)
map_prg_rom_8k(4, 0, value);
}
bb.reg = 0xFF;
_control_bank(bb.reg, info.prg.rom[0].max.banks_8k)
bb_prg_6000 = prg_chip_byte_pnt(0, bb.reg << 13);
}
void extcl_cpu_wr_mem_186(WORD address, BYTE value) {
if ((address < 0x4200) || (address > 0x4EFF)) {
return;
}
if (address > 0x43FF) {
prg.ram.data[address & 0x0BFF] = value;
return;
}
switch (address & 0x0001) {
case 0x0000:
value >>= 6;
control_bank(info.prg.rom.max.banks_8k)
m186.prg_ram_bank2 = prg_chip_byte_pnt(0, value << 13);
return;
case 0x0001:
control_bank(info.prg.rom.max.banks_16k)
map_prg_rom_8k(2, 0, value);
map_prg_rom_8k_update();
return;
}
}
